TAO1221 Computer Architecture and Organization Tutorial 3 & 4

INSTRUCTION SET OF 8085 MICROPROCESSOR

To Study

• Complete Instruction Set of 8085 Microprocessor with the following

categories

- Data Transfer Group

- Arithmetic Group ( Increment/Decrement (6), Addition(7), Subtraction (6),

Special (1))

- Logical Group (AND (3), OR (3), XOR(3), COMPARE(3), COMPLEMENT(1),

CARRY MANIPULATION(2) , ROTATE (4))

- Branch Group (Jump (3), subroutine related (4), restart(1))

- Input/Output (2), Stack operations (6) and Machine control (2) group

Page 1 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

DATA TRANSFER (COPY) OPERATIONS:

One of the primary functions of the microprocessor is copying data, from a

register or I/O or memory called the source, to another register or I/O or memory called
the destination. In technical literature, the copying function is frequently labeled as the
data transfer function, which is somewhat misleading. In fact, the contents of the source
are not transferred, but are copied into the destination register without modifying the
contents of the source.

This group consists of the following set of instructions:

1. MVI r, data (Move data immediate to register r)

( r can be any one of A/B/C/D/E/H/L registers)
This instruction directly loads a single register with a single byte of data that follows
the opcode.

Example: MVI B, 45H - This instruction loads register B with the 8 bit data
45H (Note that here H represents hexadecimal)

2. MVI M, data (Move data immediate to memory location whose address is in HL

register pair)
M represents ((HL))

This instruction directly stores the data that follows the opcode in the memory location
specified by the contents of the H and L registers.

Example: MVI M, 65H

Explanation: Suppose HL register pair contains 8000H , the data 65 H is loaded in the
memory location 8000H.

3. MOV rl,r2 (Move data from register to register; r2 to rl, r2 is the source and r1
is the destination)

(r1 and r2 can be any one of A/B/C/D/E/H/L registers)

This instruction transfers the contents of one register to another register.

Example: MOV B, C
Explanation: Copy the contents of Register C to Register B. C reg. Is the
source and B reg. Is destination

Page 2 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

4. MOV M, r (Move data from register r to memory whose address is in H and L)

r can be any one of A/B/C/D/E/H/L registers and M represents ((HL))

This instruction transfers data from the source register to a memory location,
address of which is pointed to by H and L registers.

Example: MOV M, B
Explanation: Suppose HL register contains 6000H, this instruction will copy the
contents of Register B to memory location 6000H.

5. MOV r, M (Move data from location specified by H and L registers to register r)

r can be any one of A/B/C/D/E/H/L registers and M represents ((HL))

This instruction transfers data from a memory location whose address is in H and L
registers to the destination register r.

Example: MOV L, M
Explanation: Suppose HL register contains 7050H and memory location 7050H
contains 80H, L register will contain 80H after the execution of instruction

6. LXI rp, data (Load register pair with 16 bit data)

rp can be BC,DE,HL register pairs or stack pointer register (SP)

This instruction loads immediately the double byte or 16 bit data into a register pair
or into the SP register.

Example: LXI H, 8000H

Explanation: After the execution of the instruction, HL register pair contains the
16 -bit data 8000H

7. STA 16bit address (Store data from Accumulator to the memory location
address which follows)
This stores the contents of the accumulator in the memory, the address of which is
specified.

Example: STA 6080H

Explanation: Suppose Accumulator contains 67H, after the execution of the
instruction, 6080H memory location also contains 67H

Page 3 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

8. LDA 16bit address (Load data into accumulator from the memory location, the
address of which follows)
This instruction copies the contents of the memory location given by the address
onto the accumulator
Example: LDA 8000H

Explanation: Suppose 8000H contains 98H, after the execution of the instruction,
Accumulator will contains 98H

9. SHLD 16bit address (Store H and L direct)

The contents of the register L is stored in the memory location corresponding to the
address given and the contents of register H at the next address location

Example: SHLD 7000H

Explanation: Suppose H register contains 56H and L register contains 89H, after
the execution of the instruction, 7000H memory location will contain 89H and 7001H
memory location will contain 56H

10. LHLD 16bit address (Load H and L direct)

This instruction copies the contents of the memory location given by the address
onto the register L and the contents of the next address location onto register H.

Example: LHLD 8050H

Explanation: Suppose 8050 H memory location contains 77H and 8051H memory
location contains 88H, after the execution of the instruction, L register will contain
77H and H register will contain 88H

11. LDAX rp (Load A with the contents of the memory location whose address is in
rp)
Here rp indicates BC or DE register pair.

This instruction copies onto the accumulator the contents of the memory location
whose address is given by the contents of register pair

Example: LDAX D
Explanation: Suppose DE register pair contains 8900H and 8900H memory location
contains 78H , after the execution of the instruction, Accumulator will contain 78H

Page 4 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

12. STAX rp (Store contents of Accumulator indirect)

Here rp indicates BC or DE register pair.

This instruction stores the contents of the accumulator at the memory location
whose address is given by register pair (BC or DE only)

Example: STAX B
Explanation: Suppose BC register pair contains 5000H and accumulator contains
the 8 bit data 87H, then after the execution of the instruction, memory location
5000H will contain 87H

13. XCHG (Exchange register pair contents)

This instruction exchanges the contents of the register H with that of D and of L with
that of E.

Example: XCHG
Explanation: Suppose HL register contains 8678H and DE register contains 9876H,
then after the execution of the instruction, HL register will contain 9876H and DE
register will contain 8678H.

Page 5 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

ARITHMETIC GROUP
I. INCREMENT/DECREMENT:

14. INR r (Increment Register)

Here r indicates A/B/C/D/E/H/L register

The contents of the specified register are incremented by one. All flags except carry
are affected.

Example: INR D
Explantion: Suppose Reg. D contains FFH , after the execution of the instruction D
reg. Will contain 00H and Zero flag, sign flag, parity flag will be set. Carry flag will
not be affected and it remains in the previous state.

15. INR M (Increment data in memory)

Here M= ((HL))

The contents of the memory location whose address is in HL are incremented by

one. All flags except carry are affected.

Example: INR M
Explanation: Suppose HL register pair contains 8000H and memory location 8000
H contains 8 bit data 45H, then after the execution of the instruction, memory
location 8000H will contain 46H.

16. INX rp (Increment register pair)

rp represents BC,DE,HL,SP

The contents of the specified register pair are incremented by one. No flags are
affected.

Example: INX H
Explanation: Suppose HL register pair contains 899FH, after the execution of the
instruction, HL register will contain 89A0H.

17. DCR r (Decrement register)

r represents A/B/C/D/E/H/L register

The contents of the specified register are decremented by one. All flags except carry
are affected.

Example: DCR A
Explanation: Suppose accumulator contains 88H, then after the execution of the
instruction, accumulator will contain 87H. Zero flag will be reset. Sign, Parity, and
auxillary carry flag will be set. Carry flag will remain at the previous state.

Page 6 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

18. DCR M (Decrement data in memory)

M represents ((HL))

The contents of the memory location whose address is in HL are decremented by

one. All flags except carry are affected.

Example: DCR M
Explanation: Suppose HL register pair contains 8000H and 8000H memory location
contains 00H, then after the execution of the instruction, 8000H memory location will
contain FFH. Sign and parity flags will be set. Zero flag will be reset. Carry flag will
not be affected

19. DCX rp (Decrement register pair)

Here rp represents one of BC, DE, HL register pairs or SP (Stack pointer register)

The contents of the specified register pair are decremented by one. No flags are
affected.

Example: DCX SP
Explanation: Suppose stack pointer contains FFFFH, after the execution of the
instruction, SP will contain FFFEH.

II.ADDITION related Instructions:

20. ADD r (Add register r to A) r can be any one of the 8 bit registers -A/B/C/D/E/H/L

The contents of the specified register are added to the contents of the accumulator.
The result is stored in the accumulator. All flags are affected according to the result
in accumulator.

Example: ADD C
Explanation: Suppose A register contains 67H and C register contains FEH, then
after the execution of the instruction, reg. A contains 65H. Carry flag, Auxillary Carry
flag and parity flag will be set. Zero and sign flags will be reset.

21. ADD M (Add data in memory to A) M is ((HL))

The contents of the memory location whose address is in HL are added to the
accumulator. All flags are affected according to the result.

Example: ADD M
Explanation: Suppose Accumulator contains 01H and HL register pair contains
4098H and the contents of memory locations 4098H is FFH, then after the
execution of the instruction, Accumulator will contain 00H,.Carry,zero,auxillary
carry, parity flags will be set and sign flag will be reset.

Page 7 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

22. ADI data (Add data immediate to A)

The data given in the second byte of the instruction is added to the contents of
accumulator and the result is stored in the accumulator. All flags are affected.

Example: ADI 95H

Explanation: Suppose accumulator contains 29H, then after the execution of the
instruction, accumulator will contain BEH. Sign, parity flags will be set. Carry,
auxillary carry and zero flags will be reset.

23. ADC r (Add register r (A/B/C/D/E/H/L) with carry to accumulator)

If the carry flag is set by some previous operation, is adds 1 and the contents of
register r to A, else it adds the contents of r only. The result remains in the
accumulator and all flags are affected according to the result.

Example: ADC D
Explanation: Suppose accumulator contains 88H and D register contains 98H and
carry flag is set previous to the execution of the instruction, then after the execution,
accumulator will contain 21H.Carry,Auxillary carry,Parity flags will be set and
Zero,sign flags will be reset.

24. ADC M (Add data in memory to A with carry) M is ((HL))

If the carry flag is set by some previous operation, it adds 1 and the contents of the
memory location whose address is in HL to A, else it adds the memory contents
only. The result remains in the accumulator. All flags are affected.

Example: ADC M
Explanation: Suppose accumulator contains 34H, HL register contains 8000H and
memory location 8000H contains CB H , then after the execution of the instruction,
accumulator ( ((HL))+01H+(A) ) will contain 00H. Carry, Auxillary carry, Parity,
Zero flags will be set and Sign flag will be reset.

25. ACI data (Add immediate data to A with carry)

If the carry flag is set, then it adds 1 and the given 8 bit data as part of second byte
of the instruction to accumulator, else it adds only the given data. The result remains
in accumulator. All flags are affected.

Example: ACI 88H

Explanation: Suppose accumulator contains FFH and carry flag is reset before
execution of the instruction, then after the execution, accumulator will contain 87H.
Carry, Auxillary carry, Sign, Parity flags will be set and Zero flag will be reset.

Page 8 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

26. DAD rp (Add register pair (BC/DE/HL/SP) to HL )

The contents of the specified register pair is added to HL register pair. The result
remains in HL. Only the carry flag is affected.

Example: DAD B
Explanation: Suppose BC register pair contains 7000H and HL register pair
contains 9000H then after the execution of the instruction, HL register pair will
contain 0000H and carry flag will be set. Zero, sign, pairty, auxillary carry flags will
remain in the previous state.

III.SUBTRACTION RELATED INSTRUCTIONS:

27. SUB r (Subtract register r from accumulator)

The contents of the specified register (A/B/C/D/E/H/L) are subtracted from

accumulator. If A is less than r, the carry(in case of subtraction the same flag is used
as borrow) flag is set. The result of subtraction will remain in accumulator. All flags
are affected.

Example: SUB A
Explanation: This is one of the instructions which will be used for clearing the
accumulator contents. Suppose accumulator contains EEH, then after the execution
of the instruction accumulator will contain 00H. Zero,Parity flags will be set and
Sign,Auxillary carry and Borrow (carry) flags will be reset.

28. SUB M (Subtract data in memory from A)

The contents of the memory location whose address is in HL are subtracted from
Accumulator. If A is less than the memory data, the borrow(carry) flag is set. The
result remains in accumulator. All flags are affected.

Example: SUB M
Explanation: Suppose accumulator contains 88H, HL register pair contains F000H
and memory location F000H contains A0H, then after the execution of the
instruction, accumulator will contain E8H. Borrow(carry), Sign, Parity flags will be set
and Zero, Auxillary carry flags will be reset.

29. SUI data (Subtract immediate from A)

The given data is subtracted from A. If A is less than the data, the borrow (carry) flag
is set. The result remains in A. All flags are affected.

Example: SUI 50H

Explanation: Suppose accumulator contains 20H, then after the execution of the
instruction, accumulator will contain E0H. Borrow(carry), Sign flags will be set and
Parity, Auxillary Carry , Zero flags will be reset.
Page 9 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

30. SBB r (Subtract register r from A with borrow)

The contents of the specified register are subtracted from A along with borrow. If the
carry flag is set by some previous operation, then 1 plus the contents of r are
subtracted from A, else only the contents of r are subtracted. The result remains in
accumulator. All flags are affected

Example: SBB H
Explanation: Suppose accumulator contains 45H, H register contains 44H and the
carry (borrow) flag is set, then after the execution of the instruction, accumulator will
contain 00H, Zero, Parity, Auxillary carry flags will be set and Sign, Carry (borrow)
flags will be reset.

31. SBB M (Subtract memory data from A with borrow)

The contents of the memory location whose address is in HL are subtracted from A
along with borrow. If the carry flag is set by some previous operation, then 1 plus the
memory contents are subtracted from A, else only the memory contents are
subtracted. The result remains in A. All flags are affected.

Example: SBB M
Explanation: Suppose accumulator contains FFH, HL register pair contains 4000H,
memory locations contains 00H and carry flag is set, then after the execution of the
instruction, accumulator will contain FEH. Sign, Auxillary carry flags will be set and
Carry (Borrow), Parity , Zero flags will be reset.

32. SBI data (Subtract immediate data from A with borrow)

The given data as a part of the instruction is subtracted from A with borrow. If the
carry flag is set by some previous operation, then 1 plus the data are subtracted
from A, else only the given data is subtracted from A. The result remains in A. All
flags are affected.

Example: SBI 87H

Explanation: Suppose accumulator contains FFH and the carry (borrow) flag is
reset, then after the execution of the instruction, accumulator will contain 78H.
Parity, Auxillary Carry flags will be set and Zero, Sign, Carry (Borrow) flags will be
reset.

Page 10 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

IV. Special ADD instruction:

33. DAA (Decimal Adjust Accumulator)

This adjusts A to packed BCD (Binary Coded Decimal) after addition of two BCDs. It
functions in two steps:
1. If the lower 4-bits of A are greater than 9 or the auxillary carry
flag is set, then it adds 06H to A.
2. Subsequently, if the higher 4-bits of A are now greater than 9 or
the carry flag is set, it adds 60H to A.
This affects all flags.

Note:

The instruction DAA

- adjusts a BCD sum

- does not convert a binary number into BCD numbers
- works only with addition when BCD numbers are used; does not work with
subtraction.
- Auxillary carry flag is used internally by the microprocessor; this flag is not
available to the programmer through any Jump instruction.

Example: Add two packed BCD numbers: 85 and 67

1 (carry from most significant digit)

85 = 1000 0101
67= 0110 0111
-----------------------------
(MSD=F>9,add 60H) 1111 11 0 0 (12>9, therefore add 6)
0110 0110
---------- -----------
152 = 1 0101 0010 (the carry resulting from this is added to the
most significant digit)

Page 11 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

LOGIC GROUP

I.LOGICAL OPERATIONS: (AND, OR, XOR, CMP, COMPLEMENT, SET/RESET

CARRY)

AND OPERATIONS:

34. ANA r (logically AND register r(A/B/C/D/E/H/L) with A)

This instruction logically ANDs the contents of the specified register with those of the
accumulator bit by bit and places the result in the accumulator. The carry flag is
reset and the auxillary carry flag is set. All other flags are affected according to the
result..
Note: Data MASKING can be done using logical AND

Example: ANA E
Explanation: Assume that the contents of accumulator and register E are 67H and
64H, respectively . After the execution of the instruction, accumulator will contain

0110 0111 (67H)

0110 0100 (64H)
---------------
0110 0100 (64H) - logically ANDing each of the bits.
Flags: C=0, AC=1 (does not depend upon result)
P=0, S=0, Z=0 (according to result in accumulator)

35. ANA M ( logically AND memory contents whose address is in HL registers

with Accumulator)

This instruction logically ANDs the contents of the memory location whose address
is in HL with those of the accumulator bit by bit and places the result in the
accumulator. The carry flag is reset and auxillary carry flag is set. Pairy, Sign and
Zero flags will be affected according to the result in accumulator.

Example: ANA M
Explanation: Suppose the contents of accumulator are 54H and HL register pair
contains 3000H and the contents of memory location 3000H are 82H, then after the
execution of the instruction, accumulator will contain 00H.
Flags: AC=1, CY=0 (does not depend upon result)
S=0, Z=1, P=1 (depend upon result (00H) in accumulator)

Page 12 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

36. ANI 8 bit data ( Logically AND immediate with Accumulator)

This instruction ANDs bit by bit the contents of the accumulator with the 8-bit given
data and stores the result in accumulator. The carry flag is reset and auxillary carry
flag is set. All other flags are affected according to the result.

Example: ANI 97H

Explanation: Suppose accumulator contains A3H
(A) = A3H = 1010 0011
97H = 1001 0111
--------------------------
83H = 1000 0011
--------------------------
Flags: CY=0, AC=1 (does not depend upon result)
Z=0, P=0, S=1 (depend upon result in accumulator)

OR operation based instructions:

37. ORA r ( logical OR register r with A )

This instruction performs a bit by bit OR operation between the contents of the
specified register r (A/B/C/D/E/H/L) with the contents of the accumulator. The result
is stored in accumulator. Both the carry and auxillary carry flags are reset. Zero,
Parity and Sign flags will be affected according to the result.

Example: ORA E
Explanation: Assume the contents of the accumulator are 03H and register E holds
byte 81 H, then
03 H = 0000 0011
81 H = 1000 0001
------------------------------
83H = 1000 0011
------------------------------
after the execution of the instruction,
Accumulator = 83H
Flags: CY=0, AC=0 (does not depend upon result)
Z=0, S=1, P=0 (depend upon result (83H) in A)

Page 13 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

38. ORA M ( logically OR memory contents with A)

This instruction performs a bit by bit OR operation between the contents of the
memory location whose address is in HL with the contents of the accumulator. The
result is stored in accumulator. Carry and Auxillary flags are reset. All other flags are
affected according to the result in accumulator.

Example: ORA M

Explanation: Assume that the contents of accumulator are F0H, HL register pair
contains 5400H and the contents of memory location 5400H are 0FH, then
(A) = 1111 0000
((HL)) = 0000 1111
-------------------------------
(A) = 1111 1111
-------------------------------
Register contents after the execution of the instruction:
(A) = FFH
(F) = CY=0, AC=0 ( does not depend upon result)
S=1, Z=0, P=1 (depends upon result (FFH) in A)

39. ORI 8-bit data (OR immediate data with A)

This instruction performs a bit by bit OR operation between the contents of the
accumulator and the 8-bit data that is given as the second byte of instruction. The
result is stored in accumulator. Carry and Auxillary carry flags will be reset. All other
flags affected according to the result.

Example: ORI 89H

Explanation: Suppose (A) = 90H, then after the execution of the instruction
(A) = 99H, (F) = CY=0,AC=0,
Z=0, S=1, P=1

Page 14 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

Exclusive-OR operation related instructions:

40. XRA r (Exclusive OR register r with A)

This instruction performs an Exclusive OR operation bit by bit between the contents
of the accumulator and the specified register and places the result in A. Carry and
Auxillary flags are reset. All other flags are affected according to the result in the
accumulator.

Example: XRA A
Explanation: This is one of the instruction used to clear accumulator.
Suppose accumulator contains 83H, then
(A) = 1000 0011
(A) = 1000 0011
----------------------
(A) = 0000 0000
---------------------

After the execution of the instruction,

(A) = 00H,
(F) = CY=0, AC=0 (does not depend upon result)
P=1, S=0, Z=0 (depend upon result (00H) in A)

41. XRA M ( Exclusive OR memory contents with A)

This instruction performs an Exclusive OR operation bit by bit between the contents
of the memory location whose address is in HL and the accumulator and places the
result in A. Carry and Auxillary carry flags are cleared and other flags are affected
according to the result.

Example: XRA M
Explanation: Suppose (A) = 87H, ((HL)) = 56H before the execution of the
instruction
(A) = 1000 0111
((HL)) = 0101 0110
-------------------------------
(A) = 1101 0001
-------------------------------
then, after the execution of the instruction,
(A) = D1H
(F) = CY=AC=0
Z=0, P=S=1

Page 15 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

42. XRI 8-bit data (Exclusive OR immediate with A)

This instruction performs an Exclusive OR oepration bit by bit between the contents
of the accumulator and the 8-bit data that is given as part of the instruction. The
result is stored in the accumulator. Carry and Auxillary carry flags will be reset and
other flags will be modified according to the result.

Example: XRI FFH

Explanation: Suppose before the execution of the instruction, (A) = 45H, then
(A) = 0100 0101
FFH = 1111 1111
--------------------------
(A) = 1011 1010
--------------------------
after the execution of the instruction, (A) = BAH, (F) = CY,AC=0, S=1, P=Z=0

Page 16 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

COMPARE RELATED INSTRUCTIONS:

43. CMP r ( Compare register r with A)

This instruction compare the contents of register r (A/B/C/D/E/H/L) with the contents
of accumulator. The comparison is performed by subtracting the contents of register
r from the contents of the accumulator. However, neither contents are modified.
Comparison is shown by setting the flags as follows:
- If (A) < ( r ) , Carry flag is set and Zero flag is reset
- If (A) = ( r ) , Carry flag is reset and Zero flag is set
- If (A) > ( r ), Carry and Zero flags are reset.

Example: CMP D
Explanation: Suppose (A) = 47H and (D) = 62H prior to the execution of the instruction,
then
(A) = 0100 0111
2’s complement of (D) = 1001 1110
---------------
1110 0101
---------------
after the execution of the instruction, (A) = 47 H ( previous contents will not be modified)
(F) = (CY)=1, Z=0 (since (A) < (D))
(S) =1, AC=1, P = 0 ( according to the result)

44. CMP M ( Compare memory data with A)

This instruction is similar to CMP r described above except that the contents of the
accumulator are compared with the data in the memory location whose address is in
HL

Example: CMP M
Explanation: Suppose (A) = 57H, ((HL)) = 62H, then after the execution of the
instruction
(A) = 57H ( not modified)
(F) = CY=1, Z=0 ( since (A) < ((HL)) )
S=1, P=1, AC = 1

45. CPI 8-bit data (Compare immediate data with A)

This instruction is similar to CMP r described above except that the contents of the
accumulator are compared with the 8-bit data given.

Example: CPI 98H

Explanation: Assume that prior to the execution of the instruction (A) = C2H, then
after the execution of the instruction,
- The accumulator contents remain unchanged.
- Z and CY flags are reset because (A)>8-bit data
- Other flags: S=0,AC=0, P=0
Page 17 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

COMPLEMENT RELATED INSTRUCTION:

46. CMA ( Complement A)

This instruction finds 1’s complement (inverting each bit) of the contents in
accumulator.

Example: CMA
Explanation: Suppose (A)=56H prior to the execution of the instruction, then
(A) = 0101 0110
-----------------------
(A) = 1010 1001

after the execution of the instruction, accumulator will contain A9H.

CARRY MANIPULATION INSTRUCTIONS:

47. STC (Set Carry)

This instruction sets the carry flag to 1. No other flags are affected.

48. CMC (Complement carry)

This instruction complements the carry flag. Suppose (CY)=1 before the execution of
the instruction, then after the execution of the instruction (CY)=0. No other flags are
modified.

Page 18 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

II. ROTATE RELATED INSTRUCTIONS:

49. RLC (Rotate A left)

Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in
the position of D0 as well as in the carry flag. Carry flag is modified according to bit
D7 . S,Z,P, AC flags are not affected.

Example: RLC
Explanation: Assume (A)=A7H prior to the execution of the instruction,
Accumulator contents(A7H) before the execution of instruction
CY
0

1 0 1 0 0 1 1 1

Accumulator contents (4FH) after the execution of the instruction

CY
1

0 1 0 0 1 1 1 1

Note: The contents of D7 are placed in bit D0 , and the carry flag is modified
accordingly. However, the contents of the carry are not placed in bit D0 as in
instruction RAL.

50. RRC (Rotate A right)

Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in
the position of D7 as well as in the carry flag. Carry flag is modified according to bit
D0 . S,Z,P,AC are not affected.

Example: RRC
Explanation: Assume the carry flag is reset and accumulator contains A7H before
the execution of the instruction, then
Accumulator contents (A7H) before execution of instruction:

CY
0

1 0 1 0 0 1 1 1

Accumulator contents (D3H) after the execution of the instruction (RRC)

CY
1

1 1 0 1 0 0 1 1

Page 19 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

Note: The contents of bit D0 are placed in bit D7 , and the carry flag is modified
accordingly. However, the contents of the carry are not placed in bit D7 , as in
instruction RAR.

51. RAL (Rotate Accumulator left through carry)

Each binary bit of the accumulator is rotated left by one position through the carry
flag. Bit D7 is placed in the bit in the carry flag and the carry flag is placed in the least
significant position D0
Carry flag is modified according to bit D7 . S,Z,AC,P are not affected.

Example: RAL
Explanation: Assume that (A) = A7H and carry flag is reset before execution of the
instruction, then

Accumulator contents (A7H) before the execution of instruction (RAL)

CY
0

1 0 1 0 0 1 1 1

Accumulator contents (4EH) after the execution of the instruction

CY
1

0 1 0 0 1 1 1 0

Note: This instruction effectively provides a 9-bit accumulator. The original contents
of the accumulator can be restored by using instruction RAR (Rotate Accumulator
Right through Carry). However, the contents will be modified if the instruction RRC
(Rotate Accumulator Right through carry). However, the contents will be modified if
the instruction RRC (Rotate Accumulator Right) is used to restore the contents.

Page 20 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

52. RAR (Rotate Accumulator right through carry)

Each binary bit of the accumulator is rotated right by one position through the carry
flag. Bit D0 is placed in the carry flag and the bit in the carry flag is placed in the most
significant position, D7. Carry flag is modified according to bit D0. S,Z,P,AC are not
affected.

Example:RAR

Explanation: Assume (A)=A7H and carry flag is reset before the execution of the
instruction.

Accumulator contents (A7H) before the execution of the instruction

CY
0

1 0 1 0 0 1 1 1

Accumulator contents (53H) after the execution of the instruction (RAR)

CY
1

0 1 0 1 0 0 1 1

Page 21 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

BRANCH GROUP
I. JUMP RELATED INSTRUCTIONS:

53. JMP 16-bit address (Jump unconditionally to the address)

The program sequence is transferred to the memory location specified by the 16-
bit address. This is a 3-byte instruction; the second byte specifies the low-order
byte and third byte specifies the high-order byte.

Example: Write the instruction at location 2000H to transfer the program

sequence to memory location 2050H.
Explanation:

Memory Address Code Mnemonics

2000 C3 JMP 2050H

2001 50
2002 20

Note: The 16-bit address of the operand is entered in memory in reverse

order, the low-order byte first, followed by the high-order byte.

54. Jcond 16-bit address (Jump conditionally to the address given)

This instruction causes a jump to the given address if a specified condition is

satisfied. The conditions could be:

JC Jump on Carry CY=1

JNC Jump on No Carry CY=0
JP Jump on Positive S=0
JM Jump on Minus S=1
JPE Jump on Parity Even P=1
JPO Jump on Parity Odd P=0
JZ Jump on Zero Z=1
JNZ Jump on No Zero Z=0

55. PCHL (H and L register contents to PC)

The contents of registers H and L are copied into the program counter. The contents
of H are placed as a high-order byte and of L as a low-order byte. No flags are
affected.
Note: This instruction is equivalent to a 1-byte unconditional Jump instruction. A
program sequence can be changed to any location by simply loading the H and L
registers with the appropriate address and by using this instruction.

Page 22 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

II. SUBROUTINE RELATED INSTRUCTIONS:

56. CALL 16-bit address (Call unconditionally a subroutine at the address given)

This pushes the current PC contents onto the stack and loads the given address
onto the PC; thus, the CPU jumps to the given address. The stack pointer is
decremented by two. No flags are affected.

Example: Write CALL instruction at memory location 2010H to call a subroutine

located at 2050H. Explain the sequence of events when the stack pointer is at
location 2099H.

Memory Address Hex. Code Mnemonics

2010 CD CALL 2050H

2011 50
2012 20

Sequence of events for the execution of CALL instruction:

• The address in the program counter (2013H) is placed on the stack as follows.
Stack Pointer is decremented to 2098H. MSB is stored.
Stack Pointer is again decremented to 2097H. LSB of PC is stored.
• Call address is temporarily stored in internal WZ registers and placed on the bus for
the fetch cycle.

Note: The CALL instructions should be accompanied by one of the return (RET or
conditional return) instructions in the subroutine.

57. Ccond. 16-bit address (Call the subroutine at the given address conditionally)

This instruction calls the subroutine at the given address if a specified condition is
satisfied. The Stack Pointer is decremented by two. The following conditional calls
can be made:

CC Call on Carry CY=1

CNC Call on No Carry CY=0
CP Call on Positive S=0
CM Call on Minus S=1
CPE Call on Parity Even P=1
CPO Call on Parity Odd P=0
CZ Call on Zero Z=1
CNZ Call on No zero Z=0

Page 23 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

58. RET (Return from Subroutine unconditionally)

The program sequence is transferred from the subroutine to the calling program.
The two bytes from the top of the stack are copied into the program counter and the
program execution begins at the new address. The instruction is equivalent to POP
Program counter. No flags are modified.

Example: RET
Explanation: Assume the stack pointer is pointing to location 2095H. Explain the
effect of the RET instruction if the contents of the stack locations are as follows:
2095H 50H 2096H 20H

After the execution of the instruction RET, the program execution will be transferred
to location 2050H and the stack pointer is shifted to location 2097H.
Note: This instruction is used in conjunction with CALL or conditional call
instructions.When CALL or conditional CALL instructions are executed, the address
of next instruction (the current PC address) is pushed onto the stack. This is
retrieved using RET or conditional RET instructions

59. Rcond. (Return from the subroutine conditionally)

This instruction returns the control to the main program, if the specified condition is
satisfied. The changes of PC and SP are the same as in an unconditional RET. The
following conditional return instructions are possible:

RC Return on Carry CY=1

RNC Return on No carry CY=0
RP Return on Positive S=0
RM Return on Minus S=1
RPE Return on Parity Even P=1
RPO Return on Parity Odd P=0
RZ Return on Zero Z=1
RNZ Return on No Zero Z=0

Page 24 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

III. I/O, STACK OPERATIONS AND MACHINE CONTROL RELATED

INSTRUCTIONS

I. INPUT/OUTPUT RELATED INSTRUCTIONS:

60. IN 8-bit port address (Input data to accumulator from a port with 8-bit address)

This instruction puts into the accumulator the contents of the port whose address is
specified by the one byte address as a part of the instruction. No flags are affected.

Example: IN 45H
Explanation: Suppose port 45H contains FFH, then after the execution of the
instruction accumulator will contain FFH.

Note: Here the operand is an 8-bit address; therefore, port addresses can range from
00H to FFH. While executing the instruction, a port address is duplicated on low-order
(A7 – A0) and high-order (A15-A8) address buses. Any one of the sets of address lines
can be decoded to enable the input port.

61. OUT 8-bit port address (Output data from accumulator to a port with 8-bit
address)

This instruction transfers the contents of the accumulator onto the port whose one byte
address is specified. No flags are affected.

Example: OUT 78H

Explanation: Suppose accumulator contains 33H, then after the execution of the
instruction , output port with the address 78H will contain 33H.

Note: The operand is an 8-bit address; therefore, port addresses can range from 00H to
FFH. While executing the instruction, a port address is placed on the low-order address
bus (A7-A0) as well as the high-order address bus(A15-A8). Any of the sets of address
lines can be decoded to enable the output port.

Page 25 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

STACK OPERATIONS RELATED INSTRUCTIONS:

62. PUSH rp (Push register pair (BC/DE/HL)onto the stack)

The contents of the register pair designated in the operand (BC/DE/HL) are copied into
the stack in the following sequence:
The stack pointer register is decremented and the contents of the high-order register
(B/D/H) are copied into that location. The stack pointer register is again decremented
and the contents of the low-order register (C/E/L) are copied to that location.
No flags are modified.

Example: PUSH B
Explanation: Assume the stack pointer register contains 2099H, register B contains
32H and register C contains 57H before the execution of the instruction, then

Register contents before execution of the instruction:

BC 3257H
SP 2099H

Stack contents after the execution of the instruction:

2098 32H
2097 57H

Register contents after the execution of the instruction:

BC 3257H
SP 2097H

Note: The contents of the source registers (BC) are not altered after the PUSH
instruction.

63. PUSH PSW (Push Program Status Word onto stack)

PSW is the Program Status Word; it consists of the accumulator and flag registers with
accumulator as the high-order byte. As a result of the PUSH operation, SP is
decremented and the high-order byte (A) is copied onto the location pointed to by Stack
Pointer; SP is again decremented and the low-order byte (Flag Register) is copied onto
the location pointed to by SP. None of the flags are affected.

Page 26 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

64. POP rp ( Pop off stack to register pair (BC/DE/HL))

This copies the contents of the top two memory locations of the stack onto the specified
register pair (BC/DE/HL).
- First, the contents of the memory location indicated by the stack pointer register are
copied into the low-order register (C/E/L), and then the stack pointer register is
incremented by 1.
- The contents of the next memory location are copied into the high-order register
(B/D/H) and the stack pointer register is again incremented by 1.
Note: The contents of source (Stack contents) are not modified and no flags are
affected.

Example: POP H
Explanation: Assume that the stack pointer register contains 2090H, data byte F5H is
stored in memory location 2090H, and data byte 01H is stored in location 2091H prior to
the execution of the instruction, then

Register contents before instruction execution

HL 9034H
SP 2090H

Stack contents after/before instruction execution

2090H F5H
2091H 01H

Register contents after instruction execution

HL 01F5H
SP 2092H

Note that the contents of the source, stack locations, are not altered after the execution
of POP instruction.

65. POP PSW ( Pop off stack to Program Status Word (Accumulator and Flag
register) )

It copies the contents of the location pointed to by SP onto the low-order byte of the
PSW (Flag register), increments SP, and copies the contents of the location pointed to
by SP onto the high order byte of the PSW (accumulator). SP is again incremented by
one. All flags are affected.

Page 27 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

66. XTHL (Exchange top of the stack with H and L registers)

The contents of the L register are exchanged with the stack location pointed out by the
contents of the stack pointer register. The contents of the H register are exchanged with
the next stack location (SP+1); however, the contents of the stack pointer register are
not altered. No flags are affected.

Example : XTHL
Explanation: Assume that
Register contents before the execution of the instruction
HL A257H
SP 2095H
Stack Contents before the execution of the instruction
2095 38H
2096 67H

Register contents after the execution of XTHL instruction

HL 6738H
SP 2095H
Stack contents after the execution of XTHL instruction
2095 57H
2096 A2H

67. SPHL (Copy H and L registers to the stack pointer)

This instruction copies the contents of HL onto the stack pointer register. H provides the
high-order byte of the address while L provides the low-order byte of the address. The
contents of the H and L registers are not altered. No flags are affected.

This instruction can be used to load a new address in the stack pointer register.

Page 28 of 29
 TAO1221 Computer Architecture and Organization Tutorial 3 & 4

MACHINE CONTROL RELATED INSTRUCTIONS:

68. NOP (No Operation)

No operation is performed. The instruction is fetched and decoded; however, no

operation is executed. No flags are affected.
This instruction is used to fill in time delays or to delete and insert instructions while
troubleshooting. When an error occurs in a program and an instruction needs to be
eliminated, it is more convenient to substitute NOP than to reassemble the whole
program.

69. HLT (Halt and Enter Wait State)

Microprocessor finished executing the current instruction and halts any further
execution. Microprocessor enters the Halt Acknowledge machine cycle and Wait states
are inserted in every clock period.
Address and Data bus are placed in the high impedance state. The contents of the
registers are unaffected during the HLT state.
To exit from the Halt state, a valid interrupt or reset is necessary.
No flags are affected.

Reference:

Ramesh S.Gaonkar (2002). Microprocessor Architecture, Programming, and

Applications with the 8085, 5/E. Prentice Hall.

Page 29 of 29