Cadence PA Design Using SpectreRF PDF
Cadence PA Design Using SpectreRF PDF
Cadence PA Design Using SpectreRF PDF
SpectreRF Workshop
Power Amplifier Design Using SpectreRF
MMSIM 10.1
August 2010
Contents
Purpose
This workshop describes how to use SpectreRF, which includes the new hb analysis, in
the Virtuoso Analog Design Environment to measure parameters that are important in
design verification of Power Amplifiers (PAs).
The hb analysis is one new GUI for the harmonic balance analysis, and has the similar
features with the harmonic balance engine in PSS and QPSS analyses.
Note: The procedures described in this workshop have been kept broad and generic. Your
specific design might require procedures that are slightly different from those described here.
Audience
Users of SpectreRF in the Virtuoso Analog Design Environment.
Overview
This workshop describes a basic set of the most useful measurements for PAs.
Power amplifiers can be categorized several ways depending on whether they are
broadband or narrowband, and whether they are intended for linear operation (Class A, B,
AB and C) or constant-envelope operation (Class D, E and F). This workshop focuses on
the design of narrowband and linear PAs.
The supply voltage is 5 V. There is a simple output matching network in the sub circuit
EF_PA_ostg. The power amplifier is designed to be driven by CDMA I/Q channel
baseband signals, modulated using QPSK schemes with a carrier frequency of 1 GHz.
The first testbench drives the PA by sinusoidal sources. In this workshop, you use this
testbench to make general measurements, including:
■ Power related measurements (input power, output power, supply voltage, supply
current, power gain, and power dissipation)
You use a Periodic Steady State (PSS) or hb analysis followed by a Periodic Small Signal
(PAC/PSP/PNOISE, or hbac/hbnoise) analyses to make these measurements. (For details,
see Labs 1 to 4 on pages 6-44).
Testbench Two
The second testbench drives the PA by a sinusoidal source with a port adapter added at
the output power amplifier. You use this testbench to generate
■ Load-pull contours
■ Reflection contours
You use the swept hb analysis combined with the parametric analysis tools to measure
load pull. (For details, see Lab 5 on page 52).
Testbench Three
The third testbench drives the PA by modulation signals. You use this testbench to
generate
■ ACPR plots
■ Input and output trajectory plots
You use the Envelope (envlp) analysis to make these measurements. (For details, see
Lab 6 on page 73).
Begin the examination of the flow by bringing up the Cadence Design Framework II
environment to look at a full view of the reference design:
Power related measurements include input power, output power, supply voltage, supply
current, power gain, and power dissipation. To make these measurements, you use a
swept PSS analysis to sweep the input power level.
Action 1-1: Open the schematic view of the design EF_example_simple in the library
RFworkshop.
Action 1-2: Select the PORT1 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 1
DC voltage (blank)
Action 1-3: Select the PORT2 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 2
DC voltage (blank)
Source type dc
Action 1-5: In the Virtuoso Schematic Editing window, choose Launch — ADE L.
Action 1-6: (Optional) Choose Session — Load State in the Virtuoso Analog Design
Environment window, select Cellview in Load State Option and load
state “Lab1_Power_hb”, then skip to Action 1-12.
Action 1-7: In the Virtuoso Analog Design Environment window, choose Analyses —
Choose….
Note: The hb analysis is one new GUI for the harmonic balance analysis, and has the
similar features with the harmonic balance engine in PSS and QPSS analyses.
For the hams/maxharms parameter, 5-8 is enough usually. More harms/maxharms will be
used for the strong non-linear signal.
By default, the tstab method is used for Harmonic Balance Homotopy Method.
Action 1-9: Make sure that Enabled is selected. Click OK in the Choosing Analyses
form.
Action 1-10: In the Virtuoso Analog Design Environment window, choose Outputs —
To be Saved — Select on Schematic.
Action 1-11: In the schematic, select the positive terminals of PORT2, and PORT1.
Press the ESC key to end the selection process.
Action 1-12: Choose Simulation — Netlist and Run to start the simulation or click the
netlist and Run icon in the Virtuoso Analog Design Environment
window. After the simulation finishes, use the next actions to plot the
simulation results.
Action 1-14: In the Direct Plot Form window, choose hb as the Analysis type. Choose
Power in the Function field. Choose 1G in the Output Harmonic list
box.
The waveform window shows the output power versus input power.
For the design example given, when the input power level is -5 dBm, the output power
level is close to 20 dBm. Thus, -5 dBm is assumed to be the normal operating condition.
All subsequent plots are based on this assumption.
Action 1-16: In the Direct Plot form, change the Plotting Mode to Replace and set up
the form as follows:
Action 1-18: In the Direct Plot form, click Power Gain in the Function field and set up
the form as follows:
Action 1-19: In the schematic, click the positive and negative terminals of Port2, and
then click the positive and negative terminals of VCC.
Action 1-20: In the waveform window, click the Add Sub window icon.
Action 1-21: In the Direct Plot form, set the Plotting Mode to New SubWin. Select
Power Added Eff. in the Function field. Select the Output Harmonic as
1GHz.
To use the Power Added Efficiency (PAE) function, you only need to select the output
terminal, input terminal, and DC terminal in turn. The result is a plot of the power added
efficiency versus the input power level.
Action 1-22: In the schematic, select the positive terminals of PORT2, PORT1 and
VCC in turn.
Notice that for a PA with high gain, the PAE is nearly equal to the drain efficiency. You
find that the efficiency of the PA around the nominal operating condition is only about
20%.
Action 1-23: Close the waveform window, the Direct Plot form, and the Virtuoso
Analog Design Environment window.
When the circuit is driven by two RF tones ( f in and f in 2 ), the third order intercept point
is the intercept point of the first order fundamental power term ( f in , f in 2 ) and the third
order inter-modulation power term ( 2 × f in − f in 2 , 2 × f in 2 − f in ), expressed in decibel
form.
There are at least four ways to measure IIP3 and OIP3 using SpectreRF:
2. QPSS/hb analysis with one large tone and one moderate tone
Action 2-1: If it is not already open, open the schematic view of the design
EF_example_simple in the library RFworkshop.
Action 2-2: Select the PORT1 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 1
DC voltage (blank)
Source type sine
Frequency name 1 RF
Frequency 1 fin
Amplitude 1 (dBm) pin
PAC magnitude (dBm) pin
Action 2-5: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab2_IP3_hbac,” and skip to Action 2-12.
Action 2-6: In the Virtuoso Analog Design Environment window, choose Analyses —
Choose….
Action 2-7: In the Choosing Analyses window, select hb in the Analysis field of the
window.
Action 2-9: Make sure Enabled is selected, and click Apply in the Choosing Analyses
form.
Action 2-10: In the Choosing Analyses window, select hbac in the Analysis field. Set
up the form as follows:
Action 2-11: Make sure Enabled is selected, and click OK in the Choosing Analyses
form.
When the simulation ends, use the following actions to plot the P1dB and IP3 curves.
Action 2-13: In the Virtuoso Analog Design Environment window, choose Results —
Direct Plot — Main Form.
Action 2-14: In the Direct Plot Form, select hb and set up the form like this:
The output referred 1dB compression point, which is 19.92dBm in this case, is more
meaningful for PA design.
Action 2-16: In the Direct Plot Form, set Plotting Mode to Replace. Select hbac and
set up the form like this:
Action 2-18: Close the waveform window. Click Cancel in the Direct Plot form. Close
the Virtuoso Analog Design Environment window.
Kf >1, ∆ <1
2 2
Kf > 1, B1 f = 1 + S11 − S 22 − ∆2 >0
To analyze stability for a PA, set up PSS and PSP analyses. The PSP analysis is a
periodic small-signal analysis, so the S-parameter and VSWR results it generates apply
only to the small signal. In some PA data sheets, the S-parameter and VSWR values
specified are large signal characteristics. SpectreRF currently supports large signal SP
(LSSP) analysis as demonstrated in Lab 4.
Action 3-1: If it is not already open, open the schematic view of the design
EF_example_simple in the library RFworkshop
Action 3-2: Select the PORT1 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 1
DC voltage (blank)
Source type sine
Frequency name 1 RF
Frequency 1 fin
Amplitude 1 (dBm) pin
Action 3-4: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab3_Stability_HBPSP,” and skip to Action 3-
10.
Action 3-5: In the Virtuoso Analog Design Environment window, choose Analyses —
Choose….
Action 3-6: In the Choosing Analyses window, select pss in the Analysis field of the
window and set up the form as follows:
Action 3-7: Make sure Enabled is selected, and click Apply in the Choosing Analyses
form.
Action 3-8: In the Choosing Analyses window, select psp in the Analysis field of the
window and set up the form as follows:
Action 3-9: Make sure Enabled is selected, and click OK in the Choosing Analyses
form.
Action 3-11: In the Virtuoso Analog Design Environment window, choose Results —
Direct Plot — Main Form.
Action 3-12: In the Direct Plot Form, select psp and click Kf in the Function field. The
form looks like this:
Action 3-14: In the Direct Plot Form, set Plotting Mode to Replace. In the Analysis
field, select psp, and click B1f in the Function field.
Action 3-17: In the Direct Plot Form, set Plotting Mode to Append. In the Analysis
field, select psp. In the Function field, select SP. In the Plot Type field,
select Rectangular. In the Modifier field, select dB20.
Action 3-20: In the Direct Plot Form window, set Plotting Mode to Append. In the
Analysis field, select psp. In the Function field, select SP. In the Plot
Type field, select Z-Smith.
Action 3-25: In the Direct Plot Form, in the Function field, choose VSWR (Voltage
standing-wave ratio). In the Modifier field, select dB20. Click VSWR1,
then VSWR2.
Action 3-26: Close the waveform window. Click Cancel in the Direct Plot form. Close
the Virtuoso Analog Design Environment window.
Action 4-1: If it is not already open, open the schematic view of the design
EF_example_LSSP in the library RFworkshop.
Action 4-2: Select the PORT1 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 1
DC voltage (blank)
Source type sine
Frequency name 1 RF
Frequency 1 fin
Amplitude 1 (dBm) pin
Action 4-3: Select the PORT2 source. Choose Edit — Properties — Objects and
ensure that the port properties are set as described below:
Parameter Value
Resistance 50 ohm
Port Number 2
DC voltage (blank)
Source type sine
Make sure you are using PORT. SpectreRF currently only supports PORT
for LSSP simulation.
Action 4-6: In the Virtuoso Analog Design Environment window, choose Tools —
RF — LSSP …
Action 4-7: In the Large Signal S-Parameter Wizard window, select Port1 in the
Define Input/Output field.
Action 4-10: In the Large Signal S-Parameter Wizard window, choose Amplitude in
Sweep field.
Action 4-12: In the Large Signal S-Parameter Wizard window, click OK to close the
window.
Action 4-14: In the waveform window, place a marker in curve mag(S21) at Pin=-5
dBm by choosing Marker — Place — Trace marker. It shows that
S21=23.29dB at Pin=-5 dBm.
Action 4-15: In the Virtuoso Analog Design Environment window, choose Variable —
Edit. The Editing Design Variable window appears.
Action 4-16: In the Editing Design Variable window, click pin -10, change its value
to -5. Click Change.
Action 4-17: In the Editing Design Variable window, click pout 10, change its value to
18.29. Click Change.
Action 4-19: In the Virtuoso Analog Design Environment window, choose Tools — RF
— LSSP ...
Action 4-20: Set up the Large Signal S-Parameter Wizard form as follows:
Action 4-21: In the Large Signal S-Parameter Wizard window, click OK to close the
window.
Note: If it does not happen by default, you might want to change the graph to strip mode
to get individual graphs in each sub window.
Action 4-23: Close the waveform window. Click Cancel in the Direct Plot form. Close
the Virtuoso Analog Design Environment window. Close the
EF_example_LSSP schematic.
Keep in mind that you are sweeping output reflection coefficients by changing a linear
load. The large signal output reflection coefficients computed in this manner equal the
small-signal, or incrementally computed, load reflection coefficients. However, for input
reflection coefficients, this is no longer true. You are actually computing the large signal
reflection coefficients at the fundamental frequency.
You might not always be able to achieve the optimal output power due to other design
goals, such as stability concerns. Those goals are generally posed as constraints in the
reflection coefficients. SpectreRF allows you to overlay the reflection coefficients on top
of the constant power contours to facilitate your design choices.
However, a constant power contour does not equal a constant power gain contour. You
should plot the input power contours both to verify that the input impedance of the PA
does not change significantly as the load impedance changes and to ensure that you have
achieved a reasonable power gain.
Action 5-1: Open the schematic view of the design EF_example_loadpull in the
library RFworkshop.
The following figure shows the modified EF_example_simple schematic for load pull
calculations.
The input port in the above testbench has the following parameters:
Parameter Value
Resistance 50 ohm
Port Number 1
DC voltage (blank)
Source type sine
Frequency name 1 RF
Frequency 1 fin
Amplitude 1 (dBm) pin
Parameter Value
Resistance 50 ohm
Port Number 2
DC voltage (blank)
Source type dc
Action 5-3: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab5_LoadPull_hb” then skip to Action 5-10.
Action 5-4: In the Virtuoso Analog Design Environment window, choose Analyses —
Choose….
Action 5-5: In the Choosing Analyses window, select hb in the Analysis field of the
window.
Click Variable for phi(Z) form, and set up the form like this.
(Optional): If you are using old version IC, in order to do load pull analysis, an instance
of a PortAdaptor is needed to connect to the load. The testbench should look like this:
Frequency 1G
Phase of Gamma theta
Mag of Gamma mag
r0 (this value must be equal
Reference Resistance
to the load)
In the hb form, set up two the form for sweep 1 and 2 as follows:
Action 5-7: Make sure Enabled is selected, and click OK in the Choosing Analyses
form.
Action 5-8: In the Virtuosos Analog Design Environment window, choose Outputs —
To be Saved — Select on Schematic.
Action 5-9: In the schematic, select the input terminals of PORT1 and PORT2. Press
the ESC key to end the selection process.
Action 5-11: After the simulation runs, in the Virtuoso Analog Design Environment
window, choose Results — Direct Plot — Main Form.
Action 5-12: In the Direct Plot Form, select hb, and choose the Power Contours
function. Make sure Select is toggled to Single Power/Refl Terminal,
select fundamental (harmonic 1) as the output harmonic. The form looks
like this:
Action 5-13: In the schematic window, select the PORT2 plus terminal. If you want,
click Close contours. The plot shows the contours of constant output
power.
From the above plot, the maximum power of 0.72mW is located at the center of the
smallest constant power contour.
You might want to maximize load power subject to a constraint on the magnitude of the
amplifier’s input reflection coefficient. Such a constraint can prevent unstable
interactions with the preceding stage.
You can overlay the output power contours with contours of constant input reflection
coefficient magnitude. The optimal load corresponds to the reflection coefficient that lies
on the largest power load-pull contour and also lies on a constant input reflection
coefficient contour that is within the constraint. Here, largest power means the contour
corresponding to the largest amount of power delivered to the load.
Action 5-14: In the hb Direct Plot form, choose the Reflection Contours function, then
toggle Select to Separate Refl and RefRefl Terminals. Select the input
port (PORT1) of the PA first, and then select the output port (PORT2).
This plots the constant input reflection contours in the Smith chart of the
output reflection coefficients.
The following plot shows the constant input reflection coefficient contours overlaying the
output power contour:
Action 5-15: Change the Plotting Mode to Replace, choose the Power Contours
function, and select the terminal of the input port to plot the input power
contour. If the contour shows that the input power does not vary
significantly over the output reflection coefficient sweep, then the constant
power contour is very close to the constant gain contour.
Action 5-16: Close the waveform window. Click Cancel in the Direct Plot form.
To draw the load pull contour for the compression points, three variables; power, phase
and magnitude need to be swept. The power sweep is necessary to obtain the
compression points for the specified phase and magnitude.
Action 5-17: In the Virtuoso Analog Design Environment window, choose Analyses —
Choose …
Action 5-18: In the Choosing Analyses window, select hb in the Analysis field of the
window. Set up the form for sweep 1 as follows:
(Optional): If you are using old version IC, you can set up sweeps as below:
Action 5-21: In the Virtuoso Analog Design Environment window, choose Results —
Direct Plot — Main Form.
Action 5-22: Select Compression Point for Function. Select Points for Plot. Select 1
for Gain Compression (dB). Select 1 for 1st Order Harmonic. Select
Loadpull Contour.
Action 5-24: (Optional): If you are using old version IC, setup the direct plot form like
this:
In the Calculator window, click OK and plot the load pull contour for the compression
points.
Action 5-25: In the Graph Window, choose Graph — Display Type — Impedance
To do envlp analysis, you can use either the shooting engine or the harmonic balance
engine. This lab shows you how to use the Virtuoso® Spectre® RF Envelope with the
harmonic balance engine to design and analyze transmitters.
Action 6-1: Open the schematic view of the design EF_example_envlp_acpr in the
library Rfworkshop.
The power amplifier is driven by modulation signals. CDMA I/Q baseband chip streams
are fed into an ideal QPSK modulator.
Action 6-2: View the object properties of I36. ACPR_source, which is available in
rflib starting from IC5141ISR141 and IC613ISR17, re-designed from
IC614ISR8, is a behavioral modulator that allows users to specify I/Q
PWL files, carrier frequency, input power level in one single instance,
You can also get an equivalent input by setting up a port because it can output carrier-
modulated signal for I/Q paths, configure the port as follow:
Action 6-4: From the schematic window, choose Launch — ADE L to start the
Virtuoso Analog Design Environment.
Action 6-5: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab6_ENVLP_hb,” then skip to Action 6-11.
Action 6-6: In the Virtuoso Analog Design Environment window, click the Choose
Analyses icon.
Action 6-7: In the Choosing Analyses form, select the envlp analysis and choose the
harmonic balance engine. Set Stop Time to 1.667m, Fund Frequency to
1G, and Number of harmonics to 3.
3 harmonics are enough in this case. If the circuit is strongly nonlinear, more harmonics
are needed. In cases where the circuit has a square carrier, nine harmonics are sufficient.
But for some cases, twenty or more harmonics may be required.
Action 6-8: Set the Time Step Control field to Fixed and set Step Period to
2.03451e-7.
The Step Period parameter is equal to the sample interval of the baseband data (I/Q data
in instance I36). If you check the PWL files cdma_2ms_idata and cdma_2ms_qdata, the
sample interval of these data is 0.203451us, i.e. the sample frequency is 4.9152MHz. To
achieve better accuracy and better simulation speed, the Step Period parameter should be
set to the sample interval of these data. Because the sample period is 0.203451us, the
spectrum bandwidth is -4.9152M/2 to 4.9152M/2, and the toal number of samples is
1.667m/ 0.203451us=8193.
Action 6-10: Click OK in the Envelope Options form and then click OK in the
Choosing Analyses form.
Notice the output log file when the simulation ends. The speed-up factor in this case is
203.
.
Action 6-12: In the Virtuoso Analog Design Environment window, choose Results —
Direct Plot — Main Form.
Action 6-13: Select Voltage for Function. Select time for Sweep.
Action 6-15: In the waveform window, double click the X-axis and set the Min and Max
values to 116u and 126u, respectively. Click OK.
The plot displays a number of vertical lines with a wavy line running through them. The
vertical lines are the points at which detailed calculations are performed and the wavy
line connects these points. The simulation runs much faster than a Virtuoso Spectre
Transient Analysis simulation (as envelope skips carrier cycles whenever possible) and
still satisfy numerical tolerances.
Action 6-16: To get a closer look, zoom in on any one of the vertical lines.
You can see the detailed simulation for one complete cycle.
The modulation riding on the RF carrier is the baseband signal - the information to be
transmitted. The baseband signal determines the amplitude and phase of the RF carrier,
and can be extracted at any point in the design. It is important to determine how the
transmitter might alter the baseband signal.
Action 6-21: In the waveform window, click the Strip Chart Mode icon .
Action 6-22: Set the X Axis to 45u to 57u so that you can see both the real and
imaginary parts clearly.
Action 6-23: In the waveform window, double click the X Axis and set the Range to
Auto.
Action 6-24: In the Plot vs. field (at the bottom of the form), select h = 1; v /RFIN ;
envlp re(V), and click OK.
The plot below appears in the waveform window. This is the input baseband trajectory,
undistorted by the power amplifiers.
Action 6-25: Close the Waveform window, then repeat the steps that you used to
display the plot for /RFIN, but substitute the /RFOUT net for /RFIN.
The plot you create in the waveform window looks like this.
The entire trajectory is scaled linearly and rotated. The output baseband signal is the
input baseband signal, multiplied by a complex constant. The input and output
waveforms look different because of the rotation, not because of non-linear distortion. A
common non-linear distortion, such as saturation, makes the outer edges of the trajectory
lie on a circle.
The adjacent channel power ratio (ACPR) is a common index of how much power a
transmitter emits outside its allotted frequency band. To measure ACPR, first obtain the
power spectral density of the transmitted signal. This section describes how to plot the
transmitted power spectral density.
To simulate ACPR measurement, we drive the transmitter with realistic baseband signals.
In most cases, the baseband signals pass through a digital filter before driving a
transmitter. The digital filter compresses the spectrum outside the channel
bandwidth. However the distortion in the transmitter may cause the spectrum re-growth
at the adjacent channels.
To miminize the aliasing error, it should be consistent with the step-period specified in
envlp analysis form and the data rate in I and Q PWL files.
In this lab, the data rate of input baseband signal is 2.03451e-7. Thus the step-period
in envelope analysis is set to be 2.03451e-7, and the strobe-period (T_strobe) in ACPR
post-processing is also 2.03451e-7.
Once the ACPR strobe period T_strobe is determined, other parameters in psdbb ( )
function can be deduced. Suppose we take NFFT=1024, which means the frequency
resolution is 4800Hz (Fres= 1 / (NFFT* T_strobe)). NFFT can be changed according to
the Fres of interest. If FFT is repeated 8 times, the TOTAL_POINTS should be
1024*8=8192. Note that in real simulation, TOTAL_POINTS can be slightly different.
Note: The PSD plot is the normalized result for ACPR. If you use IC 5.1.41 USR6, the
normalized PSD is plotted, while the un-normalized PSD is plotted when using IC 5.1.41
USR5 or before.
The lower ACPR is -88.6971dB, and the upper ACPR is -88.9014as shown in the plot
above.
Action 6-28: In the Direct Plot Form, click Main Channel Power, setup the form as
follow:
In this quick exercise, you rerun the previous ACPR demonstration using the Spectre RF
ACPR Wizard.
Net /RFOUT
Channel Definitions IS-95
Symbol Start (Sec) 0
Strobe Period 2.03451e-7
Window Size 1024
Repetitions 8
The Strobe Period parameter is related to the sample rate of the baseband data (I/Q data
in PORT0 or PORT1). If you check the PWL files cdma_2ms_idata and
cdma_2ms_qdata, the sample interval of these data is 0.203451us, i.e. the sample
frequency is 4.9152MHz. To obtain the real values on these sample points, the Strobe
Period parameter should be set to the sample interval of these data.
The number of repetitions is set to 8, which gives a reasonable simulation time and
accuracy. Increasing the number of repetitions provides better accuracy at the cost of a
longer simulation time.
This action loads the output section of the ADE window with your selected values.
The waveform window automatically opens after simulation and you can read ACPR
number in the Output session in the Analog Design Environment.
Now the Virtuoso Analog Design Environment window looks like this:
Action 6-35: Close the waveform window. Click Cancel on the Direct Plot form. Close
the Virtuoso Analog Design Environment window.
This lab shows you how to use the Virtuoso® Spectre® RF fast envelope with the
harmonic balance engine to design and analyze transmitters.
Action 7-1: Open the schematic view of the design EF_example_envlp_acpr in the
library Rfworkshop.
Action 7-2: View the object properties of I36. ACPR_source, which is available in
rfLib starting from IC5141ISR141 and IC613ISR17, re-designed from
IC614ISR8, is a behavioral modulator that allows users to specify I/Q
PWL files which are necessary in order to do fast envlp analysis, carrier
frequency, input power level in one single instance, greatly simplify the
ACPR simulation setup.
Action 7-4: From the schematic window, choose Launch — ADE L to start the
Virtuoso Analog Design Environment.
Action 7-5: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab7_ENVLP_fastmode_hb,” then skip to
Action 7-11.
Action 7-6: In the Virtuoso Analog Design Environment window, click the Choose
Analyses icon.
Action 7-7: In the Choosing Analyses form, select the envlp analysis and choose the
harmonic balance engine. Set Stop Time to 1.667m, Fund Frequency to
1G, note fast envlp requires a larger number of harms than regular envlp
does because it uses hb, and must have enough harms for nonlinear circuit,
in this lab, set Number of harmonics to 7.
Action 7-9: Select fast envlp levels in the fast envlp mode field, the parameters are
explained below:
Off: fast envlp is off, use regular envelope analysis (default).
level1: fast envelope analysis in level 1 (short memory).
level2: fast envelope analysis in level 2 (more accurate) .
Modulation source I: The name of I source, which corresponds to the
real part of base-band signal. Only PWL type is supported.
Modulation source Q: The name of Q source, which corresponds to the
image part of base-band signal. Only PWL type is supported.
output: nodes to be saved in fast-mode envelope analysis. Multiple nodes
can be selected.
Level 2 may be needed in the simulation where more accurate results are
required. Then Modulation bandwidth must be specified, by experience
this can be set as twice times of the main channel bandwidth, in this lab
we use level 1.
Action 7-10: In the Modulation source I, click select button and then click I36 on the
schematic, /I36/PORT0 is added automatically, note /I36/PORT1 is added
for Modulation source Q as well. In the output nodes, click select button
and then click on the output net and ACPR source output net on the
schematic, /RFOUT and /RFIN appear in the form.
Now you can repeat actions from Action 6-17 to Action 6-25 to plot net voltages etc.,
however, we only show ACPR function for fast envlp analysis below. For conception of
ACPR, refer to page86.
Note: The PSD plot is the normalized result for ACPR. If you use IC 5.1.41 USR6, the
normalized PSD is plotted, while the un-normalized PSD is plotted when using IC 5.1.41
USR5 or before.
Action 7-24: Close the waveform window. Click Cancel on the Direct Plot form. Close
the Virtuoso Analog Design Environment window.
The following actions show you how to use the fast envelope to plot EVM functions.
Action 8-1: Open the schematic view of the design EF_example_envlp_EVM in the
library Rfworkshop.
Action 8-2: View the object properties of I7. rfVsource ,which is a behavior modulator
that allows users to specify OFDM signal standards, carrier frequency,
input power in one instance, greatly simplify the EVM simulation setup.
Action 8-4: From the schematic window, choose Launch — ADE L to start the
Virtuoso Analog Design Environment.
Action 8-5: (Optional) Choose Session — Load State, select Cellview in Load State
Option and load state “Lab8_ENVLP_EVM_hb,” then skip to Action 8-
12.
Action 8-6: In the Virtuoso Analog Design Environment window, click the Choose
Analyses icon.
From the table, we can choose stop time of envlp analysis and step period according to
various signal standards, other parameters are used for post-processing later.
Action 8-7: In the Choosing Analyses form, select the envlp analysis and choose the
harmonic balance engine. Set Stop Time to 200u, note this should be less
than DataLength item in the table, otherwise the simulation results would
be incorrect. Set Fund Frequency to 2.4G. Note fast envlp requires a
larger number of harms because it uses hb, and must have enough harms
for nonlinear circuit, in this lab, set Number of harmonics to 7.
Action 8-8: Set the Time Step Control field to Fixed, since we are using 802_11n_
20M_Green, from the table, set Step Period to 8.33333333e-9.
Action 8-10: In the fast envlp mode field, select level1, the meanings of the parameters
are explained in Action7-9.
Action 8-11: In the Modulation source I field, click select button and then click I7 on
the schematic, /I7/V0 is added automatically, note /I7/V1 is added for
Modulation source Q as well. In the output nodes, click select button and
then click on the output net and rfVsource source output net on the
schematic, /RFOUT and /RFIN appear in the form.
Action 8-13: In the Virtuoso Analog Design Environment window, choose Results —
Direct Plot — Main Form.
Action 8-14: Select EVM for Function, harmonic time for sweep, Percent for
modifier, in the Error Vector Magnitude Parameters field, select
OFDM for Modulation, in the Signal Standard list, select
802_11n_20M_Green, fill other fields according to the table in Action8-
6.
Action 8-16: In the direct plot form, set New Win for Plotting Mode, click net RFOUT
on the schematic, the output EVM plots appears.
From the results, we can see the EVM increases after the signal transmitted by the
transmitter.
To learn how EVM varies with input power, we can sweep input power using parametric
sweep.
Action 8-17: In the ADE window, select Tools-Parametric Analysis. Configure plo as
the sweep variable, sweep from -30dBm to -10dBm, total steps is three,
the parametric analysis window looks like:
Action 8-19: In the direct plot form, set New Win for Plotting Mode, click net RFOUT
on the schematic, the output EVM versus input power plot appears.
From the result, we can see the EVM increases with the input power.
Action 8-20: Close the waveform window, the Direct Plot form, and Virtuoso Analog
Design Environment window.
Conclusion
This workshop describes how to use SpectreRF for RF power amplifier designs. The
workshop
• Presents the typical PA design parameters and describes how to build testbenches
and perform measurements within the Virtuoso Analog Design Environment.
• Covers in detail how to set up SpectreRF analyses and perform measurements
related to PA design.
• Displays and interprets the simulation results.
Reference
[1] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
[2] T. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge
University Press, 1998.
[3] Ken Kundert, “Predicting the Phase Noise and Jitter of PLL-Based Frequency
Synthesizers”, The Designer’s Guide, www.designers-guide.com, 2005