IEEE 1394-1995

High Performance Serial

Bus
Michael D. Johas Teener
Chief Technical Officer,
Zayante, Inc.
269 Mt. Herman Rd. #201
Scotts Valley, CA 95066-4000
[email protected]
 Background
(the way things are now)

Keyboard
Network

Sound

Power
Serial
modem
video floppy SCSI

n No I/O Integration
w lots of PCB area, silicon & software
w no common architecture
n Hard to change
w no realtime transport
w performance not scalable
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 2
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 Goals
n Low cost, high performance
ergonomic peripheral bus
n Read/write memory architecture
w NOT an I/O channel
n Compatible architecture with other
IEEE busses
w Follow IEEE 1212 CSR (Control and
Status Register) standard
n Isochronous service

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 3

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 ÒIsochronousÓ ??
n Iso (same) chronous (time) :
w Uniform in time
w Having equal duration
w Recurring at regular intervals

Data type Sample size and rate Bit rate

ISDN 8 kHz x 8 bits 64 Kbit/sec
CD 44.1 kHz x 16 bits x 2 channels 1.4 Mbit/sec
DAT 48 kHz x 16 bits x 2 channels 1.5 Mbit/sec
Video 25-30 frames/sec 1.5 – 216 Mbit/sec

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 4

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 Asynch Vs. Isoch

n Asynchronous transport
w ÒGuaranteed deliveryÓ
w Reliability more important than timing
w Retries are OK
n Isochronous transport
w ÒGuaranteed timingÓ
w Late data is useless
w Never retry

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 5

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 Unsupervised!
Mag Disk Scanner CD ROM CPU
ID=6 ID=2 ID=3 ID=7
Terminator
Terminator (may be internal)
SCSI is typical Òsupervised cablingÓ Ñ daisy-chain; manual or fixed addresses;
terminators at ends; devices with internal terminations must be at one end

Stereo
CPU Mag Disk
Interface

CD ROM Digital Scanner Printer

Camera

Serial Bus is Òunsupervised cablingÓ Ñ Ònon-cyclic networkÓ;

automatic address selection, no terminators, locations are arbitrary
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 6
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 Data paths (peer-to-peer)

Digitized sound direct playback

Stereo Mag
CPU
Interface Disk

Live display of video image

CD
Digital Scanner Printer
ROM
Camera

Direct printing of scanned image

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 7

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 Clean up the desktop cable mess!

Keyboard
Network

Sound

Power
Serial
modem
video floppy SCS
I

serial

ADB
video serial bus modem
plus telephone/voice,
sound input, hi-fi sound,
compressed video
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 8
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 Protocols
n IEEE 1394-1995 High Speed Serial Bus
w ÒMemory-bus-likeÓ logical architecture
w Serial implementation of 1212 architecture
n IEEE 1212-1991 CSR Architecture
w Standardized addressing
w Well-defined control and status registers
w Standardized transactions
n X3T10 Serial Bus Protocol-2 and IEC 61883
w SBP-2 integrates DMA into I/O process
w IEC 1883 defines control and data for A/V devices

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 9

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 Some terminology

n ÒquadletÓ - 32-bit word

n ÒnodeÓ - basic addressable device
n ÒunitÓ - part of a node, defined by a
higher level architecture ... examples:
w SBP disk drive (X3T10 standard)
w A/V device - VCR, camcorder (IEC 61883
standard)

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 10

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 IEEE 1212 addressing
bus # 0 node # 0 IEEE 1212 0
initial 512
bus # 1 memory Serial Bus
node # 1 1024
space ROM
¥ ¥ ¥ (1st 1K)
¥ ¥ ¥ 2048
¥ ¥ ¥
¥ ¥ ¥
¥ ¥ ¥
initial
bus #1022 node # 62 private units
space
bus #1023 node # 63
register
(local bus) (broadcast)
256M

Example: 0x3FF 0x3F 0xFFFFF 0x0000200

= all cycle timer registers on local bus

n 1394 uses Ò64-bit fixedÓ addressing

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 11

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 IEEE 1394 protocol Stack
Configuration &
Error Control
Read, Write, Lock
Isochronous
Channels
Transaction Layer
Serial Bus Management

Packets

Link Layer
Cycle Control Packet Transmitter Packet Receiver

Symbols

Physical Layer
Encode/Decode Arbitration Media Interface

Firmware Electrical Signals

& Mechanical Interface
Hardware

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 12

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 Cable interface
Cable Media

Cable
Interface Cable Cable Cable
(port n) Interface Interface Interface
(port 1) (port 2) (port n)

arbitration and resynch

arbitration and resynch
Link Interface PHY B
Link Interface PHY A
Serial Bus
Higher Layers Serial Bus Higher Layers
Node B (Link & Transaction) Node A

n PHY transforms point-to-point cable links into a

logical bus
n Cables and transceivers are bus repeaters

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 13

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 Cable media
n 3-pair shielded cable
w Two pairs for data transport
w One pair for peripheral power
n Small and rugged connector
w Two sockets in the same area as
one mini-DIN socket
n CMOS transceiver
w 220 mV differential
w 4 ma drive

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 14

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 Cable media example
Power pair:
22 AWG /0.87 diameter twisted pair
60% braided shield over foil shield
(over signal pairs - 2X)
Signal pairs: (2X)
28 AWG/0.87 diameter twisted pairs
6mm
(typical) 97% braided overall shield
0.70 Thick PVC jacket
Fillers for roundness (if required)

n Capable of operation at 400 Mbit/sec for 4.5 m

w Slightly thicker wire allows 10 meter operation
n p1394b encoding allows 800 Mbit/sec for 4.5 m
w ... perhaps even 1.6 to 3.2 Gbit/sec
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 15
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 Cable interface features

n Live attach/detach
w System protected from power on/off
cycling
w Higher layers provide simple
management

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 16

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 Peripheral power
n 8-40 VDC carried by cable
w 1394 TA defining tighter standards
w 20-30 VDC recommended for power sources
n Total available power is system
dependent
w Node power requirements must be declared in
configuration ROM
n Cable system allows up to 1.5 A per link
w Nodes can either source or sink power
w Multiple power sources on one bus provide
additional flexibility

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 17

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 Physical layer
n 98.304 Mbit/sec half duplex transport
w Data reclocked at each node
w 196.608 (2x), 393.216 (4x) Mbit/sec growth paths
w 1394b provides 8X, 16x, 32x rates
n Data encoding
w Data and strobe on separate pairs
w 1394b uses 8b10b encoding full duplex
w Automatic speed detection
n Fair and priority access
w Tree-based handshake arbitration
w Automatic assignment of addresses
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 18
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 Example cable PHY IC
n Two twisted pairs
A B
Port 1
A B
Port 2
A B
Port 3
A B
Port 4
for data: TPA and
Logic Logic Logic Logic
TPB
RxData
RxStrb w TPA is transmit strobe,
TxData
TxStrb receive data
RxArb
TxArb w TPB is receive strobe,
transmit data
local
clock
resynch w Both are bidirectional
signals, both are used in
arbitration arbitration
link
interface n Reclocks repeated
packet data signals
using local clock

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 19

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 Data-strobe encoding
1 0 1 1 0 0 0 1
Data

Strobe

Data xor Strobe

(delayed)

n Either Data or Strobe signal changes in

a bit cell, not both
w Gives 100% better jitter budget than
conventional clock/data
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 20
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 Cable arbitration phases
n Reset
w Used whenever reconfiguration needed
w Live insertion & new cycle master are examples
n Tree Identification
w Transforms a simple net topology into a tree
n Self Identification
w Assigns physical node number (Node ID)
w Exchange speed capabilities with neighbors
n Normal Arbitration
w Root has highest priority

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 21

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 Tree identification #1
branch

leaf branch

leaf leaf

n After reset, each node only knows if it is a leaf

(one connected port) or a branch (more than
one connected port)
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 22
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 Tree identification #2
root
ch ch

p p
leaf branch
ch ch

p p
leaf leaf

n After Tree ID process, the Root node is determined and each port is
labeled as pointing to a child or a parent
w Root assignment is ÒstickyÓ, will normally persist across a bus reset.

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 23

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 Self identification
root
node #4
ch ch

p p
leaf branch
node#0 node #3
ch ch

p p
leaf leaf
node #1 node #2

n After the self ID process, each node has a unique

physical node number, and the topology has been
broadcast
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 24
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 Normal arbitration #1
root
node #4
ch ch

request
p p
leaf branch
node#0 node #3
ch ch

request

p p
leaf leaf
node #1 node #2

n Suppose nodes #0 and #2 start to arbitrate at

the same time, they both send a request to
their parent ...
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 25
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 Normal arbitration #2
root
node #4
ch ch

request
request deny
p p
leaf branch
node#0 node #3
ch ch

deny request

p p
leaf leaf
node #1 node #2

n The parents forward the request to their parent

and deny access to their other children ...

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 26

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 Normal arbitration #3
root
node #4
ch ch
grant

request deny
p p
leaf branch
node#0 node #3
ch ch

deny request
deny
p p
leaf leaf
node #1 node #2

n The root grants access to the first request (#0), and

the other parent withdraws it's request and passes on
the deny ...
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 27
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 Normal arbitration #4
root
node #4
ch ch
grant

data prefix deny

p p
leaf branch
node#0 node #3
ch ch

deny
deny
p p
leaf leaf
node #1 node #2

n The winning node #0 changes its request to a data

transfer prefix, while the loosing node #2 withdraws
its request ...
©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 28
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 Normal arbitration #5
root
node #4
ch ch

data prefix data prefix

p p
leaf branch
node#0 node #3
ch ch

data prefix
data prefix
p p
leaf leaf
node #1 node #2

n The parent of node 1 sees the data prefix and withdraws the grant, and
now all nodes are correctly oriented to repeat the packet data (a "deny"
is a "data prefix!) ...

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 29

Permission to copy granted as long as this notification is retained, some text and figures based on 5/96 1394 Technical Summary from Apple Computer
 Link layer

n Implements acknowledged
datagram service
w Called a "subaction" of arbitration, packet
transmission, and acknowledge
n Flexible addressing using 1212
architecture
w Direct 64-bit addressing (48 bits per node)
w Hierarchical addressing for up to 63 nodes
on 1023 busses

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 30

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 Isochronous transport

n Optional
w But required for multimedia applications
n Multiple "channels" each 125 µsec
"cycle" period
w Channel count limited by available bandwidth
n Variable channel size up to ≈1000
bytes/cycle
w Up to ≈2000 bytes/cycle at 196 Mbit/sec

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 31

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 Link layer operation

Requester Responder
Link layer Link layer
arbitration &
Link request packet
transmission

Link indication

Link response

Link acknowledge
(not present for
confirmation
broadcast or
isochronous)

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 32

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 Example packets
subaction acknowledge 8 subaction
16 16 16 48 32 32
gap gap gap
dest source destination 32-bit
arb ID codes ID offset data
CRC ack

≥ 1 µsec ≈ 0.2 µsec ≥ 1 µsec

4-byte packet ≈ 0.5 µsec
< 1 µsec ≤ 0.75 µsec
160 bits @ 98.304 Mbit/sec ≈ 1.6 µsec
r
ade
he
e
ntir
160 e 2048 32
subaction subaction
gap data gap
256-byte packet
2240 bits @ 98.304 Mbit/sec ≈ 22.8 µsec

n Actual efficiency very good

w 10 Mbytes/sec information throughput including all of the SBP disk
protocol using 100 Mbit/sec rate (~80%)

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 33

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 Fairness interval

fairness interval N
fairness fairness
interval N-1 owner A owner B owner M interval N+1
ack

ack

ack

ack

ack
data arb data arb data •¥• •¥
arb ¥ arb data arb data
subactio
n
arbitration subaction gaps arbitration reset gap
reset gap

n Fairness Interval is bounded by Òarbitration

reset gapsÓ
n Reset gaps are longer than normal
subaction gaps

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 34

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 Fair arbitration
fairness fairness interval N fairness
interval N-1 interval N+1

arbitration reset gap

arbitration reset gap

arb node A arb node B arb node C
arbitration_enable flag

node A

node B

node C

set at arbitration reset gap cleared when node wins arbitration

n Each node gets one access opportunity

each Fairness Interval
w special case for isochronous data

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 35

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 Cycle structure
isochronous asynchronous
(short) gaps (long) gaps

cycle #m-1 cycle #m cycle #m+1

packet cycle start packet packet cycle start

ch J ch k ch N ch J
A data = x B C data = y

cycle #m cycle #m+1

start delay = x start delay = y

nominal cycle period = 125 µsec ± 100 PPM

cycle synch cycle synch

n The cycle start is sent by the cycle master,

which must be the root node

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 36

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 Transaction layer

Requestor Responder
Transaction Transaction
Layer Layer
Transaction trans
Request actio
i n f o r n control
matio
n Transaction
includes data if Indication
"write" or "lock"
tatu s
o n s
r a n s acti t i o n Transaction
t ma
infor Response
Transaction includes data if
Confirmation "read" or "lock"

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 37

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 Multiple transaction types

n Simplified 4-byte (quadlet) read and

write are required
n Variable-length block read and write
are optional
n Lock transactions optional
w Swap, Compare-and-swap needed for
bus management

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 38

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 Efficient media usage
n Split transactions required
w Transactions have request and
response parts
w Bus is never busy unless data is actually
being transferred
n Request and response can be unified
two ways
w "Read" and "Lock" can have
concatenated subactions
w "Write" can have immediate completion

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 39

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 Split transaction
Requester Responder
Transaction Link Link Transaction
Layer Layer Layer Layer
n Request and Read
Request
Link
Request Request

response have Packet Link

Indication

separate Read
subactions Conf
(pend) Resp
Indication
Ack (pend)
(pend)
Other Link-Layer operations can
take place between these two
subactions, including sending Link Read
Request
other transaction requests or Resp Response
Link Packet
(complete,
responses Indication
with data)

Read Conf
Confirmation Resp (compl)
(complete, with (compl) Ack
data) (compl)

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 40

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 Concatenated transaction
n Used if responder Requester Responder
is fast enough to Transaction Link
Layer Layer
Link Transaction
Layer Layer
return data before Read Link
Request Request
ack is completed Request
Packet Link
Indication

Read
Conf
(pend)
Indication
Resp
Ack (pend)
(pend) Link
the responder does not release the bus Request
Read
Resp
after sending the ack, sends response Link Packet Response
packet within 1.5µsec Indication (complete,
with data )
Read Conf
Confirmation Resp (compl)
(complete, with (compl) Ack
data) (compl)

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 41

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 Unified transaction
Requester Responder
Transaction Link Link Transaction
Layer Layer Layer Layer
Write Request Link
Req Req
Packet Link
Ind

Write Indication
Write Response
(complete)
Conf
(comp) Resp
Ack (comp)
Write Confirmation (comp)
(complete)

n Only used for write transactions

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 42

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 Bus management
n Automatic address assignment
w Done in physical layer with self-ID process
w Root (cycle master) is ÒstickyÓ between bus resets
n Resource management
w Isochronous channels and bandwidth (also ÒstickyÓ ...
stay allocated between bus resets).
w Power
n Standardized addresses and configuration
ROM from IEEE 1212 architecture

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 43

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 Resource management
n Done with 4 registers, each with
compare-swap capability
w Bus manager ID
w holds 6-bit physical ID of current bus manager
w Bandwidth available
w holds 13-bit count of time available for
isochronous transmission
w Channels available
w two 32-bit registers with a bit for each of the 64
possible isochronous channels

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 44

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 Compare-swap operation:

n request has Ònew dataÓ and ÒcompareÓ

values
n responder compares current value
(Òold dataÓ) at requested address with
ÒcompareÓ value
n if equal, the data at the address is
replaced with Ònew dataÓ value
n in all cases, Òold dataÓ is returned to
requester

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 45

Permission to copy granted as long as this notification is retained, some text and figures based on 5/96 1394 Technical Summary from Apple Computer
 Using compare-swap
n Example: allocate bandwidth
test_bw = read4 (addr = bandwidth_available);
old_bw = test_bw + 1; // force entry into loop 1st time
while (old_bw != test_bw) {
old_bw = test_bw;
new_bw = old_bw - bandwidth_needed;
if (new_bw < 0) fail; // all out of bandwidth
test_bw = compare_swap (addr = bandwidth_available,
new_data = new_bw, compare = old_bw); }

n test_bw will be equal to old_bw if no other

node has altered the bandwidth_available
register between the time it was read and
the time of the compare_swap

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 46

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 Where are the bus resource
registers?
n On bus reset PHY builds network, assigns
addresses, sends self-ID packets
w power requirements/capabilities, maximum speed
rating, port status (child, parent, unconnected)
w ÒcontenderÓ or not
w link (higher layers) running or not
n Highest numbered node with both contender and
link-on bit is Òisochronous resource managerÓ
w this is the node that has the four resource manager
registers

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 47

Permission to copy granted as long as this notification is retained, some text and figures based on 5/96 1394 Technical Summary from Apple Computer
 Automatic reallocation & recovery of
resources
n When self_ID completes:
w all nodes with allocated bandwidth and channels
before bus reset reallocate their resources
n after one second:
w nodes with new bandwidth or channel request may
ask for new resources
w nodes keep resources they had before bus reset!
w resources allocated to nodes removed from bus
are automatically restored!
n Bus manager reallocated the same way

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 48

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 Automatic restart of
isochronous operation
n Root assignment is persistent across bus reset
w Cycle master operation restarts after bus reset if node is
still root (normal case)
n Nodes assume that bandwidth and channel
allocations are still good
w Automatically restart sending when receive cycle start
n Only fails if two operating subnets are joined
w If reallocation fails, node terminates sending
w If bus over allocated, cycle master detects isoch data
sent for longer than 100 µsec and stops sending cycle
starts

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 49

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 Futures
n Gigabit rates and fiber (P1394B high speed)
w 800 Mbit/sec - 3.2 Gbit/sec
n Fast reset (P1394A)
n Support for very low power (P1394A)
w Òsuspend-resumeÓ
n Redundant gap removal (P1394A)
w ÒAccelerated ACKÓ, fly-by concatenation
n Bridging issues (P1394.1)
w for > 63 devices, or for isolation of high-bandwidth
local traffic

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 50

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 How does 1394 help?
n Much better human interface
w smaller, more rugged connectors with
defined usage
w Hot plugging, no manual configuration
n Excellent real performance
w High true data rates
w Direct map to processor I/O model
w DMA is simple: CPU memory directly
available to peripherals
w example: SBP supports direct
scatter/gather buffers

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 51

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 ... but even more important
n It's inexpensive
w For computers, itÕs already almost as
cheap as single-ended 8-bit SCSI
w will be cheaper since it's silicon-intensive
w Much less expensive for peripherals and
consumer electronics
n Direct support for isochronous data
w THE choice for digital consumer video,
high-end audio
w Media servers get cheaper

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 52

Permission to copy granted as long as this notification is retained, some text and figures based on 5/96 1394 Technical Summary from Apple Computer
 Getting documentation
n ÒIEEE 1394-1995 High Performance Serial BusÓ
w IEEE Standards Office +1-908-981-1393, http://www.ieee.org
w P1394a balloting under way (first round closed June 11, 1998),
so new version will be available in 1999.
w P1394.1 and p1394b drafts available via internet, see
http://www.zayante.com/p1394b
n Internet email reflectors
w Òstds-1394@majordomo. ieee.orgÓ (p1394a) and
Òstds-1394-1@majordomo. ieee.orgÓ (p1394.1) É send
ÒhelpÓ to Òmajordomo@majordomo. ieee.orgÓ
w Ò[email protected] Ó, subscription information at
http://www.zayante.com/p1394b
n 1394 Trade Association
w http://www.1394ta.org

©1998 Zayante, Inc. Michael Johas Teener/1394 Technical Summary Slide 53

Permission to copy granted as long as this notification is retained, some text and figures based on 5/96 1394 Technical Summary from Apple Computer