Atheros Ar8032 PDF

Data Sheet
September 2009
AR8032 Integrated 10/100 Fast Ethernet Transceiver

General Description Manufactured in a standard CMOS process, the
AR8032 is packaged in a 32-pin QFN, featuring
The Atheros AR8032 Fast Ethernet transceiver a small body size of 5 x 5mm.
is a highly integrated physical layer device that
transmits and receives high-speed data over Features
standard category 5 (CAT 5) unshielded
■ 10/100 BASE-T IEEE 802.3 compliant
twisted pair cable.
■ Supports MII/RMII interface
The AR8032 is compliant with 100 BASE-TX
■ Low power modes with internal automatic
and 10 BASE-T IEEE 802.3 standards. The
DSP power saving scheme
AR8032 device uses advanced mixed-signal
processing technology and integrates functions ■ Fully integrated digital adaptive equalizers
such as adaptive equalization, and timing All digital baseline wander correction
recovery to deliver substantial power savings ■ Supports external 25 MHz clock source in
and operation in noisy environments. MII mode
The AR8032 device supports the Media
Independent Interface (MII) and Reduced
Media Independent Interface (RMII) for direct ■
RMII mode
P Y
■ Supports external 50 MHz clock source in
Automatic speed downshift mode
O
connection to a Fast Ethernet-capable MAC. ■ Automatic MDI/MDIX crossover
■ Automatic polarity correction
C
The AR8032 supports the Atheros Cable
Diagnostic Test (CDT) feature, which uses Time ■ Loopback modes for diagnostics
Domain Reflectometry (TDR) technology to ■ IEEE 802.3u compliant Auto-Negotiation
quickly and remotely identify potential cable
malfunctions without deploying field support
personnel or bringing down the network. The
AR8032 solution detects and reports issues
O T ■
■
■
Software programmable LED modes
Cable Diagnostic Test (CDT)
Requires only one 3.3V power supply
N
such as PHY malfunctions, bad/marginal cable ■ 32-pin QFN 5mm x 5 mm package
or patch cord segments or connectors, thus
significantly reducing installation time, cable
cost.
DO
debug efforts, and overall network support
AR8032 Functional Block Diagram

Symbol MII
DAC
Encoder Tx
MDIP/ AGC
N[0:1]
Feed Decision Symbol
MII
PGA ADC Forward Feedback Decoder/ Rx
Equalizer Equalizer Alignment
Timing & Phase

PMA
Recovery
Auto- MII Management

DLL
Negotiation Registers
© 2009 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®,
Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-
Sustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros
Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL • 1
P Y
CO
O T
N
DO
2 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

2 • September 2009 COMPANY CONFIDENTIAL
Table of Contents
General Description......................................... 1 page)......................................... 30
Features ............................................................. 1 4.1.8 Function Control Register ..... 31
AR8032 Functional Block Diagram ............... 1 4.1.9 PHY Specific Status Register 33
1 Pin Descriptions ......................................... 5 4.1.10 Interrupt Enable Register ...... 34
2 Functional Description .............................. 9 4.1.11 Interrupt Status Register ....... 36
2.1 Transmit Functions ............................. 9 4.1.12 Smart Speed Register ............. 38
2.2 Receive Functions................................ 9 4.1.13 Receive Error Count Register 40
2.2.1 Decoder Modes ......................... 9 4.1.14 Virtual Cable Tester Control
2.2.2 Analog to Digital Converter . 10 Register .................................... 40
2.2.3 Baseline Wander Canceller ... 10 4.1.15 LED Control Register............. 41
2.2.4 Digital Adaptive Equalizer ... 10 4.1.16 Manual LED Override Register
2.2.5 Auto-Negotiation.................... 10 42
2.2.6 Smartspeed Function ............. 10 4.1.17 Virtual Cable Tester Status Reg-
ister ........................................... 43
2.2.7 Polarity Correction ................. 10
Y
4.1.18 Debug Port (Address Offset Set)
2.3 Loopback Modes ............................... 11
Register .................................... 43
2.3.1 Digital Loopback .................... 11
2.3.2 External Cable Loopback....... 11
2.3.3 Cable Diagnostic Test............. 11
O P
4.1.19 Debug Port 2 (R/W Port) Regis-
ter .............................................. 44
C
4.2 Power Saving and Debug Register
2.3.4 LED Interface........................... 11 Summary ............................................ 45
T
2.3.5 Power Supplies ....................... 11 4.2.20 10Base-T Test Configuration
2.3.6 Low Power Modes.................. 11 Register .................................... 45
2.3.7 Hibernation Mode .................. 11
3 Electrical Characteristics ......................... 13
3.1 Absolute Maximum Ratings............ 13
NO 4.2.21 100Base-TX Test Configuration
Register .................................... 46
4.2.22 Hibernate Control Register ... 48
4.2.23 Power Saving Control............ 49
O
3.2 Recommended Operating Conditions
13 5 Package Dimensions................................ 51
D
3.3 XTAL/OSC Timing........................... 14
3.4 MII DC Characteristics ..................... 15
3.5 MDIO Characteristics ....................... 16
3.5.8 MDIO Timing.......................... 16
3.6 Power-On Strapping ......................... 18
6 Ordering Information.............................. 53
3.7 Typical Power Consumption Parame-

ters ....................................................... 18
4 Register Descriptions ............................... 21
4.1 PHY Register Summary ................... 21
4.1.1 Control Register ...................... 22
4.1.2 Status Register......................... 24
4.1.3 PHY Identifier ......................... 26
4.1.4 PHY Identifier 2 ...................... 26
4.1.5 Auto-Negotiation Advertise-
ment Register .......................... 27
4.1.6 Auto-Negotiation Expansion
Register..................................... 29
4.1.7 Link partner ability register(base
Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 3

COMPANY CONFIDENTIAL September 2009 • 3
PY
C O
O T
N
D O

1. Pin Descriptions
This section contains a package pinout for the The following nomenclature is used for signal
AR8032 QFN 32pin and a listing of the signal types described in Table 1-1:
descriptions (see Figure 1-1).
D Open drain
The following nomenclature is used for signal
names:
IA Analog input
NC No connection to the internal die I Digital input
is made from this pin
IH Digital input with histeresis
_L At the end of the signal name,
indicates active low signals I/O Digital input/output
P Power OA Analog output
O Digital output
PD
Y
Internal pull-down for digital
input
P
O
PU Internal pull-up for digital input
T C
NO
DO

Figure 1-1 shows the pinout diagram for the
AR8032.
TXD1
TXD3
REXT
LED0
TXD2
LED1
COL
CRS
32 31 30 29 28 27 26 25
VDD12_REG 1 24 TXD0
VDD3 2 23 TXEN
VDD25_REG 3 22 TXC
RX‐ 4 21 INTP
AR8032
RX+ 5 20 RXER
TX‐ 6 19 RXC
TX+
XO
7
8
P Y
18 RX_DV
17 VDD25
9 10 11
CO
12 13 14 15 16
RXD<3>
RXD<0>
RXD<2>
RXD<1>
MDIO
MDC
RST#
XI
Figure 1-1. Pinout Diagram
O T
N
NOTE: There is an exposed ground pad on the
back side of the package.
DO

Table 1-1. Signal to Pin Relationships and Descriptions
Symbol Pin Type Description

VDD12_REG 1 AO 1.2V regulator output. A 1 uF plus a 0.1 uF cap needed to stabilize
the output
VDD3 2 P 3.3V power supply.
VDD25_REG 3 AO 2.5V regulator output. A 1 uF ceramic cap needed to stabalize the
output. It is for analog, digital I/O and the transformer center taps.
RX- 4 AI, AO Media Dependent Interface 0, terminate with a 49.9Ω resister and
connect to XFMR
RX+ 5 AI, AO Media Dependent Interface 0, terminate with a 49.9Ω resister and
connect to XFMR
TX- 6 AI, AO Media Dependent Interface 1, terminate with a 49.9Ω resister and
connect to XFMR
TX+ 7 AI, AO Media Dependent Interface 1, terminate with a 49.9Ω resister and
Y
connect to XFMR
P
XO 8 AO Crystal oscillator output. 27 pF to GND.
XI 9 AI Crystal oscillator input. 27 pF to GND. An external 25/50 MHx
O
clock source with swing from 0 to 1.2V can inject from this pin
when a crystal is not used and the two 27pF caps removed. The 25
RST# 10 IH, PU
C
Mhz clock input is for MII mode, while the 50 Mhz clock input is
for RMII mode.
T
System reset input.
O
MDIO 11 I/O, D, PU Management data.
MDC 12 I, PU Management clock reference.
RXD<3> 13 I/O, PU,
POS
N MII Receive data output [3].
O
RXD<2> 14 I/O, PD, MII Receive data output [2].
POS
RXD<1>
RXD<0>
VDD25
D 15
16
17
I/O, PD,
POS
I/O, PU,
POS
P
MII/RMII Receive data output [1].
MII/RMII Receive data output [0].
2.5V I/O power, connect with pin 3, 0.1uF to GND.

RX_DV 18 I/O, PD, Receive data valid output
POS
RXC 19 I/O, PD, Receive clock output
RXER 20 I/O, PD Receive error output
INTP 21 I/O, PU, Interrupt Output
POS
TXC 22 I/O, PU Transmit clock output
TXEN 23 I, PU Transmit data enable
TXD0 24 I, PD MII/RMII Transmit data input [0]
TXD1 25 I, PD MII/RMII Transmit data input [1]

Table 1-1. Signal to Pin Relationships and Descriptions (continued)
Symbol Pin Type Description

TXD2 26 I, PD MII Transmit data input [2]
TXD3 27 I, PD MII Transmit data input [3]
COL 28 I/O, PD, Collision Detect output
POS
CRS 29 I/O, PD Carrier Sense output
POS
LED0 30 I/O, PU Programable LED 0, the default indicates Link and Activity
POS
LED1 31 I/O, PU Programmable LED 1The default indicates Speed
POS
REXT 32 AO Connect 2.37 K to GND
PADDLE GND Gnd Ground
NOTE: All of the digital input only pads are 3.3V

input tolerant. The O and I/O pads are powered
P Y
with 2.5V power. The input level of any I/O pads
9except open-drain type) is limited to 2.5V.
CO
O T
N
DO

2. Functional Description
The Atheros AR8032 is a highly integrated transmit and receive high-speed data over
analog front end (AFE) and digital signal standard category 5 (CAT5) unshielded twisted
transceiver (see Figure 2-1), providing high pair cable.
performance with substantial cost reduction.
AFE consists of automatic gain control (AGC), See also the “AR8032 Functional Block
ADC, DAC, drivers, and clock generation. The Diagram” on page 1.
AR8032 provides physical layer functions to
Coarse
Baseline Wander
ADC
Watchdog
Fine
Programmable Gain
Amplifier Transceiver
Side
Hybrid Circuits PLL
25 MHz Crystal
Line Side
Line Driver TXDAC

AFE
Figure 2-1. Analog Front End
The AR8032 10/100 PHY is fully 802.3, 802.3u 2.2 Receive Functions
compliant, and supports the media-
independent interface (MII) and Reduced The AR8032 receive channel includes digital
Media Independent Interface (RMII) to connect gain control, feed forward adaptive equalizer,
to a Fast Ethernet-capable MAC. decision feedback equalizer, slicer, 5B/4B de-
mapper and de-scrambler, PCS receive
The AR8032 transceiver combines feed- functional block, and timing recovery logic.
forward equalizer, feedback equalizer, and
timing recovery, to enhance signal performance 2.2.1 Decoder Modes
in noisy environments. Table 2-2 describes the receive function
decoder modes.
2.1 Transmit Functions
Table 2-2. Receive Function Decoder Modes
The AR8032 transmit channel includes 4B/5B
mapper and scrambler. Table 2-1 describes the Decoder Mode Description
transmit function encoder modes. 100BASE-TX In 100BASE-TX mode, the receive
Table 2-1. Transmit Function Encoder Modes data stream is recovered and
descrambled to align to the
Encoder Mode Description symbol boundaries. The aligned
data is then parallelized and 5B/
100BASE-TX In 100BASE-TX mode, 4-bit data 4B decoded to 4-bit data. This
from the MII is 4B/5B serialized, output runs to the MII/RMII
scrambled, and encoded to a receive data pins after data stream
three-level MLT3 sequence delimiters have been translated.
transmitted by the PMA.
10BASE-T In 10BASE-T mode, the recovered
10BASE-T In 10BASE-T mode, the AR8032 10BASE-T signal is decoded from
transmits and receives Manchester then aligned.
Manchester-encoded data.

2.2.2 Analog to Digital Converter 2.2.6 Smartspeed Function
The AR8032 device employs an advanced high The Atheros Smartspeed function is an
speed ADC on each receive channel with high enhanced feature of auto-negotiation that
resolution, which results in better SNR and allows the AR8032 device to fall back in speed
lower error rates. based on cabling conditions as well as operate
over CAT3 cabling (in 10BASE-T mode) or two-
2.2.3 Baseline Wander Canceller pair CAT5 cabling (in 100BASE-TX mode).
Baseline wander results from Ethernet links By default, the Smartspeed feature is enabled.
that AC-couple to the transceivers and from Refer to the register “Smart Speed Register” on
AC coupling that cannot maintain voltage page 38, which describes how to set the
levels for longer than a short time. As a result, parameters. Set these register bits to control the
transmitted pulses are distorted, resulting in Smartspeed feature:
erroneous sampled values for affected pulses.
The AR8032 device uses an advanced baseline ■ Bit [5]: 1 = Enables Smartspeed (default)
wander cancellation circuit that continuously
■ Bits [4:2]: Sets the number of link attempts
monitors and compensates for this effect,
before adjusting
minimizing the impact of DC baseline shift on
the overall error rate. ■ Bit [1]: Timer to determine the stable link
condition
2.2.4 Digital Adaptive Equalizer
The digital adaptive equalizer removes inter- 2.2.7 Polarity Correction
symbol interference at the receiver. The digital If cabling has been incorrectly wired, the
adaptive equalizer takes unequalized signals AR8032 automatically corrects polarity errors
from ADC output and uses a combination of on the receive pairs.
feedforward equalizer (FFE) and decision
feedback equalizer (DFE) for the best-
optimized signal-to-noise (SNR) ratio.
2.2.5 Auto-Negotiation
The AR8032 device supports 10/100 BASE-T
Copper auto-negotiation in accordance with
IEEE 802.3 clauses 28 and 40. Auto-negotiation
provides a mechanism for transferring
information between a pair of link partners to
choose the best possible mode of operation in
terms of speed, duplex modes, and master/
slave preference. Auto-negotiation is initiated
upon any of the following scenarios:
■ Power-up reset
■ Hardware reset
■ Software reset
■ Auto-negotiation restart
■ Transition from power-down to power-up
■ The link goes down
If auto-negotiation is disabled, a 10BASE-T or
100BASE-TX can be manually selected using
the IEEE MII registers.

2.3 Loopback Modes 2.3.3 Cable Diagnostic Test
The Cable Diagnostic Test (CDT) feature in the
2.3.1 Digital Loopback AR8032 device uses Time Domain
Digital loopback provides the ability to loop Reflectometry (TDR) to identify remote and
transmitted data back to the receiver using local PHY malfunctions, bad/marginal cable or
digital circuitry in the AR8032 device. The patch cord segments, or connectors. Some of
registers“100Base-TX Test Configuration the possible problems that can be diagnosed
Register” on page 46 and “10Base-T Test include opens, shorts, cable impedance
Configuration Register” on page 45 are used to mismatch, bad connectors, termination
determine at which point the signal loops back mismatch, and bad magnetics. The CDT can be
(for different modes, respectively). performed when there is no link partner or
when the link partner is auto-negotiating.
Figure 2-2 shows a block diagram of digital
loopback. 2.3.4 LED Interface
The LED interface can either be controlled by
the PHY or controlled manually, independent
PH of the state of the PHY. Four status LEDs are
MAC/ PHY Y available. These can be used to indicate
MII
Switch Digital AF operation speed, duplex mode, and link status.
E The LEDs can be programmed to different
status functions from their default value. They
can also be controlled directly from the MII
Figure 2-2. Digital Loopback
register interface.
2.3.5 Power Supplies

2.3.2 External Cable Loopback The AR8032 device requires only one power
External cable loopback loops MII Tx to MII Rx supply: 3.3V.
through a complete digital and analog path
and an external cable, thus testing all the 2.3.6 Low Power Modes
digital data paths and all the analog circuits. The AR8032 device supports the software
Figure 2-3 shows a block diagram of external power-down low power mode. The standard
cable loopback. IEEE power-down mode is entered by setting
the POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22 equal to one.
PH
MAC/ In this mode, the AR8032 device ignores all
RJ-45
PHY Y
Switc MII MAC interface signals except the MDC/MDIO.
Digital AF
h It does not respond to any activity on the CAT
E
5 cable. The device cannot wake up on its own.
It can only wake up by setting the
POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22” to 0.
Figure 2-3. External Cable Loopback
2.3.7 Hibernation Mode
The AR8032 device supports hibernation
mode. When the cable is unplugged, the
AR8032 will enter hibernation mode after
about 10 seconds. The power consumption in
this mode is very low compared to the normal
mode of operation. When the cable is re-
connected, the AR8032 wakes up and normal
functioning is restored.

3. Electrical Characteristics
3.1 Absolute Maximum Ratings
Table 3-1 summarizes the absolute maximum
ratings and Table 3-2 lists the recommended
operating conditions for the AR8032. Absolute
maximum ratings are those values beyond
which damage to the device can occur.
Functional operation under these conditions,
or at any other condition beyond those
indicated in the operational sections of this
document, is not recommended.
Table 3-1. Absolute Maximum Ratings
Symbol Parameter Max Rating Unit

VDD33 3.3V supply voltage 3.8 V
Tstore Storage temperature –65 to 150 °C
ESD Electrostatic discharge tolerance 2000 V
3.2 Recommended Operating Conditions

Table 3-2. Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit

VDD33 3.3V supply voltage 3.0 3.3 3.6 V
TA Ambient Temperature 0 — 70 °C
ΤJ Junction Temperature 0 — 125 °C
ΨJT Thermal Dissipation Coefficient — 4 — °C/W
NOTE: The following condition must be satisfied:

ΤJmax > TCmax + ΨJT x PTypical
Where:
ΤJmax = Maximum allowable temperature of the Junction

TCmax = Maximum allowable Case temperature
ΨJT = Thermal Dissipation Coefficient
PTypical = Typical power dissipation

3.3 XTAL/OSC Timing
Figure 3-1 shows the XTAL timing diagram.
tXI_PER
tXI_HI tXI_LO
VIH-XI
VIL-XI
tXI_RISE tXI_FALL
Figure 3-1. XTAL/OSC Timing Diagram
Table 3-3. XTAL/OSC Timing — MII mode

T_XI_PER XI/OSCI Clock Period 40.0 - 40.0 40.0 + ns
50ppm 50ppm
T_XI_HI XI/OSCI Clock High 14 20.0 ns
T_XI_LO XI/OSCI Clock Low 14 20.0 ns
T_XI_RISE XI/OSCI Clock Rise Time, VIL (max) 4 ns
to VIH (min)
T_XI_FALL XI/OSCI Clock Fall time, VIL (max) 4 ns
to VIH (min)
V_IH_XI The XTLI input high level 0.8 1.4 V
V_IL_XI The xtli input low lever voltage -0.3 0.15 V
Table 3-4. XTAL/OSC Timing — RMII mode

T_XI_PER XI/OSCI Clock Period 20.0 - 20.0 20.0 + ns
50ppm 50ppm
T_XI_HI XI/OSCI Clock High 8 10.0 ns
T_XI_LO XI/OSCI Clock Low 8 10.0 ns
T_XI_RISE XI/OSCI Clock Rise Time, VIL (max) 2 ns
to VIH (min)

T_XI_FALL XI/OSCI Clock Fall time, VIL (max) 2 ns
to VIH (min)
V_IH_XI The XTLI input high level 0.8 1.4 V
V_IL_XI The xtli input low lever voltage -0.3 0.15 V
3.4 MII DC Characteristics

Table 3-5 shows the MII DC characteristics.
Table 3-5. MII DC Characteristics
Symbol Parameter Min Max Unit
VOH Output high voltage 2.0 3.0 V
VOL Output low voltage GND 0.4 V
VIH Input high voltage 1.7 — V
VIL Input low voltage — 0.7 V
IIH Input high current — 15 μA
IIL Input low current –15 — μA
Figure 3-2 shows the MII input AC timing

diagram.
VIH
VIL
TXC
VIH
VIL
TXD[3:0]/TXEN
Min setup 5 ns 0 ns Min
Figure 3-2. MII Input AC Timing Diagram

Figure 3-3 shows the MII output AC timing
diagram.
VIH
RXC VIL
VIH
RXD[3:0]/RX_DV/RXER VIL
100Base-TX: 15 to 25ns
10Base-T: 15 to 205ns
Figure 3-3. MII Output AC Timing Diagram
3.5 MDIO Characteristics

Table 3-6 shows the MDIO DC characteristics.RMII Timing
Table 3-6. MDIO DC Characteristics
VOH Output high voltage 2.4 — V
VOL Output low voltage — 0.4 V
IIH Input high current — –0.4 mA
IIL Input low current 0.4 — mA
3.5.8 MDIO Timing

Figure 3-4 shows the MDIO timing diagram.
tmdc
t mdch tmdcl
MDC
t mdsu t mdhold
MDIO
Figure 3-4. MDIO Timing Diagram

Table 3-7. MDIO Timing

tmdc MDC Period 100 nS
tmdcl MDC Low Period 40 nS
tmdch MDC High Period 40 nS
tmdsu MDIO to MDC rising setup time 10 nS
tmdhold MDIO to MDC rising hold time 10 nS
Table 3-8 shows the RMII AC timing

characteristics.
Table 3-8. RMII AC Timing
Tck XI Period — 20 nS
Tsu TXEN, TXD to XI rising setup time 4 — nS
Thold TXEN, TXD to XI rising hold time 2 — nS
Tdly XI to RX_DV, RXD output delay 3 14 nS
Figure 3-5 shows the AC RMII timing diagram.
tck
XI
tsu
thold
TXEN
TXD[1:0]
tdly
RX_DV
RXD[1:0]
Figure 3-5. RMII AC Timing Diagram

3.6 Power-On Strapping
Table 3-9 shows the pin-to-PHY core configuration signal power-on strapping.
Table 3-9. Power-On Strapping[1]

PHY Core
PHY Pin Name Pin Configuration Signal Description
RXD<3> 13 PHYADDRESS[0] PHY address
RXD<2> 14 PHYADDRESS[1]
RXD<1> 15 PHYADDRESS[2]
RXD<0> 16 DUPLEX 1 = Full Duplex
RXDV 18 CONFIG2 CONFIG[2:0]
000 = MII
001 = RMII
All other binary combinations are Reserved.
CRS 29 CONFIG1
COL 28 CONFIG0
TXC 22 EN_AB Enable class AB mode
RXC 19 POWER_DOWN Enable Power Down mode
RXER 20 ISOLATE 1 = enable
0 = disable
INTP 21 TESTMODE 1 = normal operation
0 = test mode
LED0 30 AUTO- 1 = enable
NEGOTIATION 0 = disable
LED1 31 SPEED 1 = 100Mbps
0 = 10 Mbps
[1]Default values: 0 = Pull-down, 1 = Pull-up with 10 K resistor.
3.7 Typical Power Consumption Parameters

The following conditions apply to the typical
characteristics unless otherwise specified:
VDD33 = 3.3V, Tamb = 25 °C
Table 3-10 shows the typical power drain as a function of the AR8032’s operating mode.
Table 3-10. Total System Power
Mode Current (mA) Power (mW) Description

LDPS 3 9.9 Link down, power-
saving mode
Isolate 18 59.4 Isolate mode
100F 92 303.6 100Base-T Full Duplex
10F 89 293.9 10Base-T Full Duplex
10TX 83 273.9 10Base-T Transmit

Table 3-10. Total System Power
Mode Current (mA) Power (mW) Description

10RX 25 82.5 10Base-T Receive
10IDLE 21 69.3 10Base-T Idle

4. Register Descriptions
Table 4-1 shows the reset types used in this Table 4-1. Reset Types (continued)
document.
Table 4-1. Reset Types Type Description
R/W Read/Write
Type Description
RWC Read/Write Clear. After read, register
LH Register field with latching high function. field is cleared to zero.
If status is high, then the register is set to
one and remains set until a read operation RWR Read/Write Reset. All bits are readable
is performed through the management and writable. After reset or read, the
interface or a reset occurs. register field is cleard to zero.
LL Register field with latching low function. RWS Read/Write Set. All bits are readable and
If status is low, then the register is cleared writable. After reset or read, the register
to a zero and remains cleared until a read field is set to a non-zero value specified in
operation is performed through the the text.
management interface or a reset occurs. SC Self-Clear. Writing a one to this register
Retain Value written to a register field takes causes the desired function to be
effect without a software reset. immediately executed, then the register
field is cleared to zero when the function
SC Self-Clear. Writing a one to this register is complete.
causes the desired function to execute
immediately, and the register field clears WO Write Only. Reads to this type of register
to zero when the function is complete. return undefined data.
Update The value written to the register field does

not take effect until a software reset is
executed. The value can still be read after
it is written.
RES Reserved for future use. All reserved bits
are read as a zero unless otherworse 4.1 PHY Register Summary
noted.
Table 4-2 summarizes the registers for the
RO Read Only AR8032.
ROC Read Only Clear. After read, register field
is cleard to zero.
Table 4-2. Register Summary

Offset Register Page
0x00 Control Register page 22
0x01 Status page 24
0x02 PHY Identifier page 26
0x03 PHY Identifier 2 page 26
0x04 Auto-Negotiation Advertisement page 29
0x05 Link Partner Ability page 30
0x06 Auto-Negotiation Expansion page 29
0x07 Reserved
0x08 Reserved
0x09 Reserved
0x0A Reserved
0x0B Reserved

Table 4-2. Register Summary (continued)
0x0C Reserved
0x0D Reserved
0x0E Reserved
0x0F Reserved
0x10 Function Control Register page 22
0x11 PHY Specific Status Register page 33
0x12 Interrupt Enable Register page 34
0x13 Interrupt Status Register page 36
0x14 Smart Speed Register page 38
0x15 Recieve Error Counter Register page 40
0x16 Virtual Cable Tester Control Register page 40
0x18 Reserved
0x19 LED Control Register page 41
0x1A Manual LED Override Register page 42
0x1B Reserved
0x1C Virtual Cable Tester Status Register page 40
0x1D Debug Port 1 (Address offset) page 43
0x1E Reserved
0x1F Reserved
4.1.1 Control Register

Offset: 0x00
Mode: Read/Write
Hardware Reset: 0
Software Reset: See field descriptions
Bit Name Type Description

15 Reset Mode R/W PHY Software Reset. Writing a "1" to this bit causes the PHY the
reset operation is done , this bit is cleared to "0" automatically. The
HW 0 reset occurs immediately.
Rst
1= PHY reset
SW SC 0 =Normal operation
Rst
14 Loopback Mode R/W When loopback is activated, the transmitter data presented on
TXD is looped back to RXD internally. Link is broken when
HW 0 loopback is enabled.
Rst
1 = Enable Loopback
SW 0 0 = Disable Loopback
Rst

13 Speed Selection Mode R/W Upon hardware reset , this bit and 0.6 bit depend upon
(LSB)
HW See anen(bit0.12) and SPEED:
Rst Desc. anen {0.6 , 0.13}
0 {0, SPEED}
SW Retain
Rst 1 2'b01
(00:10Mbps, 01:100Mbps, 10:Reserved, 11:Reserved)
12 Auto-negotiation Mode R/W Upon hardware reset, this bit depends on ANEN_PAD.
HW See 1 = Enable Auto-Negotiation Process
Rst Desc. 0 = Disable Auto-Negotiation Process
SW Retain
Rst
11 Power Down Mode R/W When the port is switched from power down to normal operation,
software reset and restart Auto-Negotiation are performed even
HW 0 when bits Reset (0.15) and Restart Auto-Negotiation (0.9) are not
Rst set by the user.
SW 0 1 = Power down
Rst 0 = Normal operation
10 Isolate Mode R/W The MII output pins are tristated when this bit is set to 1.
HW 0 The MII inputs are ignored.
Rst 1 = Isolate
0 = Normal operation
SW 0
Rst
9 Restart Auto- Mode R/W, Auto-Negotiation automatically restarts after hardware or
negotiation SC software reset regardless of whether or not the restart bit (0.9) is
set.
HW 0
Rst 1 = Restart Auto-Negotiation Process
0 = Normal operation
SW SC
Rst
8 Duplex mode Mode R/W, Upon hardware reset, this bit bit depends on
SC DUPLEX_MODE_PAD and anen bit(0.12):
HW See
Rst Desc.
0.12 0.8
SW
Rst 0 0
1 DUPLEX_MODE_PAD
1:Full Duplex
0:Half Duplex
7 Collision Test Mode R/W Setting this bit to 1 will cause the COL pin to assert whenever the
TX_EN pin is asserted.
HW 0
Rst 1 = Enable COL signal test
0 = Disable COL signal test
SW 0
Rst
6 Speed Selection Mode R/W See bit 0.13.
(MSB)
HW See
Rst Desc.
SW
Rst

5:0 RES Mode RO Reserved for future use.
HW 00000
Rst
SW 00000
Rst
4.1.2 Status Register

Offset: 0x01
Mode: Read/Write
Hardware Reset: 0
Software Reset: See field descriptions

15 100Base-T4 Mode RO 100BASE-T4.
HW 0 This protocol is not available.
Rst 0 = PHY not able to perform 100BASE-T4
SW 0
Rst
14 100Base-Tx Full- Mode RO Capable of 100Base-Tx Full-Duplex operation
Duplex
HW 1
Rst
SW 1
Rst
13 100Base-Tx Half- Mode RO Capable of 100Base-Tx Half-Duplex operation
Duplex
HW 1
Rst
SW 1
Rst
12 10 Mbps Full- Mode RO Capable of 10Base-T Full-Duplex operation
Duplex
HW 1
Rst
SW 1
Rst
11 10 Mbps Half- Mode R/W Capable of 10 Mbps Half-Duplex operation
Duplex
HW 1
Rst
SW 1
Rst
10 100Base-T2 Full- Mode RO Not able to perform 100Base-T2 Full-Duplex operation
Duplex
HW 0
Rst
SW 0
Rst

9 100Base-T2 Half- Mode R/W Not able to perform 100Base-T2 Half-Duplex operation
Duplex
HW 0
Rst
SW 0
Rst
8 Extended Status Mode RO Extended status information in register 15
HW 1
Rst
SW 1
Rst
7 RES Mode RO Reserved
HW 0
Rst
SW 0
Rst
6 MF Preamble Mode RO PHY accepts management frames with preamble suppressed
Suppression
HW 1
Rst
SW 1
Rst
5 Auto-negotiation Mode RO 1: Auto negotiation process complete
Complete 0:Auto negotiation process not complete
HW 0
Rst
SW 0
Rst
4 Remote Fault Mode RO, 1: Remote fault condition detected
LH 0:Remote fault condition not detected
HW 0
Rst
SW 0
Rst
3 Auto-Negotiation Mode R/W 1: PHY able to perform auto-negotiation
Ability
HW 1
Rst
SW 1
Rst
2 Link Status Mode RO, This register bit indicates whether the link was lost since the last
LL read. For the current link status, read
HW 0 register bit 17.10 Link Real Time.
Rst 1 = Link is up
0 = Link is down
SW 0
Rst

1 Jabber Detect Mode RO, 1: Jabber condition detected
LH 0: Jabber condition not detected
HW 0
Rst
SW 0
Rst
0 Extended Mode RO 1: Extended register capabilitites
Capability
HW 1
Rst
SW 1
Rst
4.1.3 PHY Identifier

Offset: 0x02

15:0 Orgainizationally Mode RO Orgainizationally Unique Identifer Bits 3:18
Unique Identifer
Bits 3:18 HW Always
Rst 16’h
004d
SW Always
Rst 16’h
004d
4.1.4 PHY Identifier 2

Offset: 0x03

15:0 OUI bit 19:24 Mode RO Orgainizationally Unique Identifer Bits 3:18
Model Number
Revision Number HW Always
Rst 16’h
d023
SW Always
Rst 16’h
d023

4.1.5 Auto-Negotiation Advertisement Register
Offset: 0x04

15 Next Page Mode R/W The value of this bit will be updated immediately after writing
this register. But the value written to this bit does not takes effect
HW 0 until any one of the following occurs:
Rst
o Software reset is asserted (register 0.15)
SW Update o Restart Auto-Negotiation is asserted (register 0.9)
Rst o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
If 1000BASE-T is advertised then the required next pages are
automatically transmitted. Register 4.15 should be set to 0 if no
additional next pages are needed.
1 = Advertise
0 = Not advertised
14 Ack Mode RO Must be 0
HW Always
Rst 0
SW Always
Rst 0
13 Remote Fault Mode R/W 1 = Set Remote Fault bit
HW See 0 = Do not set Remote Fault bit
Rst Desc.
SW Update
Rst
12 Reserved Mode RO Always 0.
HW Always
Rst 0
SW Always
Rst 0
11 Asymmetric Pause Mode R/W Upon hardware reset , this bit depends on ASYM_PAUSE_PAD.
HW See The value of this bit will be updated immediately after writing
Rst Desc. this register. But the value written to this bit does not takes effect
until any one of the following occurs:
SW Update o Software reset is asserted (register 0.15)
Rst o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = Asymmetric Pause
0 = No asymmetric Pause

10 PAUSE Mode R/W Upon hardware reset , this bit depends on PAUSE_PAD.
HW See The value of this bit will be updated immediately after writing
Rst Desc. this register. But the value written to this bit does not takes effect
until any one of the following occurs:
SW Update o Software reset is asserted (register 0.15)
Rst o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down to
normal operation
o Link goes down
1 = MAC PAUSE implemented
0 = MAC PAUSE not implemented
9 100BASE-T4 Mode RO Not able to perform 100BASE-T4
HW Always
Rst 0
SW Always
Rst 0
8 100BASE-TX Mode R/W The value of this bit will be updated immediately after writing
Full Duplex this register. But the value written to this bit does not takes effect
Rst
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
Half Duplex this register. But the value written to this bit does not takes effect
Rst
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
Full Duplex this register. But the value written to this bit does not takes effect
Rst
normal operation
o Link goes down
1 = Advertise
0 = Not advertised

5 Mode R/W The value of this bit will be updated immediately after writing
10BASE-TX this register. But the value written to this bit does not takes effect
Half Duplex Rst
normal operation
o Link goes down
1 = Advertise
0 = Not advertised
4:0 Selector field Mode RO Selector Field mode
HW Always 00001 = 802.3
Rst 00001
SW Always
Rst 00001
4.1.6 Auto-Negotiation Expansion Register

Offset: 0x06

15:5 RES Mode RO Reserved. Must be 0.
HW Always
Rst 0
SW Always
Rst 0
4 Parallel Detection Mode RO, LH 1: a fault has been detect
Fault 0: no fault has been detected
HW 0
Rst
SW 0
Rst
3 Link Partner Next Mode RO 1: Link partner is Next page able
Paga Able 0: Link partner is not next page able
HW 0
Rst
SW 0
Rst
2 Local Next Page Mode RO 1 = Local Device is Next Page able
Able
HW 1
Rst
SW 1
Rst

1 Page Received Mode RO, LH 1: A new page has been received
HW 0 0: No new page has been received
Rst
SW 0
Rst
0 Link Partner Auto- Mode RO 1: Link partner is auto negotiation able
Negotiation Able 0: Link partner is not auto negotiation able
HW 0
Rst
SW 0
Rst
4.1.7 Link partner ability register(base page)

Offset: 0x05

15 Next page Mode RO Received Code Word Bit 15
HW 0 1 = Link partner capable of next page
Rst 0 = Link partner not capable of next page
SW 0
Rst
14 Ack Mode RO Acknowledge
HW 0 Received Code Word Bit 14
Rst 1 = Link partner received link code word
0 = Link partner does not have Next Page ability
SW 0
Rst
13 Remote Fault Mode RO Remote Fault
Rst 1 = Link partner detected remote fault
0 = Link partner has not detected remote fault
SW 0
Rst
12 Reserved Mode RO Technology Ability Field
Rst
SW 0
Rst
11 Asymmetric Pause Mode RO Technology Ability Field
Rst 1 = Link partner requests asymmetric pause
0 = Link partner does not request asymmetric pause
SW 0
Rst

10 PAUSE Mode RO Technology Ability Field
Rst 1 = Link partner is capable of pause operation
0 = Link partner is not capable of pause operation
SW 0
Rst
9 100BASE-T4 Mode RO Technology Ability Field
Rst 1 = Link partner is 100BASE-T4 capable
0 = Link partner is not 100BASE-T4 capable
SW 0
Rst
8 100BASE-TX Mode RO Technology Ability Field
Full Duplex HW 0 Received Code Word Bit 8
Rst 1 = Link partner is 100BASE-TX full-duplex capable
0 = Link partner is not 100BASE-TX full-duplex capable
SW 0
Rst
Half Duplex HW 0 Received Code Word Bit 7
Rst 1 = Link partner is 100BASE-TX half-duplex capable
0 = Link partner is not 100BASE-TX half-duplex capable
SW 0
Rst
Full Duplex HW 0 Received Code Word Bit 6
Rst 1 = Link partner is 10BASE-T full-duplex capable
0 = Link partner is not 10BASE-T full-duplex capable
SW 0
Rst
Half Duplex HW 0 Received Code Word Bit 5
Rst 1 = Link partner is 10BASE-T half-duplex capable
0 = Link partner is not 10BASE-T half-duplex capable
SW 0
Rst
4:0 Selector field Mode RO, LH Selector Field
HW 0 Received Code Word Bit 4:0
Rst
SW 0
Rst
4.1.8 Function Control Register

Offset: 0x10

15:12 RES Mode R/W Reserved
HW 0
Rst
SW Retain
Rst
11 Assert CRS on Mode R/W 1 = when transmitting, crs_o is asserted to 1;
Transmit 0 = crs_o is asserted to 1 only when receiving.
HW 1
Rst When in RMII mode, this bit is fixed to 0.
SW Retain
Rst
10 RES Mode R/W Reserved
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW Retain
Rst
6:5 MDI Crossover Mode R/W Changes to these bits are disruptive to the normal operation;
Mode therefore any changes to these registers must be followed by a
HW 11 software reset to take effect.
Rst
00 = Manual MDI configuration
SW Update 01 = Manual MDIX configuration
Rst 10 = Reserved
11 = Enable automatic crossover for all modes
HW 0
Rst
SW Retain
Rst
2 SQE Test Mode R/W SQE Test is automatically disabled in full-duplex mode
HW 0 1 = SQE test enabled
Rst 0 = SQE test disabled
SW Retain
Rst
HW 0
Rst
SW Retain
Rst

0 Disable Jabber Mode R/W Jabber has effect only in 10BASE-T half-duplex mode.
HW 0 1 = Disable jabber function
Rst 0 = Enable jabber function
SW Retain
Rst
4.1.9 PHY Specific Status Register

Offset: 0x11

15:14 Speed Mode RO These status bits are valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed or Auto-
HW 00 Negotiation is disabled.
Rst
11 = Reserved
SW Retain 10 = Reserved
Rst 01 = 100 Mbps
00 = 10 Mbps
13 Duplex Mode RO This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed or Auto-
HW Negotiation is disabled.
Rst
1 = Full-duplex
SW 0 = Half-duplex
Rst
12 Page Received Mode RO 1 = Page received
(real-time) 0 = Page not received
HW 0
Rst
SW Retain
Rst
11 Speed and Duplex Mode RO When Auto-Negotiation is not enabled, 17.11 = 1 for force speed
Resolved mode.
HW 0
Rst 1 = Resolved
0 = Not resolved
SW 0
Rst
10 Link (real-time) Mode RO 1 = Link up
HW 0 0 = Link down
Rst
SW 0
Rst
9:7 RES Mode RO Reserved
HW Always
Rst 0
SW Always
Rst 0

6 MDI Crossover Mode RO This status bit is valid only after resolved bit 17.11 = 1. The
Status resolved bit is set when Auto-Negotiation is completed or Auto-
HW 0 Negotiation is disabled. This bit is 0 or 1 depending on what is
Rst written to 16.6:5 in manual configuration mode. Register 16.6:5
SW Retain are updated with software reset.
Rst 1 = MDIX
0 = MDI
5 Wirespeed Mode RO 1 = Downgrade

Downgrade 0 = No Downgrade
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
3 Transmit Pause Mode RO This is a reflection of the MAC pause resolution. This bit is for
Enabled information purposes and is not used by the device.
HW
Rst This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed; While in
SW force mode, this bit is set to be 0.
Rst 1 = Transmit pause enabled
0 = Transmit pause disabled
2 Receive Pause Mode RO This is a reflection of the MAC pause resolution. This bit is for
Enabled information purposes and is not used by the device.
HW
Rst This status bit is valid only after resolved bit 17.11 = 1. The
resolved bit is set when Auto-Negotiation is completed; While in
SW force mode, this bit is set to be 0.
Rst 1 = Receive pause enabled
0 = Receive pause disabled
1 Polarity (real-time) Mode RO 1 = Reversed
HW 0 0 = Normal
Rst
SW Retain
Rst
0 Jabber (real-time) Mode RO 1 = Jabber
HW 0 0 = No jabber
Rst
SW Retain
Rst
4.1.10 Interrupt Enable Register

Offset: 0x12

15 Auto-Negotiation Mode R/W 1 = Interrupt enable
Error Interrupt HW 0 0 = Interrupt disable
Enable Rst
SW Retain
Rst
14 Speed Changed Mode R/W 1 = Interrupt enable
Interrupt Enable 0 = Interrupt disable
HW 0
Rst
SW Retain
Rst
13 Duplex Changed Mode R/W 1 = Interrupt enable
Interrupt Enable HW 0 0 = Interrupt disable
Rst
SW Retain
Rst
12 Page Received Mode R/W 1 = Interrupt enable
Interrrupt Enable 0 = Interrupt disable
HW 0
Rst
SW Retain
Rst
11 Link Fail Interrupt Mode R/W 1 = Interrupt enable
Enable 0 = Interrupt disable
HW 0
Rst
SW Retain
Rst
10 Link Success Mode R/W 1 = Interrupt enable
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW 0
Rst

HW 0
Rst
SW Retain
Rst
6 MDI Crossover Mode R/W 1 = Interrupt enable
Changed Interrupt 0 = Interrupt disable
Enable HW 0
Rst
SW Retain
Rst
5 Wirespeed- Mode R/W 1 = Interrupt enable
downgrade 0 = Interrupt disable
Interrupt Enable HW 0
Rst
SW Retain
Rst
HW 000
Rst
SW Retain
Rst
1 Polarity Changed Mode R/W 1 = Interrupt enable
HW 0
Rst
SW Retain
Rst
0 Jabber Interrupt Mode R/W 1 = Interrupt enable
Enable 0 = Interrupt disable
HW
Rst
SW
Rst
4.1.11 Interrupt Status Register

Offset: 0x13

15 Auto-Negotiation Mode RO, LH An error is said to occur if MASTER/SLAVE does not resolve,
Error parallel detect fault, no common HCD, or link does not come up
HW 0 after negotiation is completed.
Rst
1 = Auto-Negotiation Error
SW Retain 0 = No Auto-Negotiation Error
Rst

14 Speed Changed Mode RO, LH 1 = Speed changed
HW 0 0 = Speed not changed
Rst
SW Retain
Rst
13 Duplex Changed Mode RO, LH 1 = Duplex changed
HW 0 0 = Duplex not changed
Rst
SW Retain
Rst
12 Page Received Mode RO, LH 1 = Page received
HW 0 0 = Page not received
Rst
SW Retain
Rst
11 Link Fail Interrupt Mode RO, LH 1 = Link down happened.
HW 0 0 = Link down not happened.
Rst
SW Retain
Rst
10 Link Success Mode RO, LH 1 = Link down happened.
Interrupt 0 = Link down not happened.
HW 0
Rst
SW Retain
Rst
9 RES Mode RO, LH Reserved
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
6 MDI Crossover Mode RO, LH 1 = Crossover changed
Changed 0 = Crossover not changed
HW 0
Rst
SW Retain
Rst

5 Wirespeed- Mode RO, LH 1 = Wirespeed-downgrade detected.
downgrade 0 = No Wirespeed-downgrade.
Interrupt HW 0
Rst
SW Retain
Rst
HW 000
Rst
SW 000
Rst
1 Polarity Changed Mode RO, LH 1 = Polarity Changed
HW 0 0 = Polarity not changed
Rst
SW Retain
Rst
0 Jabber Mode RO, LH 1 = Jabber
HW 0 0 = No jabber
Rst
SW Retain
Rst
4.1.12 Smart Speed Register

Offset: 0x14

15:11 RES Mode RO Reserved. Must be 00000000.
HW 0
Rst
SW 0
Rst
10:9 Reserved Mode R/W Reserved
HW 1’b0
Rst
SW Retain
Rst
HW 1’b0
Rst
SW Update
Rst

HW 0
Rst
SW Update
Rst
5 Smartspeed_en Mode R/W The default value is one; if this bit is set to one and cable inhibits
completion of the training phase, then
HW 0
Rst After a few failed attempts, the Atheros card automatically
downgrades the highest ability to the next lower speed: from 100
SW Update to 10.
Rst
4:2 Smartspeed_retry_ Mode R/W The default value is three; if these bits are set to three, then the
limit Atheros card will attempt five times before downgrading; The
HW 0 number of attempts can be changed through setting these bits.
Rst
SW Update
Rst
1 Bypass_smartspeed Mode R/W The default value is zero; if this bit is set to one, the Smartspeed
_timer FSM will bypass the timer used for stability.
HW 0
Rst
SW Update
Rst
0 RES Mode R/W Reserved.
HW 0
Rst
SW 0
Rst

4.1.13 Receive Error Count Register
Offset: 0x15

15:0 Receive Error Mode RO Counter will peg at 0xFFFF and will not roll over.
Count (when rx_dv is valid, count rx_er numbers)
HW 0
Rst (in this version, only for 100Base-T)
SW 0
Rst
4.1.14 Virtual Cable Tester Control Register

Offset: 0x16

15:11 Vct_dbg_psw Mode RO For VCT debug
HW 0
Rst
SW 0
Rst
10 vct_wp_ Mode RO For VCT debug
Max_vcode[3] HW 1’b1
Rst
SW Retain
Rst
9:8 MDI Pair Select Mode R/W Virtual Cable Tester™ Control registers. Use the Virtual Cable
Tester Control Registers to select which MDI pair is shown in the
HW 00 Virtual Cable Tester Status register.
Rst
00 = MDI[0] pair
SW 00 01 = MDI[1] pair
Rst 10 = Reserved
11 = Reserved
7:5 vct_wp_ Mode RO For VCT debug
Max_vcode[2:0] HW 3’b111
Rst
SW Retain
Rst
4:1 vct_np_ Mode R/W For VCT debug
Max_vcode[3:0] HW 3’b111
Rst
SW Retain
Rst

0 Enable Test Mode R/W When set, hardware automatically disable this bit when VCT is
done.
HW 0
Rst 1 = Enable VCT Test
0 = Disable VCT Test
SW Retain
Rst
4.1.15 LED Control Register

Offset: 0x18

15 Disable LED Mode R/W Control the output LED pins.
HW 0 0 = Enable
Rst 1 = Disable
SW Retain
Rst
14:12 LED On Time Mode R/W 000 = 5 ms
HW 0 001 = 10ms
Rst 010 = 21 ms
011 = 42ms
SW Retain
Rst 100 = 84 ms
101 = 168ms
110 to 111 = 42ms
11 Force Interrupt Mode RO Always 0
HW 0
Rst
SW 0
Rst
10:8 LED Off Time Mode R/W 000 = 21 ms
HW 0 001 = 42 ms
Rst 010 = 84 ms
011 =168 ms
SW 0
Rst 100 =330 ms
101 = 670 ms
110 to 111 = 168ms
HW 000
Rst
SW 000
Rst
4:3 LED_LINK Control Mode R/W 00 = Direct LED mode
HW 0 11 = Master/Slave LED mode
Rst 01, 10 = Combined LED modes
SW Retain
Rst

2 LED_DUPLEX Mode R/W 0 = Duplex
Control 1 = Duplex/Collision
HW 0
Rst
SW Retain
Rst
1 LED_RX Control Mode R/W 1 = Receive activity/Link
HW 0 0 = Receive activity
Rst
SW Retain
Rst
0 LED_TX Control Mode R/W 1 = Activity/Link
HW 0 0 = Transmit activity
Rst
SW Retain
Rst
4.1.16 Manual LED Override Register

Offset: 0x19

HW 0
Rst
SW 0
Rst
11:10 LED_DUPLEX Mode R/W LED "Off" means LED pin output equals high.
HW 00 LED "On" means LED pin output equals low.
Rst 00 = Normal
01 = Blink
SW Retain
Rst 10 = LED Off
11 = LED On
9:8 LED_LINK10 Mode RO LED "Off" means LED pin output equals high.
Rst 00 = Normal
01 = Blink
SW Retain
Rst 10 = LED Off
11 = LED On
7:6 LED_LINK100 Mode R/W LED "Off" means LED pin output equals high.
Rst 00 = Normal
01 = Blink
SW Retain
Rst 10 = LED Off
11 = LED On

HW 0
Rst
SW Retain
Rst
3:2 LED_RX Mode R/W LED "Off" means LED pin output equals high.
Rst 00 = Normal
01 = Blink
SW Retain
Rst 10 = LED Off
11 = LED On
1:0 LED_TX Mode R/W LED "Off" means LED pin output equals high.
Rst 00 = Normal
01 = Blink
SW Retain
Rst 10 = LED Off
11 = LED On
4.1.17 Virtual Cable Tester Status Register

Offset: 0x1C

HW 0
Rst
SW 0
Rst
9:8 Status Mode RO The content of the Virtual Cable Tester Status Registers applies to
the cable
HW 00
Rst pair selected in the Virtual Cable Tester™ Control Registers.
11 = Link-up state, no short or open in cable
SW 00 00 = Valid test, normal cable (no short or open in cable)
Rst
10 = Valid test, open in cable (Impedance > 333 ohms)
01 = Valid test, short in cable (Impedance < 33 ohms)
7:0 Delta_Time Mode R/W Delta time indicates distance along the cable
HW 0
Rst
SW 0
Rst
4.1.18 Debug Port (Address Offset Set) Register

Offset: 0x1D

HW 0
Rst
SW 0
Rst
5:0 Addres Offset Mode R/W The address index of the register will be written or read.
HW 0
Rst
SW 0
Rst
4.1.19 Debug Port 2 (R/W Port) Register

Offset: 0x1E

15:0 Debug Data Port Mode R/W The data port for the debug register.
HW 0 Before accessing this register, you must set the address offset
Rst first.
SW 0
Rst

4.2 Power Saving and Debug Register Summary
Table 4-2 summarizes the registers for the
AR8032.
Table 4-3. Register Summary
0x12 Test Configuration for 10Base-T page 45
0x10 Test Configuration for 100Base-Tx page 46
0x1B Hibernate Control page 48
0x29 Power Saving Control page 49
4.2.20 10Base-T Test Configuration Register

Offset: 0x12

15:14 Interval_sel_timer Mode R/W Controls the interval that PHY detects whether the data frames
on the cable are MLT-3 coded. This logic is used to divide
HW 0 Manchester code from MLT-3 code.
Rst
SW Retain
Rst
13:12 Triger_sel_timer Mode R/W Controls the threshold that PHY detects at the end of the interval
whether the data frames on the cable are MLT-3 coded. This logic
HW 00 is used to divide Manchester code from MLT-3 code.
Rst
SW Retain
Rst
11 En_mask_bt Mode R/W 1: enable the function of dividing Manchester code from MLT-3
code.
HW 1
Rst 0: disable the function.
SW 0
Rst
10 En_10bt_idle Mode R/W 1: In 10BT mode , if there's no data or NLP to transmit, shut off
dac; otherwise turn on the dac;
HW 0
Rst 0: In 10BT, dac will not be turn off.
SW 0
Rst
HW 0
Rst
SW 0
Rst
5 Test_mode[2] Mode R/W bit 2 of test_mode
HW 0
Rst
SW 0
Rst

4 En_longcable Mode R/W Enable long cable test
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW Retain
Rst
2 Loopback mode Mode RO 1: lpbk2-deep in Loopback mode
select 0: lpbk1-shallow in Loopback mode
HW 0
Rst (connect to dig10.test_mode_i[0])
SW 0
Rst
1:0 Test_mode[1:0] Mode R/W [001]: packet with all ones, 10MHz sine wave, For harmonic test.
HW 0 [010]: pseudo random, for TP_IDLE/Jitter/Differential Voltage
Rst test.
[011]: normal link pulse only,
SW 0 [100]: 5MHz sin wave.
Rst
Others: normal mode.
4.2.21 100Base-TX Test Configuration Register

Offset: 0x10

15 TM100_ENA Mode R/W Enable dig100 loopback test mode.
HW 0
Rst
SW Retain
Rst
HW 0
Rst
SW Retain
Rst
7 Jitter_test Mode R/W 100Base-Tx Jitter test
HW 0
Rst
SW Retain
Rst

6 Os_test Mode R/W 100Base-Tx Overshoot test
HW 0
Rst
SW Retain
Rst
5 Dcd_test Mode R/W 100Base-Tx DCD test
HW 0
Rst
SW Retain
Rst
4 PMD_LPBK_2 Mode R/W PMD loopback, test MLT-3 Encoder and Decoder
HW 0
Rst
SW 0
Rst
3 PMD_LPBK_1 Mode R/W PMD loopback, test Scrambler and Descrambler
HW 0
Rst
SW 0
Rst
2 PMA_LPBK_1 Mode R/W PMD loopback, test Carrier Detect and Link Monitor
HW 0
Rst
SW 0
Rst
1 PMA_LPBK_2 Mode R/W PMA loopback, test FEF Generator and FEF Detector
HW 0
Rst
SW 0
Rst
0 PCS_LPBK Mode R/W PCS loopback, test pcs_tx and pcs_rx
HW 0
Rst
SW 0
Rst

4.2.22 Hibernate Control Register
Offset: 0x1B

15 Ps_hib_en Mode RO Power hibernate conrol bit;
HW 0
Rst ‘1’ : hibernate enable
‘0’ : hibernate disable
SW 0
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst
HW 0
Rst
SW 0
Rst

4.2.23 Power Saving Control
Offset: 0x29

15 TOP_PS_EN Mode RO ‘1’ : Top level Power Saving Enable
HW 1 ‘0’ : Top level Power Saving Disable
Rst
SW Retain
Rst
HW 3’h3
Rst
SW Retain
Rst
11:9 Dac_amp_100 Mode R/W Control amplitude of transmit signal in 100BT mode.
HW 3’h3
Rst 000: -2%
SW Retain
Rst ……
111: +12%
8:6 Dac_amp_10 Mode R/W Control amplitude of transmit signal in 10BT mode.
HW 3’h3
Rst 000: -2%
SW Retain
Rst ……
111: +12%
HW 0
Rst
SW 0
Rst
HW 1
Rst
SW Retain
Rst

5. Package Dimensions
The AR8032 is packaged in a QFN 32. The body and dimensions are provided in Figure 5-1 and
size is 5 mm by 5 mm. The package drawings Table 5-1.
Figure 5-1. Package Views

Table 5-1. Package Dimensions
Dimension Label Min Nom Max Unit

A 0.80 0.85 0.90 mm
A1 0.00 0.01 0.05 mm
A2 0.60 0.65 0.70 mm
b 0.18 0.23 0.30 mm
D 5.00 Basic mm
D1 4.75 Basic mm
E 5.00 Basic mm
E1 4.75 Basic mm
P 0.24 0.42 0.60 mm
R 0.13 0.17 0.23 mm
Q 0.30 0.40 0.65 mm
D2 2.60 2.70 2.80 mm
E2 2.60 2.70 2.80 mm
θ 0 — 12 °
Notes:
1. To be determined at seating plane C.
2. Dimensioning and tolerences conform to ASME Y14.5M — 1994.
3. Dimension b applies to plated terminal and is measured between
0.15 and 0.30mm from terminal tip.
4. The Pin #1 identifier must be on the top surface of the package us-
ing indentation mark or other feature of the package body.
5. All Dimensions are in millimeters.
6. The shape shown on four corners are not actual I/O.
7. Q and R applies only for straght tiebar shapes.

PRELIMINARY
6. Ordering Information
The order number AR8032-AL1E specifies a
current version of the AR8032.
Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet

Transceiver • 53
The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to
change without notice. Atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no
commitment to update or to keep current the contained information, or to notify a person or organization of any updates. Atheros reserves
the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product possible.
Document Number: 981-00072-001 MKG-0607 Rev. 1
Atheros Communications, Incorporated

5480 Great America Parkway
Santa Clara, CA 95054
t: 408/773-5200
f: 408/773-9940
www.atheros.com

Atheros Ar8032 PDF

Uploaded by

Document Informationclick to expand document information

Document Informationclick to expand document information

Copyright:

Available Formats

Atheros Ar8032 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Atheros Ar8032 PDF

Uploaded by

Copyright:

Available Formats

Data Sheet

AR8032 Integrated 10/100 Fast Ethernet Transceiver

Automatic speed downshift mode

AR8032 Functional Block Diagram

Timing & Phase

Auto- MII Management

2 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

3.7 Typical Power Consumption Parame-

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 3

4 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

P Power OA Analog output

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 5

Figure 1-1. Pinout Diagram

6 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

Symbol Pin Type Description

MII/RMII Receive data output [0].

2.5V I/O power, connect with pin 3, 0.1uF to GND.

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 7

Symbol Pin Type Description

NOTE: All of the digital input only pads are 3.3V

8 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

Line Driver TXDAC

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 9

10 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

2.3.5 Power Supplies

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 11

Table 3-1. Absolute Maximum Ratings

Symbol Parameter Max Rating Unit

3.2 Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

ΤJ Junction Temperature 0 — 125 °C

ΨJT Thermal Dissipation Coefficient — 4 — °C/W

NOTE: The following condition must be satisfied:

ΤJmax = Maximum allowable temperature of the Junction

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 13

Figure 3-1. XTAL/OSC Timing Diagram

Table 3-3. XTAL/OSC Timing — MII mode

Symbol Parameter Min Typ Max Unit

Table 3-4. XTAL/OSC Timing — RMII mode

Symbol Parameter Min Typ Max Unit

14 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

3.4 MII DC Characteristics

Figure 3-2 shows the MII input AC timing

Figure 3-2. MII Input AC Timing Diagram

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 15

Figure 3-3. MII Output AC Timing Diagram

3.5 MDIO Characteristics

3.5.8 MDIO Timing

Figure 3-4. MDIO Timing Diagram

16 • AR8032 Integrated 10/100 Mbps Ethernet Transceiver Atheros Communications, Inc.

Symbol Parameter Min Typ Max Unit

Table 3-8 shows the RMII AC timing

Figure 3-5 shows the AC RMII timing diagram.

Figure 3-5. RMII AC Timing Diagram

Atheros Communications, Inc. AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 17

Table 3-9. Power-On Strapping[1]

3.7 Typical Power Consumption Parameters