A VLSI Implementation of a New Simultaneous

Images Compression and Encryption Method

Maher Jridi, Member, IEEE, and Ayman AlFalou, Senior, IEEE
Département d’optoélectronique, Laboratoire L@bISEN
20 rue cuirassé Bretagne CS 42807, 29228 Brest Cedex 2, France
e-mail: ([email protected] and [email protected])

Abstract—In this manuscript, we describe a fully pipelined to exploit signal proprieties to improve the tradeoff between
single chip architecture for implementing a new simultaneous computation time and hardware requirement. Among these,
image compression and encryption method suitable for real-time the DCT algorithm proposed by Loeffler [5], has opened a
applications. The proposed method exploits the DCT properties to
achieve the compression and the encryption simultaneously. First, new area in digital signal processing by reducing the number
to realize the compression, 8-point DCT applied to several images of required multiplications to the theoretical limit. In this
are done. Second, contrary to traditional compression algorithms, paper we use the DCT architecture for image compression and
only some special points of DCT outputs are multiplexed. For we demonstrate that the number of arithmetic operators can
the encryption process, a random number is generated and be reduced without dramatically decreasing the compressed
added to some specific DCT coefficients. On the other hand,
to enhance the material implementation of the proposed method, image quality. In fact, by exploiting the spacial correlation
a special attention is given to the DCT algorithm. In fact, a of input images, we can reduce the number of arithmetic
new way to realize the compression based on DCT algorithm operators from 11 multipliers and 29 adders to 4 multipliers
and to reduce, at the same time, the material requirements of and 14 adders. Simultaneously, in order to perform the security
the compression process is presented. Simulation results show a level, a second stage a using random number generator is
compression ratio higher than 65% and a PSNR about 28 dB.
The proposed architecture can be implemented in FPGA to yield applied to some specific DCT outputs.
a throughput of 206 MS/s which allows the processing of more This paper is organized as follows: the description of the
than 30 frames per second for 1024x1024 images. proposed simultaneous compression and encryption method is
presented in section II. Section III is dedicated to the optimiza-
I. I NTRODUCTION tion of the DCT architecture. Implementation results using
Reconfigurable hardware in the form of Field Programmable FPGA are illustrated in the last section before conclusion.
Gate Arrays (FPGAs) have been proposed to obtain high
performance and economical price to implement image pro- II. M ETHOD PRINCIPLE
cessing applications like face recognition, detector or airport We proposed a new technique, based on our methods
security [1]. For these applications, we need to use com- presented in [3] and [6], which can carry out compression
munication systems with a good security level (encryption) and simultaneous encryption using random number generator
and an acceptable transmission rate (compression rate). In the and Discrete Cosine Transform (DCT). The main idea of
literature, several encryption and compression techniques can our approach consists in multiplexing the spectra of different
be found. However, for some applications such as detectors, transformed images separately by a DCT.
the encryption and the compression techniques cannot be The choice of the DCT is justified by the use of the DCT
deployed independently and in a cascade manner without in many standards such as JPEG [7], MPEG [8] and ITU-T
considering the impact of one technique over another [2]. H261 [9]. Moreover, we need fewer DCT coefficients than
To solve this problem, we developed a new technique to DFT coefficients to get a good approximation to a typical
simultaneously compress and encrypt multiple images [3]. signal [10]. In fact, by applying the DCT, the most of the signal
The main idea of our approach consists, firstly, in multiplexing information tends to be concentrated in a few low-frequency
the spectra of different transformed images (to be compressed components. Consequently, the higher frequency coefficients
and encrypted) by a Discrete Cosine Transform (DCT) and are small in magnitude and can be ignored in the compression
secondly in implementing the proposed system in FPGA. and encryption process.
Consequently, special attention is given to the DCT algo- Fig. 1 presents the synoptic diagram of the proposed com-
rithm implementation in the context of image compression. pression and encryption system. In the left side, 4 input gray
In fact, the DCT is the heart of the proposed compression level images are presented (P 1, P 2, P 3, P 4). To apply to
and encryption method. It has been widely used in speech each of these images a full parallel DCT algorithm, we need
and image compression due to its good energy compaction to parallelize each image by blocks of 8 pixels. This operation
[4]. However its computational requirement is a heavy burden can be done by a serial to parallel block composed by 8 flip-
in the real time simultaneous compression and encryption flops.
application. Different DCT architectures have been proposed Then, 4 DCT blocks are used to transform the 4 input

978-1-4244-6494-4/10/$26.00 ©2010 IEEE

 Fig. 1. Synoptic diagram of the proposed compression and encryption system

III. DCT ARCHITECTURE

The DCT is the heart of the proposed compression and
encryption method. Therefore, an optimization of the whole
proposed method requires a DCT optimization. In this sec-
tion, we present the modified DCT architecture and the data
encoding of DCT outputs in order to allow an acceptable
compression ratio and a relatively high image quality.
Fig. 2. Histogram of DCT outputs A. Related Work
The N-point DCT of N input samples x(0),...,x(N − 1) is
defined as:
images. These DCTs are employed to regroup lower frequency r N −1
2 X (2k + 1) nπ
components of the DCT. In fact, by taking into account only X (n) = C (n) x (k) cos (1)
the first and the second DCT outputs among 8, we get a good N 2N
k=0
approximation of input pixels. Hereafter, we use the following √
notations: DCT out1 for the first DCT output and DCT out2 where C (0) = 1/ 2 and C (n) = 1 if n 6= 0.
for the second one. In literature, many fast DCT algorithms are reported. In [11],
Concerning the encryption process, the algorithm is based on the authors show that the theoretical lower limit of 8-point
the next observation: the multiplexed spectrum plane presents DCT algorithm is 11 multiplications. Since the number of
alternatively one high value DCT out1 followed by one low multiplications of Loeffler’s algorithm [5] reaches the theo-
value DCT out2. In terms of security, we can imagine that retical limit, we use this algorithm as the reference to this
behind the histogram on the left of Fig. 2 we can find DCT work. A modified signal flow graph of 8 inputs 2 outputs
coefficients. In fact, as it will be explained in the next section, DCT is presented in Fig. 3. We will explain the reasons of
the low value of the DCT out2 is due to the spatial correlation modifications in the next section.
between 8 successive pixels presented in input images. In [12] one realization based on Loeffler algorithm is shown.
In order to ensure a good encryption level against any hacking A low power design is obtained with this algorithm.
attempt, we propose to add to DCT out2 a positive random In [13] use the recursive DCT algorithm and their design
value to have a data values close to DCT out1. As mentioned requires less area than conventional algorithms. The authors
in Fig. 2, the addition of a random number can drastically of [13] use Distributed Arithmetic (DA) multipliers and show
modify the characteristic spectral distribution of the DCT that N-point DCT can be obtained by computing N N/2-point
The security key will be sent separately as a private encryption inner products instead of computing N N-point inner products.
key. Once secure and compressed information safely reach the In [14], a new DA architecture called NEDA is proposed,
authorized receiver, the image extraction can be easily done aimed at reducing the cost metrics of power and area while
by reversing the various steps used in the whole process: maintaining high speed and accuracy in digital signal pro-
cessing (DSP) applications. Mathematical analysis proves that
• Subtract the received image by the security key; DA can implement inner product of vectors in the form of
• Add 6 zeros to each block (zeros padding); two’s complement numbers using only additions, followed by
• Run an Inverse DCT (IDCT). a small number of shifts at the final stage. Comparative studies
show that NEDA outperforms widely used approaches such as
 Fig. 3. Signal flow graph of 8 inputs 2 outputs DCT

multiply/accumulate (MAC) and DA in many aspects. + (−E18 ∗ sin (π/16) + E16 ∗ cos (π/16))
In this paper, we will not optimize the arithmetic operators but + (E16 ∗ cos (3π/16) + E14 ∗ sin (3π/16))(2)
we present a new algorithm based on Loeffler one and makes
dependency between the compression ratio and the material After factorizations, DCT out2 can be written as follows:
complexity. Consequently, optimizations in [12], [13] or [14] c1
can be used with the presented new algorithm. z }| {
DCT out2 = E18 ∗ (cos (π/16) − sin (π/16))
B. Proposed DCT architecture c2
z }| {
The circuit of the proposed algorithm of the DCT is + E16 ∗ (cos (3π/16) − sin (3π/16))
inspired from the Loeffler one. Therefore, some similarities c3
exist between these two circuits. For example, we propose to z }| {
+ E14 ∗ (cos (3π/16) + sin (3π/16))
compute DCT outputs on four stages as shown in Fig. 3. Each c4
stage contains some arithmetic operations. The first stage is z }| {
performed by 4 AddSub (adder and subtracter) blocks while + E12 ∗ (cos (π/16) + sin (π/16)) (3)
the second one is composed of 2 AddSub and 2 MultAddSub
According to these equations, the MultAddSub blocks of Fig.
(Multiplier, Adder and Subtracter) blocks. The details of these
3 can be replaced by more simple blocks. In fact, the original
blocks are shown in Fig. 4.
block requires 1 adder, 1 subtracter and 4 multipliers to
Moreover, some important differences should be mentioned.
compute the outputs. Loeffler reduces the number of arithmetic
Since the proposed DCT circuit accepts 8 pixels per clock
operators to 3 multipliers and 3 adders per block. In this work,
cycle and delivers 2 outputs against 8 outputs in the original
as presented in Fig. 4 the MultAddSub block can be replaced
Loeffler algorithm, we decide to change the DCT architecture
by only two multipliers. Like this, we economize 6 adders and
to compute only necessary DCT coefficients DCT out1 and
2 multipliers.
DCT out2.
Using these three optimization levels, the proposed DCT
It should be outlined that traditionally, one possible manner for
architecture requires 4 multipliers and 14 adders to compute
compression based on DCT algorithm consists in computing
relevant and representative data outputs for image compression
all DCT outputs (8 outputs for 8 pixels) and after that some
against 11 multipliers and 29 adders proposed by Loeffler.
special points are selected. The whole computation time and
latency are therefore very high.
C. Data encoding
The changes in DCT architecture are as follows:
First, only necessary paths to compute DCT out1 and The minimization of data length implies less computation,
DCT out2 are kept as shown in the Fig. 3. Thus, we can and consequently, lower power consumption and higher speed.
economize 5 multipliers, 2 adders and 2 subtracter compared On the other hand, truncating introduces errors at the outputs
to the Loeffler architecture. and degrades the PSNR (Peak Signal to Noise Ratio). Thus a
Then, we can notice that in Fig. 3 only the first outputs of trade-off between power and PSNR is made. In the input side
AddSub5 to AddSub10 are used. Therefore, the AddSub5 to of the proposed method, the pixels of input images are encoded
AddSub10 blocks are reduced to 1 adder per block. Conse- using unsigned 8-bit values. In the output side, DCT out1
quently, 6 additional subtracters can be saved. contains the major part of the information, so this value
Finally, the DCT out2 can be written as follows: must be encoded by the maximum number of bits. DCT out1
results in 3 successive additions of input pixels. Consequently,
DCT out2 = (E25 + E28) + (E26 + E27)
and considering the carry of each addition, the DCT out1 is
= (E18 ∗ cos (π/16) + E12 ∗ sin (π/16)) encoded by using 11 bits.
+ (−E16 ∗ sin (3π/16) + E14 ∗ cos (3π/16)) For the constant ci , i ∈ [1, 4] of (3] we can employ the
 Fig. 4. Arithmetic operator blocks

Fig. 5. Input images

coefficients encoding used in [15] and detailed by the next
equation:
IV. VALIDATION
cei = round ci ∗ 28−1 − 1/ci,max


(4)
A. Methodology
For DCT out2 encodage, we can take into account the spatial A fixed point Matlab Simulink model has been estab-
correlation of images. In fact, we can suppose that for image lished to validate the proposed method. This step is very
size of 256*256 pixels or higher, the block of each 8 adjacent important to validate the the algorithm structure before the
pixels of the same line are very correlated and have a very material implementation. Concerning the description language,
close value. Consequently, signals E12, E14, E16 and E18 we decide to use VHDL rather than DIME-C and Mitrion-C
from Fig. 3 which are the subtraction of input image pixels which produce less efficient hardware design. In fact, DIME-
from In1 to In8 have a very low value. In the same way, the C and Mitrion-C are much easier to program than VHDL, but
signals E25 to E28 also have a lower value compared to input visibility to hardware details allowing optimizations is lost due
pixel images. Consequently, we can limit the DCT out2 by to abstraction [16]. In addition, the VHDL standard language
−F S ≤ DCT out2 ≤ F S where F S = 28 is the full scale of gives the choice of implementing target devices (FPGA family,
the input images. CPLD, ASIC) at the end of the implementation flow. It means
On the other hand, for encryption process, the encrypted that the models reported here are synthesized and may be
DCT3 out2 have to be close to DCT out1 which is in implemented on arbitrary technologies [17].
0, 2 ∗ F S . Consequently, the DCT out2 is added to r̃, a Simulation results of the VHDL model are reported in Fig. 5
generated random number expressed by the next equation: and Fig. 6 and show that original images are rebuilt correctly
with a PSNR average between four images about 28 dB.
r̃ = round (F S + 6 ∗ F S ∗ r) (5)
B. FPGA implementation
where r is an uniformly distributed pseudorandom number, The original DCT Loeffler architecture and the proposed
0 ≤ r ≤ 1. Finally, DCT out1, DCT out2 are encoded using one in this article have been implemented in the same kind
11 bits. of FPGA boards, that is, Virtex 5 of xc5vlx330t. In order to
The data encoding allows a high compression ratio. In fact, illustrate the differences in hardware consumption, the FPGA
since the 4 spectra will be regrouped in a single plane, the implementation results are presented in Table 1. From this
consequent compression ratio for input image sizes of S is: comparison we can notice that the proposed DCT architecture
  reduces the area consumption (slices and Look Up Tables,
S ∗ 11bits LUTs) at a rate higher than 50 %.
R= 1− × 100% = 65.62% (6)
4 ∗ S ∗ 8bits Furthermore, the throughput, expressed in Millions of Samples
per second (MS/s), presents a light increase compared to the
Moreover, for higher compression rate, we can use the Loeffler architecture. The throughput of 206 MS/s allows the
correlation between the neighboring pixels to encode the processing of more than 30 frames per second. Finally, it
second DCT coefficient using only 7 bits. The obtained should be pointed out that the modified DCT and the proposed
compression ratio can achieve a value of about 72% compression and encryption method have the same throughput:
the proposed method is for sure fully pipelined.
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V. C ONCLUSION
In this manuscript, a new method of simultaneous com-
pression and encryption based on a DCT transformation is
presented. An optimized DCT algorithm is proposed to reduce
real time application requirements. This algorithm needs only
4 multiplications to compute relevant DCT output data. The
FPGA implementation of the whole method shows improve-
ments in terms of throughput, area and power consumption.
To prove the good performances, the proposed algorithm is
compared favorably with several existing methods.

ACKNOWLEDGMENT
The author thanks Dominique Maratray for her help and
advice.

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