Department of Electrical Engineering

Faculty Member: ____________________ Dated: ________________

Semester:__________________________ Section: ________________

Group No.:

EE-221: Digital Logic Design

Lab 5: Binary to Gray and Gray to Binary Code Conversion

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

EE-221: Digital Logic Design Page 1

Lab4: Part (a): Binary to Gray and Gray to Binary Code Conversion

Lab4: Part (b): Gate-level Modeling in Verilog

This Lab has been divided into two parts:

In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).

The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.

Objectives:

 Understand steps involved in design of combinational circuits

 Understand binary codes for decimals and their hardware realization
 Write code for combinational circuits using Verilog Gate Level Modeling
 Design a circuit in Verilog by calling different modules

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
 The students will complete lab task and submit complete report to Lab Engineer before leaving
lab.
 The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day
will be done for late submission.
 A lab with in-complete lab tasks will not be accepted.
 There are related questions at the end of this activity. Give complete answers.

EE-221: Digital Logic Design Page 2

Pre-Lab Tasks: (To be done before coming to the lab) ( 5 marks- Individual and Team
Work)

1. What do you mean by binary codes for the decimal digits? Give some examples and codes (tables) for
the decimal digits.

2. What is a self-complementing code? Name any two of them; show their complementing nature with
examples and describe advantages.

3. In the lab you would be implementing a gray to binary and binary to gray code converter. Make a truth
table for both the codes by filling in the following tables and Simplify the expressions for W,X,Y,Z in
terms of A,B,C,D and vice versa.( Use backside of the page if necessary). Also give some applications
in which gray code could be used.

EE-221: Digital Logic Design Page 3

HINT: Dec Binary Gray
A B C D W X Y Z
Our inputs and outputs are of 4-bit each.
You will have to make 4 K-Maps (Consider
W as independent function of A,B,C,D,
Make K-Map and simplify it). Arrive at the
simplest expression for each output. W=

X=

Y=

Z=

EE-221: Digital Logic Design Page 4

 Dec Gray Binary HINT:
W X Y Z A B C D
Our inputs and outputs are of 4-bit each.
You will have to make 4 K-Maps (Consider
A as independent function of W,X,Y,Z.
Make K-Map and simplify it). Arrive at the
simplest expression for each output.

A=

B=

C=

D=

EE-221: Digital Logic Design Page 5

 4. Draw the logic diagram for the Binary-to-Gray and Gray-to-Binary code converters using Exclusive-OR
gates in the space provided below.

Binary Gray Binary

A
W A

B
X B

C
Y C

D
Z D

Only the following gates are available to you for lab tasks.

EE-221: Digital Logic Design Page 6

Lab Tasks: (To be completed in the lab) (10 marks)
Lab Task 1: (3 Marks - Modern Tool Usage)

Implement the Binary to Gray Code Converter using Basic gates (AND, OR, NOT). Make the Schematic
(logical) Diagram. What and how many gates did you use? Do not dispatch your hardware. You will need it
in lab task 3.

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Lab Task 2: (2 Marks - Modern Tool Usage)

Realize the Gray to Binary Code Converter using exclusive-OR gates. Make the Schematic (logical) diagram
using xor gate below. How many xor gates did you use? Do not dispatch your hardware. You will need it in
lab task 3.

EE-221: Digital Logic Design Page 8

Lab Task 3:

Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to the inputs of the
gray-to-binary converter. You should be able to get the binary input at output as well. Show the results to your
Teacher/Lab Engr. Use trainer LEDs to show input-output relationship. (2 Marks - Analysis of data in Lab Report)

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Lab Task4: (3 Marks - Analysis of data in Lab Report)

Design and simulate the gate-level model of the circuit you patched in task 3. Give the code in the space
provided below.

EE-221: Digital Logic Design Page 10