Anti Islanding PV
Anti Islanding PV
Anti Islanding PV
Sreg Kern
Issued by Sandia National Laboratories, operated for the United States
Department of Energy by Sandia Corporation.
Printed in the United States of America. This report has been reproduced directly
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,
DISCLAIMER
Greg Kern
Ascension Technology
Boulder, Colorado
Abstract
4
Table of Contents
1. Introduction .............................................................................................................. 7
2. Background ............................................................................................................... 8
A Brief Discussion of Line-Commutated Versus Self-Commutated
Invetiers ..................................................................................................................... 9
5
Test Results . ............................................................................................................. 37
Motor Load Testing at Smdia ............................................................................. 37
10. Implementing SVS & SFS Islanding Protection in a Static Utility Interactive
Inverter ........................................................................................................................5l
Voltage Seining ...................................................................................................... 51
Voltage Trip Points ................................................................................................ 52
Frequency Seining ................................................................................................. 52
Frequency Trip Ltits ........................................................................................... 53
Voltage, Frequency and Current Re~lation ..................................................... 53
Sandia Voltage Shift (SVS) .................................................................................... 54
Ou~ut Current Control ........................................................................................55
Sandia Frequency SWt .......................................................................................... 55
How can Inverter Frequency be Different than Grid Frequency? ..................56
Inverter Frequency Control .................................................................................. 56
Fast Response, It is Critical ! ................................................................................. 57
A V~iable.Power.Factor.InverterConsideration............................................. 58
Digital or AnaIog Implementation? .................................................................... 58
6
1. Introduction
The report presents background, test results that helped direct the formulation of
the final islanding prevention approach, and test results of the final anti-
islanding technique.
One of the significant objectives of this project was to define a test procedure that
can be used to confirm that a satisfactory anti-islanding technique is
incorporated in an inverter. It was necessary to develop a standardized test that a
single inverter with an adequate anti-islanding technique can pass, but which
one that lacks such a technique will fail. This report describes such a test, and
provides a discussion of why the testis adequate.
7
2. Background
A new generation of inverters was available in the mid-1990s. At this same time
an upsurge in interest in utility-interconnected PV systems generated fresh
interest in the topic of islanding. In addition, the developmental work on two
standards required an improved understanding of islanding. These two
standards were an IEEE standard on utility interconnection of PV systems (IEEE
Std. 929-2000) and the Underwriters Laboratories safety standard for
photovoltaic inverters (UL 1741). Because of the renewed interest in islanding
and the need for test data to confirm anti-iskmding capabilities of modern
inverters, Sandia National Laboratories initiated a test program to investigate the
propensity for islanding in today’s inverters. To this end, several inverters from
different manufacturers were subjected to islanding testing at Sandia. One
important finding resulting from these tests was that the various approaches for
preventing islanding utilized by different manufacturers interfered with each
other thus allowing islanding to occur. Another finding was that even single
inverters did not respond fast enough to meet the newly proposed IEEE Std. 929-
2000 requirements. As a result of these findings Sandia undertook an anti-
islanding development program in cooperaticm with U.S. PV inverter
manufacturers.
1Public Service Electric and Gas Co. (New Jersey), Georgia Power Co., Salt River
Project (Arizona), and Southern California Edlison Co
8
was perceived by these manufacturers as a problem where cooperation among
manufacturers was more productive than development of proprietary techniques
(that is, techniques that could possibly interfere with each other) consensus was
reached that a common technique was in the interest of aIl inverter
manufacturers. An approach was then proposed for developing such a
technique. This approach will be discussed further in this report.
Islanding prevention techniques other than that described in this document are
certainly possible. However, any islanding prevention technique should be
capable of passing the non-islanding inverter test described herein. Additionally
no anti-islanding technique should be allowed to interfere with the techniques
described in this document.
BUT, there is a second converter in many designs that controls the shape of the
output current waveform, that is, the shape of the half sine waves that the
● unwrapper operates on. This converter is truly “self-commutated.” The
switching frequency is independent of the utility frequency. This converter is
used to control the shape of the output current to be a 1/2 sine wave. This
second converter is a dc/ dc converter that functions before the line-commutated
dc/ac inverter bridge unwrapper. The self-commutated operation of this second
converter is what allows designers to achieve low harmonic distortion, typically
9
< 2% THD, which would never be achieved with a purely line-commutated
design. Also, the self-commutated portion of the inverter allows the controls to
be more sophisticated than a pure line-commutated design, as will be seen in the
body of this report.
10
3. Islanding - Why the Concern?
Exactly what are we referring to when we use the term islanding? Islanding is a
condition in which a portion of the utility system, which contains both load and
operating generation, remains energized while isolated from the remainder of
the utility system. If the generation is under the controI of the utiIity, then it is
not a concern in the context that this report addresses. If, however, the
generating source(s) supplying the loads within the island is not within the direct
control of the power system operator, then there is a concern for reasons that are
discussed below. PV generation normally fits this latter condition. Although it is
conceivable that PV generation couId be controlled by the utility, that is not the
normal case and is certainly not true with small dispersed systems such as those
found on residential rooftops. Islanding of these small dispersed systems is the
topic addressed by the work described in this report.
There has been some discussion that islanding under certain circumstances may
be desirable. For example, if a utility experiences a disturbance that results in
inadequate generation being available, it maybe desirable to have all non-utility
generation remain online to assist the utility in recovering from the disturbance.
However, in today’s world the penetration of utiity-interconnected PV
generation is not high enough to support entire sections of utility systems, so this
issue is ignored for now, but maybe revisited at a later time. Therefore, for the
reasons discussed below, islanding of PV systems is to be avoided.
11
● The utility cannot control voItage and frequency in the island. Voltage or
frequency excursions can cause damage to customer equipment. Utilities are
concerned that they might be found liable for electrical damage to customer
equipment connected to their lines which is the result of voltage or frequency
excursions outside of the acceptable ranges.
● Islanding may interfere with the restoration of normal service by the utility.
● Reclosing into an island may result in re-tripping the line or damaging the
dispersed generation equipment, or other connected equipment, because of
out-of-phase closure. (See “Reclosing,” which follows.)
12
Single-phase to
Ill /
ground fault
,?
7 Phase A
Q—
Phase B
PV Inverter
Substation
Reclosing
The vast majority (over 90%, by utility industry estimates) of utiIity outages in
areas with overhead lines are caused by something that is transient in nature,
such as a branch being blown into the lines, or a flash-over caused by a lightning
surge. A technique that most utilities use to limit the outage time associated with
these transient faults is known as “reclosing.” This involves opening of the fault-
interrupting device (circuit breaker or recloser), and then rapidly reclosing it.
The time that the device is opened often allows the fault to clear, and then the
reclosing operation restores normal service. If the first reclosing operation
doesn’t clear the fault, the reclosing procedure is normally repeated 2 or 3 times
with increasingly longer “open” periods. If the fault can’t be cleared by this
succession of reclosing operations, then the interrupting device opens and stays
open, requiring service personnel to visit the site, determine and remedy the
cause of the problem, and then manually reclose the breaker.
.
What has this to do with islanding? If the line is opened, then reclosed, and a PV
inverter remains active during the open period, two things might occur, neither
of which is good.
13
First, the energy output from the inverter could conceivably maintain the fauh
arc so that the reclosing operation will fail and a long outage requiring service
personnel will result. Two things make this possible. The PV system can
energize a phase that it is not connected to by backfeeding various three-phase
devices such as large motors and distribution transformers. Also the energy
necessary to maintain a fault arc is much less than the energy required to initially
establish the fault.
Second, a phase difference may develop between the inverter and utility during
the outage so that, when the line is reclosed, the phase difference is adequate to
damage the inverter. This is not expected to be a problem with reclosing
intervals on the order of less than a second, but longer reclosing intervals are
common for the final reclose attempts before lc~ckout.
14
4. Basic Anti-Islanding Techniques
Most islands can be easily avoided by monitoring ac voltage and frequency at the
inverter output terminals and only allowing inverter operation when these
parameters are within acceptable limits. When an island is created, unbalance
between islanded load and islanded generation will result in either frequency or
voltage (or both) drifting outside of their normal operating range, causing the PV
inverter to disconnect. It is possible, however, that the power requirements of
the load match the instantaneous output of the PV system so closely that voltage
and frequency limits would not be exceeded if the system were islanded. The
existence of this “nondetection zone,” where the load and generation balance is
such that an inverter utilizing only voltage and frequency detection can continue
to operate, is discussed in reference 2. This paper also discusses an interesting
statistical analysis of the probability of having a load-to-generation match such
that operation is in the nondetection zone. The analysis is based on correlation of
simulated PV output with actual measured load data on specific feeders in
various parts of the U.S. The paper indicates that, at certain times of day, with
specific PV penetration levels (there must be connected PV system power ratings
of at least 70% of the line’s average loading), the probability of the load being in
the nondetection zone can be as high as 30%. This non-zero probability suggests
the need for additional controls to detect this potential islanding condition and
remove the PV system from the circuit until the utiIity system is restored to
normal voltage and frequent y.
15
If the intention is to be certain that a downed lie is de-energized in sufficient
time that a lineworker or other person doesn’t come in contact with an energized
line, then an inverter that will disconnect in several seconds is adequate. A much
more demanding requirement is to have the inverter disconnect rapidly enough
that it will be off-line before the first “reclose” is initiated. Since high-speed
reclosing often results in the line being reclosed within 12 to 15 cycles (0.20 to
0.25 seconds for a 60Hz system) of the initial opening, then an anti-islanding
technique that can disconnect the inverter in less than 12 cycles is desirable. The
intent of the work described in this report was to have an anti-islanding
technique that will disconnect in 10 cycles (0.1167 seconds) or less under most
load-to-generation ratio conditions.
It should be noted that any utility condition that results in either frequency or
voltage being out of specification at the inverter terminals is easily detected and
responded to by the basic inverter voltage andl frequency functions. Modern
inverter designs can readily detect and respond to such situations in times
significantly less than 10 cycles. Response in significantly less than 10 cycles is
not desirable because it would result in nuisance tripping.
The only situation that presents some potential for difficulty occurs when the
utility is disconnected and there is no associated perturbation of frequency or
voltage at the inverter terminals. In most such situations, the voltage or
frequency at the inverter terminals will eventually deviate from aIlowable
values, causing the inverter to trip. Generally speaking, if the ratio of the real
power of the islanded load to the real power c)f the PV inverter output is less
than 0.5 or greater than 1.5, or if the islanded load has a power factor of less than
95% leading or lagging, then most inverters will not maintain both voltage and
frequency inside the normal operating windows and the inverter will rapidly
disconnect from the line.
The islanding condition that is most challenging to detect is the condition where
the utility has disconnected, the inverter has seen neither a voltage nor a
frequency disturbance, and the resulting islanded load has a close match to the
PV output, both in terms of real and reactive power. A discussion of this
situation is presented in Section 6, “The Non-lklanding Inverter,” of this report.
16
5.Establishing the Need - Testing of Existing Hardware
utility building/house
(primary) (secondary)
disconnect disconnect
1
utility Inv -- -- -- Inv
1 n
x Cod
distribution
transformer
17
common anti-islanding technique, one that all manufacturers could adopt if they
chose to do so, was in the best interests of the I?V industry. The working group
made recommendations regarding the approach that was to be pursued. Active
methods that perturb the utility and measure a coincident change in voltage or
frequency were rejected by the working group because it was felt that there
would need to be synchronization between units for this type of scheme to work
in high penetrations. Utility members of the P929 working group had expressed
the concern that such synchronized perturbaticms can be undesirable for the
interconnected utility by degrading power quality.
18
6. The Non-Islanding Inverter
An inverter that will cease to energize the utility line in 10 cycles or less
when subjected to a typical islanded load in which either of the following
is true:
1. There is at least a 50% mismatch in real power load to inverter
output (that is, real power load is less than 50% or greater than 150%
of inverter power output) or,
2. The islanded-load power factor is less than 95% (lead or lag),
Note that the above definition includes two cases. Case 1 is for a “typical” island
in which load and generation are not closely matched, and case 2 is for an island
in which load and generation ~ closely matched. In case 1, where load and
generation are not closeIy matched, disconnect is required to be in 10 cycles or
less. For case 2, two seconds are allowed for the inverter to recognize the island
and disconnect. Note that the 10 cycle disconnect for case 1 is the value that was
discussed in the section titled “What is a DesirabIe Response to Islanding
Conditions?” in order to eliminate problems associated with high-speed
reclosing. Although the 2-second disconnect associated with case 2 is longer
than the time required to not interfere with high-speed reclosing, this is not seen
as a problem because of the low probability of occurrence. That is, in order to
qualify for the 2-second disconnect time, both real and reactive power of the load
must match real and reactive output of the PV system.
19
What Is Q and Why Does It Matter?
The IEEE definition for a non-islanding inverter also specifies that the closely
matched load case has a quality factor, or Q of 2.5 or less. (Unfortunately, “Q
can be confusing because it is used for different quantities in electrical
engineering. It is used for the reactive component of compIex power, as in the
equation S = P+jQ, and also as the quality factor of a resonant circuit. The latter
use is what is intended in this discussion.) Q is defined as 27ctimes the ratio of
the maximum stored energy at the resonant frequency to the energy dissipated
per cycle at that frequency. Resonant frequencies near the utility operating
frequency, 60Hz in the US, are the only resonant frequencies of concern in this
discussion. If a circuit is resonant at some freq~uency other than the utility
operating frequency, it will have a tendency tc~move the island frequency
outside of the normal frequency-operating window. This will trip the inverter.
or, noting that for the resonant case where II, the angukzr~req uency is
then
Q = R/~L. (3)
On a power system, where real power, P, and reactive powers, vmL for inductive
load, and varc for capacitive load are measured at 60Hz:
Note that in this report, “var” (often written VAr) is used to designate reactive
power. This is for convenience even though it is technically incorrect, as “var” is
a unit of reactive power. In addition, “var” is used as a n-uzgnitude in this report,
not a signed value. Thus, for the resonance case the notation varc =varL is used,
rather than [capacitive reactive power] = -[ind,uctive reactive power].
20
Also note that equation (4) assumes the load can be modeled as a parallel RLC
load. Reality is much more complicated. Test results and theoretical modeling
[3] have shown that this simple model works well in predicting worst-case
islanding test conditions. Also note that the quantities varc and varI, actually
vary as a function of power system frequency. For example, as frequency
increases, varc increases and varL decreases. At the resonant frequency varc and
varL are equal. When varc and varL are equal, the RLC load appears resistive
with unity power factor. This will be discussed further in a later section.
Q = VW~, (5)
The higher Q is, the stronger the resonance. The reason that Q is important to this
discussion is that strong resonance (high Q) results in a circuit with a strong
tendency to move toward, or remain at, the resonant frequency. Thus the higher
Q the more difficult it is for an anti-islanding technique that uses frequency
shifting to actually shift the frequency, a necessary action for proper response to
an island. Therefore, when defining a non-islanding inverter, the maximum
value chosen for Q is important. Too low of a value for Q is unrealistic and may
result in “passing” an inverter design that will island under real-world
conditions. Too high of a value for Q is also not realistic, and results in an island
for which an anti-islanding technique may not be abIe to respond properly.
Utility engineers agred that Q >2.5 is unlikely on an actual distribution feeder.
21
2. Assume that through good planning, or bad luck, power factor-correction
shunt capacitors are added just adequate tc~correct the total circuit power
factor to unity. This assumption is basic to obtaining the “worst case scenario”
for the anti-islanding protection, since it makes the resonant frequency equal
to the power system frequency. Any other :resonant frequency would tend to
aid, rather than hinder, the anti-islanding protection. (Note that once this
assumption is made, L and C are no longer independent; they have a fixed
relationship of OL = 1/ oC.)
3. With this parallel resonant RLC circuit, Q =’R/oL, as stated in equation (3)
above. Note that, given Assumption 2, one doesn’t need to know C explicitly
in order to calculate Q. It can be calculated simply from R and OL obtained
from step 1.
With the above to establish the thought process, it can be seen that, even though
the line may have shunt capacitors connected to improve power factor, the
following calculation is performed using the power factor of the line as it would
be without the capacitors connected.
where PF is the power factor of the distribution line with no shunt capacitors
connected.
22
connected, the SFS unstable frequency controls are not strong enough to affect
frequency. When the utility is disconnected, the SFS method forces the frequency
to shift outside of the frequency-operating window, causing the inverter to
disconnect. The frequency shift is not in a fixed direction, but can be either up or
down depending on generation and load characteristics.
When an island exists, the SFS unstable frequency controls will cause the inverter
frequency to deviate from 60Hz. If the island frequency starts to move up, the
reference frequency of the inverter moves up at a faster rate. If the island
frequency moves down, the reference frequency of the inverter moves down at a
faster rate. In order to prevent out of phase operation between the inverter
output and the utility during operation in the normal frequency window, the
inverter reference signal is reset at every zero crossing of the voltage waveform, a
characteristic of line-commutated inverters. More detail on the implementation
of SFS will be given later in this report. This method can be implemented
digitally in inverter firmware.
Much discussion surrounded the selection of trip points during the standards-
writing process. For example, allowing the PV system frequency to go as low as
the inverter can tolerate will result in leaving generation on line at a time when
the utility presumably needs generation. However, many utility power pools
have requirements that under-frequency trip points of generators and Ioads must
be coordinated. Thus, the frequency trip points were selected to coordinate with
existing trip points with the thought in mind that these points may be changed as
23
distributed resources increase to the point that they have a larger impact on
utility system operation.
Note that the above operating times have beenl selected to allow ride through of
brief vohage and frequency excursions to nuisance tripping.
mitiLmize
24
7. Testing Considerations
Before beginning a discussion of the test results obtained using the SFS/SVS
techniques, a discussion of the significance of magnetic components and
associated distortion on test results is needed. This discussion will help explain
some of the results that otherwise might not be clear, as well as helping to
understand the final testing technique selection.
utility building/house
(primary) (secondary)
disconnect disconnect
L Inv .- -- -- Inv
utility
1 n
x (-- d G‘ :- ;
distribution
transformer
Investigation led to the conclusion that the reduction in run-on time seen with
the transformer in the test circuit was caused by the distortion in the combined
transformer/capacitor load, which resulted in a harmonic-rich load that the PV
inverters could not support. Figure 4 shows the transformer magnetizing
current, the capacitor charging current and the combined current of the
transformer and capacitor. (Figure 4a shows the values for the specific 50kVA
transformer used in the test. Figure 4b shows similar values for a 15kVA
distribution transformer for comparison.)
25
20
I
15
10
G I
E5
~
Eo
a)
k
z -5
-10
-15
-20
0.000 0.002 0.004 0.006 0.006 0.010 0.012 0.014 0.016 0.018
Time (seconds)
Figure 4a. Distortion and power factor associated with a 50kVA distribution
transformer.
40
5kVA Xfmr Mag Current
30 Vat= 121.1 V
20 xftnronly
ITHDr= 60.1Y.
10 VTHD= 1.8%
pf + 15/0.2
0
.10
-20
%
-30 4S
-40
0.000 0.005 0.010 0.015 0.020
Time (seconds)
Figure 4b. Distortion and power factor associated with a 15kVA distribution
transformer.
Note that Figure 4 also indicates power factor for magnetizing current, capacitor
charging current, and total current. The first power factor value for each current
is total power factor and the second value is displacement power factor. (That is,
the first value is power factor when all frequencies are considered, the second is
power factor of the 60Hz component only.) The capacitors cancel only the 60Hz
component of transformer magnetizing current. The combination of 50kVA
transformer and capacitors results in a load cumrent that has 67% distortion and
73% total power factor, a harmonic-rich load at a power factor that the PV
inverters aren’t designed to supply.
26
Repeatability and predictability of the impact of magnetic circuits on testing is
difficult to achieve because of the non-linearity of the saturation curve (B-H
curve) of magnetic circuits. Excitation voltage affects distortion of a particular
magnetic component, as does the manufacturer’s selection of the magnetic
material. For economic reasons, manufacturers of inductive components, such as
distribution transformers, design the magnetic circuit so that operation is near
the point at which the relation between voltage and current becomes highly non-
linear. Thus, repeating the test with a small difference in excitation voltage can
have a large impact on distortion. (Westinghouse’s Electrical T’rmwnissim and
Distribution Refeyerzce Book, fourth edition, indicates that an increase from 100% to
102% voltage will increase magnetizing current from 100% to 120% in
commercial distribution transformers.) Other factors that impact the
repeatability of such tests include design tradeoffs made in both the sizing of the
magnetic circuit and in magnetic materials used.
Even though one may not be easily able to predict the impact of a particular
magnetic component in an islanding test, it is clear that the more magnetics are
involved in the island, the more distortion will be seen in the islanded load. In
addition, an increase in magnetics in the islanded load decreases total power
factor even if an attempt is made to cancel the magnetizing current requirements
of the Ioad with capacitors (which only impacts displacement power factor, not
total power factor.) The characteristics of “off the shelf” PV inverters are such
that they will not be able to support an islanded load which contains significant
magnetic components, whether or not the magnetizing current is compensated
by capacitors. (Custom-designed inverters capable of operating with variable
power factor can be built. See “A Variable-Power-Factor-Inverter Consideration”
in chapter 10 for a brief discussion regarding these inserters.) This leads to the
conclusion that the fewer the magnetic components in the circuit, the more
meaningful the resulting test. This is because the most difficult islanding test for
an inverter is one with an undistorted, unity power factor load and circuit
resonance at 60Hz.
Another nonlinear effect that is seen in inductors is the result of the magnetic
core nonlinear B-H curve, which results in inductance varying as a function of
applied voltage as discussed earlier. Because of this, any mismatch in real
power, which causes a shift in voltage when the island is formed, will also affect
inductance. This, in turn, affects reactive power balance, which affects island
frequency. Because of this real world effect, it is more difficult to achieve the
balance necessary for islanding with magnetic components in the circuit.
Because of the above, it was determined that worst-case testing excludes the
distribution transformer from the islanded load. Therefore, all further testing
discussed in this report is performed without the transformer.
27
Relation to Actual Utility Conditions
The above discussion might lead one. to wonder if testing without a distribution
transformer in the island represents a real islanding situation on a utility
distribution line. Rather than examine various scenarios to determine the
probability of islands without distribution transformers, it is better to examine
the interaction of distribution transformers and utility line distortion.
Any islands that contain distribution transformers will also contain the loads on
those transformers, resulting in reasonable distortion values. Thus, the islanding
testing without a distribution transformer resdts in low distortion values, which
are more like those actually seen on utility systems. The current distortion
values seen with the unloaded transformer and associated capacitors are
uncharacteristically high for operating utility systenw.
28
in much of the “proof of concept” testing done at both Ascension Technology
and at Sandia. The motors were chosen specifically to have a “flywheel” effect.
In most of these tests a 1/2horsepower induction motor with capacitors and
grinding wheels attached was used. As will be seen, the addition of these motors
with flywheels did not, in general, result in an islanded load that was more
difficult to detect than a tuned RLC circuit without a motor. A theoretical
discussion of induction motors in islanded situations can be found in [3].
The motor did, however, add a variety of parameters to the test procedure that
change from one motor to the next, making repeatable tests extremely difficult.
For example, motor core materials, winding patterns, quality and condition of
bearings, and inertia all impact the electrical characteristics of the motor in an
island. Repeatability of testing with a tuned RLC load was excellent.
29
8. Preliminary Test Results
The testing at Sandia used multiple inverters in parallel. The Sandia testing
included more variables than the Ascension Technology testing, as the inverter
outputs continually varied as the sun varied, requiring frequent adjustment of
the load to maintain balance between load and inverter output. It was important
to do the Sandia testing to examine the response of multiple inverters in parallel,
as well as to confirm that the inverters behaved the same way in a “field”
environment as they did in the tightly controlled environment provided at
Ascension Technology.
Preliminary tests included a wide range of generation to load ratios and load
conditions. During the final testing, efforts ccmcentrated on worst-case load
testing only.
30
much faster test cycle time than is possible in field-testing. Firmware version
1.46 of the SunSineTM 300 utilized the SFS and SVS methods for anti-islanding.
Other RLC load combinations were tested, but are not presented here. The tests
presented represent the worst-case tests.
In Figures 5 and 6, the endpoints of the trajectories represent the last ii.dl cycle of
voltage or frequency measurement. At some time during the following cycle the
inverter shut down. The measurement system only made measurements on a
fuIl cycle of data, but the inverter makes measurements every half cycle.
Therefore, the inverter may trip before a full cycle of data is taken. For example,
all high-frequency trajectories in Figure 6 end below 63 Hertz. If the next
complete cycle of data were taken, then it would show the trajectory passing 63
Hertz.
31
SF S+SVS
Load: L+ C, Qres = 3.7
132
128
124
120
116
112
108
0 1 10 100
SFS + SVS
Load: L+ C, Qres =3.7
64
63
58
57
56
o 1 10 100
Trip Time (cycles)
32
Iosses of the motor (that is, the power required to maintain motor speed) were
119 watts, resulting in Q = 2.2. Again, a range of inverter power levels was used
to achieve a range of generation/load ratios that varied from 0.88 to 1.15. In
these tests, no island exceeded 70 cycles, well below the 2 seconds required by
IEEE/UL standards, and all trips were due to frequency trips. The power-factor-
corrected motor voltage would drop by Vi in 42 cycles after disconnect of all
sources of power. Figures 7 and 8 show the voltage and frequency trajectories
for motor load tests. Figure 9 shows that the time to trip is heavily influenced by
the generation-to-load ratio.
SFS + SVS
Load: Motor+ C
132.0
128.0
124.0
116.0
112.0
108.0
0 1 10 100
Trip Time (cycles)
33
Sl=s+svs
Load: Motor+ C
64 . ................. ...................
63 ..... .. .. .. ..
1-----’ !
62 . ... ......... .
R 61 ........ .. .
~ 1---------- ~
58
:,
i“”-”-””-”””-””-”--
57
4 ----------:
1 10 100
Trip Time (cycles)
34
SFS + SVS
Load: Motor + C
80 ---
,
70 [ ----------------;
------------------
;------------------:
-----------------~
---------------:
----------------
;------------------------
-- - \
20 ------------------:--------------
\
10- ---------. --------;----------=
\ +
o i
0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20
Generation I Load Ratio
Configuration.
Three of the specially modified SunSineTM 300 AC Modules were connected in
parallel with various loads in an outdoor array field for the evaluation of the
SVS/SFS anti-islanding technology. The circuit configuration is shown in Figure
10. The various loads were configured as required for each test and included R,
RL, RLC, RC, motor, and motors with C. The 1/2HP induction motor load
included a flywheel (based on the concept that the flywheel can store energy,
then transfer it back to the island through generator action). Parameters varied
included power factor, Pgeneration /l’load, and Q. one of the two disconnects shown
was used to interrupt the utility power. Because of the nonlinearity of the
magnetizing currents in the transformer, as previously discussed most tests were
performed using the secondary disconnect.
35
primary secondary
disconnect disconnect
The test loads were selected based on a variety of input. The first discussions
that indicated that an RLC circuit tuned to the power system frequency would be
a good islanding test load occurred during an International Energy Agency
workshop on PV/ grid interconnection that was held in Zurich, Switzerland, in
September of 1997. In addition, testing at Sandia and the theoretical results in
[3], indicated a problem with high-Q loads. The “distribution transformer” used
for those tests that included a primary side disconnect was unusually smalI (2
kVA) for a distribution transformer. That size was used to maintain an
appropriate scale for the three 300 watt, module scale inverters. This approach
resulted from the thought that two 4 kW invm-ters connected to a 15 kVA
distribution transformer wouId be representi~tive of two residential PV systems
and would operate in a similar manner.
Initially the value of C in the RLC circuit was fixed at 301 microfarads (1.63kvar
at 120Vac) and L was selected to provide 60 Hz resonance. The value of R was
then sized to dissipate power equal to that produced by the three parallel
inverters. This was a necessary condition for islanding. The value of R also
determines Q. Since, with var. = var, = var, and Q = var/P (as stated earlier in
equation 5), it follows that high Q is achieved by operating the inverters at low
power, as shown in Table 3. Thus the circuit could be islanded only for
particular combinations of inverter output power and values of R, L and C.
Q Power
&
(watts)
2 839
5 328
10 164
20 81
36
Test Results.
Three setsofdata arepresented in Table4. The first column ofdata was the
result of extensive testing of the SFS anti-islanding approach. (That is, SFS only,
no SVS). This was an extensive series that evaluated a full range of load types.
The results of the evaluation show that the SFS approach was very successful for
all cases with the exception of certain RLC loads with strong resonance at 60 Hz.
The run-on time is related to the circuit Q with run-on times of about 6 cycles
(approximately 100 milliseconds) for a Q equal to 1.5. For 1.5< Q <7, the
inverter shut down in less than 0.5 seconds (although relatively long for this
series of tests, still less than the 2 seconds required in IEEE Std. 929-2000 case 2).
For two of the higher Q cases (Q of 8 and 11), the circuit using only SFS islanded
untiI operator intervention.
The second cohmnn of data in Table 4 incIudes both the SFS and the SVS anti-
islanding methods. This series of tests was limited to the previously identified
worst cases, RLC and a 1/2HP induction motor load (with flywheel and
capacitor). This series of tests shows that the islanding associated with RLC
resonance has been eliminated, the longest time being .32 seconds for a Q = 7
case.
The third column of data in Table 4 expands on the second set by doubling the
available capacitance and hence increasing the allowable power output from the
inverters for a specific value of Q. While this doubled the islanding time to .78
seconds, the islanding time is still not lengthy and the Q of 8 is very high,
equivalent to having a line with uncorrected power factor of 12.5 % or less. This
very high Q condition is unlikely to occur in a normal distribution circuit
37
presents no unusual obstacles to the SFS/SVS anti-islanding technique. The
testing with three parallel inverters, and the sun as the energy source, was feIt
necessary to give a complete picture of the interaction of the SFS/ SVS technique
with motor loads.
The tests were configured as shown in Figure 10. The load consisted of the
motor (with its associated inductance and resistance), plus additional resistive
load to balance the output of the PV arrays, and adequate capacitance to balance
the inductance of the motor. The motor is a 112 HP induction motor that runs a
bench grinder. The grinder has two grinding wheels attached to enhance the
flywheel effect of the motor. The secondary dkconnect switch was used to
initiate the tests. Ten tests were run with this configuration, with all shutoff
times substantially less than the 2 seconds req@red by case 2 of IEEE Std. 929-
2000. Five of the tests were run with the motor and flywheel “freewheeling,” in
which case the motor consumed 270 watts to :maintain speed. The other five tests
were operated with a steel bar pressed against one of the grinding wheels to
increase the load on the grinder motor. In this condition, the motor consumed
420 watts to maintain speed. (The nameplate rating of the 1/2 HP motor was 480
watts.) The resistance was adjusted for these tests so that the balance between
load and generation was maintained. That is, the 3 inverters combined were
producing about 750 watts during these tests, so the total load needed to be
about 750 watts whether the motor was consuming 270 watts or 420 watts.
For both the loaded and unloaded grinder tests, the fastest inverter trip times
were 0.172 seconds. For the loaded grinder tests, the maximum run-on time was
0.196 seconds, while the maximum run-on time for the unloaded winder test was
0.22 seconds, as shown in Tables 5 and 6. Clearly, the two-second trip time Iirnit
was easily met.
38
Table 6. Trip times for% HP grinder motor without load.
39
9. The Non-islanding Inverter Test
The task, then, was to develop a test that wiIl be meaningful when applied to
single inverters. This test should identify inverters that have an anti-islanding
scheme that will assure that the inverter will not island if tested with multiple
inverters, This is where the concept of a load that is resonant at the power
system frequency (60Hz in the U.S.) with a Q of 2.5 is important. If the load in
the island under test is simply a resistance, and load and generation are not well
balanced, then basic frequency and voltage trip limits provide satisfactory
islanding protection. However, the addition c)f inductance and capacitance,
tuned to 60Hz, will tend to keep the frequency at 60Hz. Additionally, balancing
load and generation will maintain voltage within operational limits. Therefore,
an islanding test with balance between Ioad and generation (ratio of load to
generation between 0.5 and 1.5) and a 60 Hz resonant circuit with Q = 2.5
constitutes a satisfactory single-inverter non-isIanding test.
Non-Unity-Power-Factor Inverters
An additional complication arises with inverters that are designed to be able to
operate in either the utility-tied mode or the stand-alone mode. These inverters
are understandably popular because of their ability to provide the I?V system
owner with power even when there is a utility outage. This type of inverter
typically has two ac tie points - one that is tied to the utility and one that is tied
to those loads that the owner has chosen to keep energized during a utility
outage. The owner’s other loads are energized conventionally through the main
distribution panel, the same place that the PV system ties into the utility system.
The utility tie connection is the one to which the anti-islanding scheme applies.
During a utility outage, the inverter opens this tie, disconnecting the customer
and his PV system from the utility. At this time alI loads in his house are
dropped except those that are tied to the second inverter ac tie point. The
40
inverter maintains the connection to these loads, which the owner has selected
for operation during outages. Conceivably, the owner could choose to connect
the entire house to this second tie point so that the entire house would maintain
power during a utility outage. The owner would just need to be certain that the
PV system, and its battery backup, has the capacity to carry the load of the entire
house.
The fact that the inverter can source reactive power adds a complicating factor to
any islanding testing. One of the key features of an islanding test is that the real
power and the reactive power must be balanced independently at the point
where disconnection will take place. That is, the islanded real power load and
the islanded real power generation must equal each other, resulting in zero real
power current flow out of the island. The same must be done independently
with the reactive power.
The following is the test procedure that was developed to identify a non-
islanding inverter. This procedure is also included as an annex in IEEE Std. 929-
2000:
41
A
UTILITY I
A 1S2
DISCONNECT s] -
J-
/
SWITCH
1
UTILITY
I IT
R L
1
TC
INVERTER
~~
T’
Figure 11. Non-islanding inverter test circuit.
T
This test procedure is based on having the Q of the islanded circuit (including
load and inverter) set equal to 2.5. RecaIl the following equations from section 6
of this report (also recall that “var” is used to represent the magnitude of reactive
power):
Q = (l~)~VEirc x V=L
Q = varll?,
Harmonic current that flows between the utility, the loads and the inverter,
further complicates the situation by making it appear that current is flowing
42
when the 60 Hz component of current has been zeroed. Thus, it is important,
when adjusting inductive and capacitive reactance, to use instruments that can
distinguish the 60Hz component of current and power from other frequencies.
The sequence of the steps below is suggested for several reasons. The inductance
is measured first because that measurement is low in harmonics. The
capacitance is added second so that the voltage is stable when the resistance is
added. The resistive parallel load is then added and adjusted. Note that this
resistance will be in addition to the resistance that will be part of the inductive
load.
43
4) Comecting a resistor that results in the :power consumed by the RLC
circuit equaling Ptiv.
e) Connect the RLC load configured in step d) to the inverter by closing S 1. Close S2
and turn the inverter on, making certain that the power output is as determined in step
a).
(Note: The purpose of the procedure up to this point is to zero out the 60
Hz components of real and reactive power,’or to zero out the 60 Hz
component of current flow, at the utility disconnect switch. System
resonances will typically generate harmonic currents in the test circuit. These
harmonic currents will typically make it impossible to zero out an RMS
measurement of power or current flow at the disconnect switch. Because of
test equipment measurement error and some impact from harmonic currents,
it is necessary to make small adjustments in the test circuit to achieve worst
case islanding behavior. Step g) is performed to make these small
adjustments.)
f) Open the utility-disconnect switch to initiate the test.
g) After each successful test, one parmeter is adjusted by approximately 1.0%
per test, within a total range of A5% of the c)perating point determined in step
d) above. The parameter that is adjusted relay be load inductance, L, or load
capacitance, C. After each adjustment, an island test is run and time to trip is
recorded. If any of these tests results in islanding for longer than 2 seconds,
the unit fails the test and the test sequence is considered complete.
This test should be performed with the following ratios of real load to inverter
output, where both values are given as a percent of inverter full output rating:
Note that the final test, where load substantially exceeds generation, was
included in the IEEE test procedure at a time when there was no experience with
the non-islanding inverter. Testing since that time has shown that this is not a
useful test, and it will probably be deleted from the IEEE test procedure when
IEEE Std 929-2000 is revised in its next 5-year cycle.
44
SFS on, SVS on (Ten tests at each power level)
Note that the inverter without SFS and SVS passed the last test. This test was
performed with a mismatch between load and generation that was adequate to
cause the inverter to trip. Also note that the average trip time is 6 cycles, which
indicates a frequent y trip. (Recall that the first levels of voltage trips are allowed
120 cycles.) The mismatch in real power caused the island voltage to drop. The
load demanded more power than the PV could supply. Changing the voltage, in
this case dropping the voltage, affects the reactive power balance. This is
because inductance is typically very nonlinear with voltage, but capacitance is
more likely to be linear. In this case, the drop in voltage has the effect that the
varc now exceeds the varL and the resonant frequency drops quickly, causing the
inverter to trip on under-frequency.
45
Additional Testing of the Non-Islanding Inverter Test Procedure
In order to gain more confidence in the capability of the non-islanding inverter
test procedure, testing was performed on a previous-generation anti-islanding
technique, which had initially looked very promising. The test procedure
described above was used, with the required ten tests at each load level. The
testing was performed by Ascension Technology in their Boulder facility. The
results of these tests are illustrated in Figures 12a through 12d.
124
119
114
104
99
94
0 1 10 100 1000
Trip Time (cycles)
Figure 12a. Previous generation (non SFS/SVS) anti-islanding test - inverter voltage
and frequency trajectories for 25°/0inverter output and matched load case. Trip
points – 59.5Hz, 60.5Hz, 106V, 132V.
The inverter under test almost passed the first itestscenario where the inverter is
producing at 25% of its rated capacity, and the load equals the output, as shown
in Figure 12a. Of the ten tests performed, onIy one exceeded the aIIowed 120
cycles to trip, and that test tripped in 123 cycles. The quickest trip time in this
test series was 14 cycles.
I
The test sequences shown in Figures 12b and 12c reveal the shortcoming of this
particular anti-islanding technique. Recalling that the maximum trip time for
these test scenarios is 120 cycles, it is seen froml these two figures that many of
the tests went to 1000 cycles, where manual intervention terminated the test.
46
1007. Load 100% Gen, Q=2.5
,: ::
:: ::
61 -----: -- ,-,-------;. ..-,-.
\ :: :,
,,
,, :,
:: ::
:: :,
59 -------;
--- ,,..............>.
1
::
::
:: ::
:: :: ::
58 ---------- ::
, .,. ,.
,.,.....– ,. ...:..
:: ,.
., ::
::::’
,,, ,, ::
::::: :,
,,~,
0 1 10 100 1000
Trip Time (cycles)
Figure 12b. Previous generation (non SFS/SVS) anti-islanding test - Non SFS/SVS
inverter voltage and frequency trajectories for 50°/0inverter output and matched
load case. Trip points – 59.5Hz, 60.5Hz, I06V, 132V.
47
50% Load 50% Gen, Q=2.5
o 1 10 +00 1000
Trip Time (cycles)
Figure 12c. Previous generation (non SFS/SVS) anti-islanding test - inverter voltage
and frequency trajectories for 100°/0 inverter output and matched load case. Trip
points - 59.5Hz, 60.5Hz, 106V, 132V.
In this particular set of tests, the inverter under test easily passed the last test
scenario, shown in 12d. In this test, the inverter is operating at full capacity, and
is loaded at 125% of capacity. In each of the ten tests in this scenario, both
voltage and frequency went beyond the initial trip points. Since frequency has a
quicker trip time than voltage at the first tril? point (six cycles for frequency,
versus 120 cycles for voltage), all the tests illustrated in Figure 12d resulted in
under-frequency trips.
48
lzs~o Load 400% Gen, Q=2.5
120
,,:::
.........
:, :
115
::
.k \
::
.,,-;;:
:
:::’
.. ................
V+a~e~
::;:
::.’
::;::
::,
;:,
,,
......... 110
95
,,, ,::
\iK-: IF!+?! :.—
90
80
0 1 10 100 1000
Trip Time (cycles)
Figure 12d. Previous generation (non SFS/SVS) anti-islanding test - inverter voltage
and frequency trajectories for 100°/0 inverter output and 125°/0load case. Trip
points – 59.5Hz, 60.5Hz, 106V, 132V.
Many of the inverters were able to pass both the resistive and motor load test,
but failed the Non-islanding Inverter test. These results supported use of the
Non-islanding Inverter test to distinguish between non-islanding inverters and
those that do not employ an adequate anti-islanding technique.
49
Multiple-Inverter Testing
Although multiple-inverter testing is not included in IEEE Std. 929-2000 or UL
1741, Sandia Laboratories will continue to periorm multiple-inverter and single-
inverter evaluations. The purpose of the tests is to continue to expand our
knowledge base and to ensure that the single-inverter test is adequate for new
inverter models.
50
10. Implementing SVS & SFS Islanding Protection in a Static
Utility Interactive Inverter
.
Islanding protection is needed in utility interactive inverters when those
inverters are outside the control of utility system operators and it is desired to
have the inverter shut down when the rest of the utility shuts down as well. In a
majority of situations, voltage and frequency operating limits are sufficient to
prevent a persistent island of an inverter with a section of the grid that has been
‘shut down’,
The method presented below uses those same voItage and frequency trip
setpoints to decide when to shut down the inverter. No additional sensing
mechanisms, such as sensing a phase shift in the voltage waveform, sensing
changes in utility impedance, sensing changes in voltage harmonic content or
rates of change of utiIity frequency are used by the inverter to decide when it is
time to shut down.
Voltage Sensing
AC voltage is measured by sampling the ac voltage waveform 64 times per cycle,
a sample rate of 3,840 samples per second. The timing of these samples is
synchronized with the zero crossing of the ac voltage using software methods. A
hardware phase lock loop is not used. A signal, representative of the ac voltage,
is added to a fixed dc offset and enters an 8-bit a/ d converter. The ac signal is
added to a dc offset so that a unipolar 0.0 to 5.O-volt a/ d converter can be used.
The microprocessor computes the ac voltage based on the following formulas.
RA4S$=D(?+V2
V= sqrt(l?kl~ – DC2)
The need for an RMS-type computation of V may be questioned with the thought
that the average of the rectified voltage should be sufficient. This is certainly
51
true for the purposes of SVS operation. However, we have used an RMS method
because measurement inaccuracies can arise when averaging is used to compute
ac voltage in the presence of changing voltage harmonic distortion.
The important point to note from this section is that ac voltage is measured and
computed every Y2cycle.
As can be seen, there are fast, medium, and SIC}Wspeed trip times. Any number
of trip settings and times to operate could be programmed into such a unit. The
intent is to trip faster on the more severe voItage changes, but to ride through the
less severe excursions, hence minimizing nuisance tripping of the unit during
normal power system operation.
For any particular trip speed there is a counter, SloW_cOUntfor example. If the
voltage exceeds the slow trip limit, the counter is incremented. If the voltage is
in the satisfactory range, the counter is decrem.ented. The counter is never
allowed to ‘roll over’ or go past the limit for an 8 bit counter of 255; nor is the
counter allowed to ‘roll under’, or decrement a step backwards from Oto 255.
This increment/ decrement operation is performed once every 1/2 cycle. A
counter larger than 8 bits could be used if desired times to operate exceeded 127
cycles.
When a counter exceeds its allowed number of steps, the inverter is shut down.
Frequency Sensing
The ac voltage signal is passed into a Zero Crossing Detect (ZCD) circuit. This
circuit has filtering to filter out the effects of high frequency noise on the power
line. The output of the circuit is a square wave logic signal that passes into the
microprocessor. A 16-bit timer running at 5.0 MHz captures the rising and
falling edges of the ZCD signal in the microprocessor. This timer rolls over every
13.1 milliseconds, enough time to measure the period of each % cycle to a
resolution of 200 nanoseconds.
Once every cycle, the period measurement from the last two 1/2 cycles is
combined to determine the period of the last cycle of ac voltage. The resulting
52
period measurement is then converted to a frequency and compared to the
stored frequency trip limits once per full cycle.
The 1 cycle trips don’t need a counter. The counter for the 5 cycle trips is
implemented in the same manner as the counters for the voltage trips.
The SVS and SFS methods add positive feedback to the output current controls of
the inverter such that system operation under these circumstances is
destabilized. It is important not to make the positive feedback so strong that it
destabilizes the utility grid. Fortunately, not much positive feedback is needed
to destabilize even strong islands.
53
Sandia Voltage Shift (SVS)
The measurement of ac voltage, Vi, is the starting point of the SVS method, and is
described above. The voltage measurement is first scaled to obtain high
resolution between 90.0 to 154 volts.
The parameter kv determines the time-constant of the IIR filter, and in our
implementation was 1/256. This filter computation is made every 1/2cycle.
An error signal, Evl, is computed as the difference between the most recent
measurement of ac voltage and the filtered ac voltage.
Evi = Vpsi– VJ
If Evi is positive, that means that the most recent voltage is greater than the
average voltage, that is, voltage is rising. If Evl is negative, voltage is dropping.
During normal operation of the power system, there will be nom-d cycle by
cycle fluctuations in Vpsi, thus creating fluctuations in Evi. As long as the grid is
connected, these fluctuations are small.
When the voltage appears to be rising, the output current control is increased.
When the voltage is dropping, the output current control is decreased. As long
as the grid is connected, operation of the inverter will not affect system voltage.
Thus, even though the output current is fluctuating a small amount, it will not
sustain a trend. YVhen the grid is no longer connected, any fluctuation in voltage
will cause the inverter to react. Since the utility is no longer maintaining system
voltage, the inverter will continue to push voltage either up or down until a
voltage trip shuts down the inverter.
One of the benefits of this method is that multiple inverters on the system will
support each other in destabilizing the island. If system voltage at one inverter is
rising, it is likely that it is also rising at other inverters on the island. Island
operation with inverters controlled in this manner is inherently unstable.
54
OutputCurrentControl
The control of the magnitude of the output current of the inverter is done
depending upon the application. In photovoltaic applications, output current is
increased or decreased to track the maximum power of the photovoltaic power
source. This maximum power tracking has a slow time constant compared with
the cycle by cycle variations mentioned above. For the purpose of destabilizing
an island, one may assume that the maximum power tracking output current
magnitude command signal, designated Pmpt, is constant during operation of
the islanding protection method. In the SunSine@ 300 inverter, the value of Pmpt
varies from about Oto 200, and is stored in an 8 bit register. For purposes of
these discussions, a value of Pmpt of 200 represents 100% inverter output. Evl
ranges from -127 to +127 and represents an error voltage of -32 to + 32 volts ac.
When Evi is zero, Pcmdi = Pmpti. As the magnitude of Evi increases we know
that the voltage is moving either up or down and will eventually reach one of the
trip limits. In other words, high gain is needed to destabilize the system.
SandiaFrequencyShift
The SFS method is similar in principle to the SVS method. The SFS method acts
to destabilize system frequency.
The measurement of frequency, Fi, is the starting point of the SFS method, and is
as described above for vohage measurement. The frequency measurements are
digitally filtered with a simple IIR filter. The filtered result, call it Ffi, is a
measure of the average recent ac frequency. Ffi does not fluctuate very much
because it is a filtered parameter. The subscript 1indicates data from the most
recent 1/2cycle. A subscript i-l is data from the 1/2cycle before that.
The parameter kf determines the time-constant of the IIR filter, and in our
implementation was 1/256.
An error signal, Efi, is computed as the difference between the most recent
measurement of frequency and the filtered frequency.
Ej$=Fi-F~
55
If Efi is positive, that means that the most recent frequency is greater than the
average frequency, that is, frequency is rising. If Efi is negative, frequency is
dropping. During normal operation of the power system, there wiIl be normal
cycle by cycle fluctuations in Fi, thus creating fluctuations in Efl. As long as the
grid is connected, these fluctuations are very small.
When the frequency appears to be rising, the output current control frequency is
increased. When the frequency is dropping, thle output current control frequency
is decreased. As long as the grid is connected, operation of the inverter will not
affect system frequency, so even though the output current is fluctuating a small
amount, it will not sustain a trend. When the grid is no longer connected, any
fluctuation in frequency will cause the inverter to react. Since the utility is no
longer maintaining system frequency, the inverter will continue to push
frequency either up or down until a frequency trip shuts down the inverter.
One of the benefits of this method is that multiple inverters on the system will
support each other in destabilizing the island. If system frequency at one
inverter is rising, it is also rising at other inverters on the island. Island operation
with inverters controlled in this manner is inherently unstable.
The effect of such operation in an island is that the inverter quickly causes island
frequency to move outside the trip limits. When the inverter is connected to the
utility, these small fluctuations do not affect system frequency.
InverterFrequencyControl
Thesinewave frequency, Finv, of the output current waveform is determined
based upon the grid frequency, Fgrid, and the frequency error Efi (also called
frequency deviation).
56
The function, fn20, is shown in the chart below. The steps seen in the graph are
due to digitization and resolution effects in the digital implementation
Figure 13. SFS compensation curve, showing the relation between measured
frequency deviation and the shift that SFS will apply.
FastResponse,It is Critical!
Theability of the SVS & SFS methods to react quickly in shutting down an island
is partly due to fast and accurate measurement and control. Accurate measures
of voItage and frequency are made on the order of 1 cycle. Computation of the
output current controls is made during the next 1/2 cycle before being applied to
the output current waveform. This implies an average delay time of about 1
cycle in the destabilizing control loop.
57
A Variable-Power-Factor-Inverter
Consideration
PV inverters can be designed to operate at power factors other than unity, and an
interconnecting utility may request that an inverter for a large PV system operate
at some non-unity power factor. However, the IEEE and UL standards for
inverters rated 10kW or less requires that they operate at greater than .85 power
factor, and most are designed to operate at unity power factor. The SVS and SFS
methods could work with a variable power factor inverter as long as the power
factor of the inverter changes slowly enough that it is nearly constant over the
time period that anti-islanding controls need to operate. We would suggest an
order of magnitude difference in response times between the power factor
response and the anti-islanding response to provide a comfortable degree of
margin. Thus the power factor tracking feature of such an inverter should have a
response time no faster than 20 seconds. If a power-factor-tracking inverter were
able to change power factor to match the load,, and did so with a response time
faster than 2 seconds, it is quite possible that such operation would interfere with
SVS and SFS operation. However, this would depend very much on the details
of exactly how such power factor correction operation is irnplemented.
58
11. Conclusions
The SVS and SFS methods have been fairly easy to implement. The only
modifications necessary to implement them in the inverters used for testing were
changes in firmware. No changes to the hardware were required. This may not
be true in general for all inverter designs.
Results presented here are far superior to results of other anti-islanding tests
conducted over the last 18 months both at Ascension Technology and at Sandia
National Laboratories. This work was supported by a consensus of U.S. inverter
manufacturers. Although not guaranteed, it is likely that the results of this work
will move toward a defacto standard for anti-islanding in the United States. It is
hoped that by sharing these results, similar methods will be considered in the
international community.
A significant product of this work was the establishment of a test procedure that
can be used to distinguish between inverters that have satisfactory anti-islanding
techniques and those that do not.
59
12. References
60
DISTRIBUTION
Chuck Whitaker
u-is Freitas Greg Kern
Endecon Engineering
ace Engineering Company Ascension Technology
2500 Old Crow Canyon Road
’16 195ti N.E. 4700 Sterling Drive, Suite E
Suite 220
‘Iington, WA 98223 Boulder, CO 80301
San Ramon, CA 94583
61
Michael Ropp Tron Melzl
John Moriarty
Electrical Engineering Department S&C Electric
Raytheon Systems Company
BOX 2220, HH205 Power Electronics Division
50 Apple Hill Drive, T3TN46
South Dakota State University P.O. BOX 879
Tewksbury,MAO1876-0901
Brookkgs, SD 57007-2220 East Troy, WI 53129 ,
Lynne Gillette
Steve Hester Miles Russell
U.S. Department of Energy
Utility PhotoVoltaic Group Ascension Technology
Forrestal Building
1800 M Street, NW, Ste. 300 P.O. Box314
1000 Independence Ave., S.W.
Washington, DC 20036-5802 Lincoln Center, MAO 1773
Washington, DC 20585
62