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DGD 8 Sol

This document contains solutions to several digital logic design problems involving finite state machines (FSMs). Question 1 calculates the maximum clock frequency of a 4-bit linear feedback shift register (LFSR) given timing parameters. Question 2 determines the maximal clock rate of a decade counter circuit. Question 3 compares the maximum clock rates of two implementations of a programmable mod-m counter. Question 4 provides the design process and solution for an odd parity detector FSM. Question 5 asks to design an FSM and write VHDL code for a circuit that blinks a light, keeping it on for T1 clock cycles and off for T2 cycles while starting in the on state.

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Dolores Makaruina
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243 views6 pages

DGD 8 Sol

This document contains solutions to several digital logic design problems involving finite state machines (FSMs). Question 1 calculates the maximum clock frequency of a 4-bit linear feedback shift register (LFSR) given timing parameters. Question 2 determines the maximal clock rate of a decade counter circuit. Question 3 compares the maximum clock rates of two implementations of a programmable mod-m counter. Question 4 provides the design process and solution for an odd parity detector FSM. Question 5 asks to design an FSM and write VHDL code for a circuit that blinks a light, keeping it on for T1 clock cycles and off for T2 cycles while starting in the on state.

Uploaded by

Dolores Makaruina
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CEG3155: Digital Systems II Medhat Elsayed

CEG3155: DGD 8
Question 1
Let the propagation delay of an xor cell be 4 ns, and the setup time and clock-to-q delay of the
register be 2 and 3 ns respectively. Determine the maximum clock frequency of a 4-bit LFSR.

Solution

Critical path delay:


𝑡𝑐 = 4 + 2 + 3 = 9 𝑛𝑠
Maximum allowable frequency
1
𝑓𝑐 = = 111.11 𝑀𝐻𝑧
𝑡𝑐

Question 2 (Chu 8.11)


Consider the block diagram of the decade counter in Figure 8.13. Let 𝑇𝑐𝑞 and 𝑇𝑠𝑒𝑡𝑢𝑝 of the DFF
be 1 and 0.5 ns, and the propagation delays of the incrementor, comparator and multiplexer be 5,
3 and 0.75 ns respectively. Assume that no further optimization will be performed during synthesis.
Determine the maximal clock rate.
CEG3155: Digital Systems II Medhat Elsayed

Solution
The critical path of the next-state logic consists of the incrementor and multiplexer (the
comparator run in parallel with the incrementor and thus has no effect on the critical path).

𝑡𝑙𝑜𝑔𝑖𝑐 = 𝑡𝑖𝑛𝑐 + 𝑡𝑚𝑢𝑥 = 5 + 0.75 = 5.75 𝑛𝑠


𝑡𝑐𝑙𝑘 = 𝑡𝑙𝑜𝑔𝑖𝑐 + 𝑡𝑐𝑞 + 𝑡𝑠𝑒𝑡𝑢𝑝 = 5.75 + 1 + 0.5 = 7.25 𝑛𝑠
1
𝑓𝑐𝑙𝑘 = = 138 𝑀𝐻𝑧
𝑡𝑐𝑙𝑘

Question 3 (Chu 8.12)


Consider the two block diagrams of the programmable mod-m counter in Figure 8.14. Assume
that no further optimization will be performed during synthesis. Use the timing information in
Problem 8.1 1 to determine the maximal clock rates of the two configurations.

Solution
a)
𝑡𝑙𝑜𝑔𝑖𝑐 = 𝑡𝑖𝑛𝑐 + 𝑡𝑚𝑢𝑥 = 5 + 0.75 = 5.75 𝑛𝑠
𝑡𝑐𝑙𝑘 = 𝑡𝑙𝑜𝑔𝑖𝑐 + 𝑡𝑐𝑞 + 𝑡𝑠𝑒𝑡𝑢𝑝 = 5.75 + 1 + 0.5 = 7.25 𝑛𝑠
1
𝑓𝑐𝑙𝑘 = = 138 𝑀𝐻𝑧
𝑡𝑐𝑙𝑘
b)
𝑡𝑙𝑜𝑔𝑖𝑐 = 𝑡𝑖𝑛𝑐 + 𝑡𝑐𝑜𝑚𝑝 + 𝑡𝑚𝑢𝑥 = 5 + 3 + 0.75 = 8.75 𝑛𝑠
𝑡𝑐𝑙𝑘 = 𝑡𝑙𝑜𝑔𝑖𝑐 + 𝑡𝑐𝑞 + 𝑡𝑠𝑒𝑡𝑢𝑝 = 8.75 + 1 + 0.5 = 10.25 𝑛𝑠
1
𝑓𝑐𝑙𝑘 = = 97 𝑀𝐻𝑧
𝑡𝑐𝑙𝑘

Question 4
Odd/Even Parity Detector
Consider a logic circuit that counts the number of ones in a bit serial input stream. If the circuit
asserts its output when the input contains an odd number of ones, it is called odd parity. If it asserts
its output when the input contains an even number of ones, it is called even parity. Use FSM to
design an odd parity detector circuit.
CEG3155: Digital Systems II Medhat Elsayed

Solution
FSM Design Process:
1. Draw the state diagram.
2. Translate the state diagram into a state transition table.
3. Write the logic expressions for next-state and output logic using the state transition
table.
4. Implement the circuit using logic gates.

1. Draw the state diagram


The circuit can have two states: Either even or odd number of ones have been seen since reset.

a=1

Even Odd a=0


y=0 y=1

a=0
a=1

2. State transition table


Symbolic Table Present state Input (a) Next state Output (y)
Even 0 Even 0
Even 1 Odd 0
Odd 0 Odd 1
Odd 1 Even 1

Encoded Table Present state (PS) Input (a) Next state (NS) Output (y)
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 1

3. Logic expressions
𝑁𝑆 = 𝑎 ⊕ 𝑃𝑆

𝑦 = 𝑃𝑆
CEG3155: Digital Systems II Medhat Elsayed

4. Implementation

D Q
a
D-FF

CLK CLK

Question 5
Blinking light
This problem concerns a circuit that must turn a light on and off, remaining on during T1 clock
periods and off during T2 clock periods. An important desired feature is that when the circuit is
enabled it must start from a state with the light on (to prevent the user from thinking that the
circuit is not working when large transition times are involved).
a) Design the FSM.
b) Write a VHDL to describe the operation of the circuit.

Solution
CEG3155: Digital Systems II Medhat Elsayed
CEG3155: Digital Systems II Medhat Elsayed

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