EEC302: MICROPROCESSORS AND INTERFACING

Course Objectives:
1. To study the architecture of the general purpose microprocessors
8085 and 8086.
2. To understand the assembly language programming of both 8085
and 8086 processors.
3. To impart knowledge about assembly language programming to
interface various peripherals like data converters, keyboards,
display units etc.,
4. To interface different peripheral units with microprocessors i.e., the
hardware of various consumer electronic goods.
5. To design and implement microprocessor based embedded
systems.

Course Outcomes:
Students will be able to
1. Acquire the knowledge of the internal architecture, memory
organization and operating modes of processors.
2. To write efficient codes on 8 bit and 16-bit platform.
3. interface the microprocessor with different peripheral ICs such as
8255, 8251, 8257, 8279 etc.,
4. Design standalone microprocessor - based systems.

Prepared by
Dr Sreenivasa Rao Ijjada
Dept of ECE,GIT, GITAM University, Visakhapatnam
2019-2020
[email protected]

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 1
Module I: 8085 Microprocessors & Architecture

Microprocessors historical, perspective, 8085 pin diagram, architecture,

addressing modes, overview of 8085 instruction set, microprocessor
communication and bus timings, 8085 functional block diagram.

Microprocessor: It is an IC with all the functions of a CPU however, it cannot be

used stand alone since unlike a microcontroller it has no memory or peripherals.
It is a multipurpose, programmable, clock-driven, register-based electronic device
that reads binary instructions from a storage device called memory, accepts
binary data as input and processes data according to those instructions and
provide results as output.

Microprocessors can be classified based on the data bus width

 4-Bit Microprocessors
 8-Bit Microprocessors
 16-Bit Microprocessors
 32-Bit Microprocessors
 64-Bit Microprocessors

1. History:

Microproces Bata Bus Pins No.Of

sor transi
Intel
4004 4-bit 640 bytes 16 2300 1971
8008 8-bit 16KB 18 3500
8080 8-bit 64KB 40 6000
8085 8-bit 64KB 40 1976
8086 16-bit 1MB 40 29000 1978
8088 8/16 bit 1MB 40 1979
80186 16-bit 1MB 68 1982
80286 16-bit 16MB real, 4 68 134000 1982
GB Virtual
80386 32-bit 4GB real, 132 PGA 275000 1986
64TB virtual
80486 32-bit 4GB real, 168 PGA 1200000 1989
64TB virtual
Pentium 64-bit 4GB real l 273 PGA 3.1 1993
Million
Pentium 64-bit 64 GB real 5.5 1995
pro Million
Pentium II 64-bit 64 GB real 7.5 1997
Million
Pentium II 64-bit 1998
XEON
Pentium III 64-bit 1999
Pentium 64-bit 2000

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 2
IV
Dual Core 64-bit 2006
Core 2 2006
Core i7 2008
Core i5 2009
Core i3 2010
Motorola
6800 8-bit 64KB 40 1974
6809 8-bit 64KB 40 1978
68000 16-bit 16MB 64 1979
68020 32-bit 4GB 169 PGA 200000 1984
68030 32-bit 4GB 169 PGA
68040 32-bit 4GB
Zilog
z-80 8-bit 64KB 40
z-800 8-bit 500K
z-8000 16-bit 64KB

It is a 2nd generation microprocessor and is the base for studying and using all
the microprocessor available in the market.

2. Salient features of 8085 μp:

 It is an 8 bit microprocessor.

 It has 16(A0-A15) bit address lines (AB), hence can address up to 216 =
65536 (64K) memory locations.

 Data bus (DB) is a group of 8 lines D0 – D7.

 First 8 lines of AB & 8 lines of DBs are multiplexed AD0 – AD7.

 It supports 5 hardware interrupt & 8 software interrupt.

 A 16 bit program counter (PC)

 A 16 bit stack pointer (SP)

 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.

 It requires a signal +5V power supply

 Max.clock Frequency= 3MHz and Min.clock Frequency=500kHz

System Bus

Bus is a group of conducting wires which carries information, all the peripherals
are connected to microprocessor through Bus. There are three different types of
buses.

 Address bus

 Data Bus

 Control Bus

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 3
Address bus –It is a group of conducting wires which carries address only. AB is
unidirectional because address flows in one direction, from μp to memory or from
μp to Input/output devices. The range of Address of 8085 μp is from 0000 H to
FFFF H. The μp can address 65, 536 different memory location. The Length of the
AB determines the amount of memory can be handled. Actual amount of memory
can be accessed is usually much less than this theoretical limit due to chipset
and motherboard limitations.

Data bus –It is a group of conducting wires which carries Data only. DB is
bidirectional because data flow in both directions, from μp to memory or
Input/Output devices and from memory or Input/Output devices to μp. It is
ranging from 00 H to FF H. In write operation, the μp will put the data on the DB,
where as in read operation, the memory controller will get the data from specific
memory block and put it into the DB.

The width of the DB is directly related to the largest number that the bus can
carry, such as an 8 bit bus can represent 2 to the power of 8 unique values, this
equates to the number 0 to 255. A 16 bit bus can carry 0 to 65535.

Control bus –It is a group of conducting wires, which is used to generate timing
and control signals to control all the associated peripherals, μp uses control bus
to process data, that is what to do with selected memory location. Some control
signals are:

Memory read

Memory write

I/O read

I/O Write

Opcode fetch

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 4
If one line of control bus may be the read/write line. Low on this line indicates
the read operation, if this is high, it is write operation.

Control and Status Signals:

ALE (Address Latch Enable) signal: It goes high during first T state of a every
machine cycle and enables the lower 8-bits of the address, and for the rest of the
T states of the machine cycles the lower 8-bits are data nines.

IO/M’ – It is a status signal which determines whether the address is for input-
output or memory. When it is high (1) the address on the address bus is for
input-output devices. When it is low(0) the address on the address bus is for the
memory.

RD’ – It is a signal to control READ operation. When it is low the selected memory
or input-output device is read.

WR’ – It is a signal to control WRITE operation. When it goes low the data on the
data bus is written into the selected memory or I/O location.

SO, S1 – These are status signals. They distinguish the various types of
operations such as halt, reading, instruction fetching or writing.

IO/M’ S1 S0 RD’ WR’ Data Bus Status

X 0 0 High impedance Halt
X X X High impedance HOLD
X X X High impedance HLD
INTA’=1
0 0 1 1 0 Memory write
0 1 0 0 1 Memory read
0 1 1 0 1 Opcode fetch
1 0 1 1 0 I/O write
1 1 1 0 1 I/O read
1 1 1 INTA’=0 Interrupt acknowledge

READY – It senses whether a peripheral is ready to transfer data or not. If READY

is high (1) the peripheral is ready. If it is low (0) the microprocessor waits till it
goes high. It is useful for interfacing low speed devices.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 5
Architecture:

Fig 1.2: 8085 Architecture

(a) General Purpose Registers –

The 8085 has 6 general-purpose registers to store 8-bit data; these are identified
as- B, C, D, E, H, and L. They can be combined as register pairs – BC, DE, and
HL, to perform 16-bit operations. These registers are used to store or copy
temporary data during the execution of the program.

(b) Specific Purpose Registers –

Accumulator: The accumulator is an 8-bit register (can store 8-bit data) that is
the part of the arithmetic and logical unit (ALU). After performing arithmetical or
logical operations, the result is stored in accumulator. Accumulator is also
defined as register A.

Flag registers: It is a special purpose register and it is completely different from

other registers. It consists of 8 bits and only 5 of them are useful. The other three
are left vacant and are used in the future Intel versions. The 5 flags are set
or reset (1-set and 0-reset) after an operation according to data condition of the
result in the accumulator and other registers. The 5 flag registers are:

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 6
 Fig 1.3: flag register

Sign Flag: It is 7thbit of the flag register, which is also known as the MSB. It
helps the programmer to know whether the number in the accumulator is
positive or negative. After any operation if the MSB of the result is 1, it in
indicates the number is negative and the sign flag becomes set, i.e. 1. If the
MSB is 0, it indicates the number is positive and the sign flag becomes reseti.e.0.
from 00H to 7F, sign flag is 0 from 80H to FF, sign flag is 11- MSB is 1 (negative)
0- MSB is 0 (positive)

Example:

MVI A, 30H // A=30H

MVI B, 40 // B=40H
SUB B // (A = A – B)
A=-10H S=1
MVI A 40 // A=40H
// B=30H
MVI B 30 //(A = A – B)
SUB B A=10H S=0

Zero Flag: 6th bit of the flag register. After any arithmetical or logical operation if
the result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise it becomes
reset i.e. 0.00H zero flag is 1.from 01H to FFH zero flag is 01- zero result, 0-
non-zero result. It helps in determining if two numbers are equal or not.

Example:

MVI A, 10 //A=10H

SUB A //(A = A – A)

A=00H and Z=1

Auxiliary Carry Flag (AC): It is 4th bit of the flag register. This flag is used in
BCD number system (0-9). If after any arithmetic or logical operation B(3)
generates any carry and passes on to B(4) this flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0. Note –Flag register in 8085 which is not accessible by user

Example:

MOV A, 2B //A=2BH
MOV B ,39 //B=39H
ADD B //(A = A + B)

A= , AC=11

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 7
Parity Flag: It is 2nd bit of the flag register. This flag tests for number of 1’s in the
accumulator. If after any arithmetic or logical operation the result has even
parity, if the accumulator holds even number of 1’s, it is set, P=1. On the
other hand if the number of 1’s is odd, then it is reset, P=0, it is said to be odd
parity.

Example: MVI A 05 //A=05H

BCD code of 05H is 00000101, hence P=1

Carry Flag: 0th bit of the flag register. Carry is generated when performing n bit
operations and the result is more than n bits, then this flag becomes set i.e. 1,
otherwise it becomes reset i.e. 0. During subtraction (A-B), if A>B it becomes
reset and if (A<B) it becomes set. Carry flag is also called borrow flag.1-carry out
from MSB bit on addition or borrow into MSB bit on subtraction 0-no carry out
or borrow into MSB bit

Example:

MVI A 30 //A=30H
MVI B 40 //B=40H
SUB B // (A = A – B)
since A<B,CY=1 as 30 – 40 generates a carry/borrow.

MVI A 40 //A=40H
MVI B 30 //B=30H
SUB B //(A = A – B)
since A>B,CY=0 as 40 – 30 generates a carry/borrow.

(c) Memory Registers –There are two 16-bit registers used to hold memory
addresses. The size of these registers is 16 bits because the memory addresses
are 16 bits. They are:-

Program Counter: This register is used to sequence the execution of the

instructions. The function of the program counter is to point to the memory
address from which the next byte is to be fetched. When a byte (machine code)
is being fetched, the program counter is incremented by one to point to the
next memory location.

Stack Pointer: It is used as a memory pointer. It points to a memory location in

read/write memory, called the stack. It is always incremented/decremented by 2
during push and pop operation.

Pin diagram & Description

S.No Signals No.of Pins

1 Address & data bus 16
2 Control & status signals 6
3 Power supply & Clock related signals 5
4 Interrupts & peripheral initiated signals 7

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 8
5 Reset signals 2
6 DMA signals 2
7 Serial I/O signals 2

Fig 1.4: Pin diagram

1. Address Bus & Data Bus: The AB is a group of sixteen lines i.e A0-A15. The
AB is unidirectional, i.e., bits flow in one direction from the microprocessor unit
to the peripheral devices and uses the high order address bus.

2. Control and Status Signals:

ALE – Address Latch Enable signal. It goes high during first T state of a machine
cycle and enables the lower 8-bits of the address, if its value is 1 otherwise data
bus is activated.

IO/M’ – It is a status signal which determines whether the address is for input-
output or memory. When it is high(1) the address on the address bus is for input-
output devices. When it is low(0) the address on the address bus is for the
memory.

SO, S1 –Status signals. They distinguish various types of operations such as

halt, reading, instruction fetching or writing. types of operations as given below.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 9
 IO/M’ S1 S0 Operation

0 0 0 HALT

0 0 1 Memory WRITE

0 1 0 Memory READ

0 1 1 OPCODE FETCH

1 0 1 I/O Read

1 1 0 I/O Read

1 1 1 interrupt ack

RD’( To control READ operation): When it is low the selected memory or input-
output device is read.

WR’( To control WRITE operation): When it goes low the data on the data bus is
written into the selected memory or I/O location.

READY – It senses whether a peripheral is ready to transfer data or not. If READY

is high (1) the peripheral is ready. If it is low(0) the microprocessor waits till it
goes high. It is useful for interfacing low speed devices.

3. Power Supply and Clock Frequency

Vcc – +5v power supply

Vss – Ground Reference

XI, X2(CLK in) – A crystal is connected at these two pins. The frequency is
internally divided by two, therefore, to operate a system at 3MHZ the crystal
should have frequency of 6MHZ.

CLK OUT – This signal can be used as the system clock for other devices.

Fig 1.5: clock setup

4. Interrupts & Peripheral Initiated Signals:

The 8085 has five interrupt signals that can be used to interrupt a program
execution.

(i)INTR (ii)RST 7.5 (iii) RST 6.5 (iv) RST 5.5 (v) TRAP

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 10
In addition to Interrupts, there are three externally initiated signals namely
RESET, HOLD and READY. To respond to HOLD request, it has one signal called
HLDA.

INTR – It is an interrupt request signal.

INTA’ – It is an interrupt acknowledgment sent by the microprocessor after

INTR is received.

5. Reset Signals:

RESET IN’ – When the signal on this pin is low(0), the program-counter is set
to zero, the buses are tristated and the microprocessor unit is reset.

RESET OUT – This signal indicates that the MPU is being reset. The signal can
be used to reset other devices.

6. DMA Signals:

HOLD – It indicates that another device is requesting the use of the address
and data bus. Having received HOLD request the microprocessor relinquishes
the use of the buses as soon as the current machine cycle is completed.
Internal processing may continue. After the removal of the HOLD signal the
processor regains the bus.

HLDA – It is a signal which indicates that the hold request has been received
after the removal of a HOLD request, the HLDA goes low.

7. Serial I/O Ports:

Serial transmission in 8085 is implemented by the two signals SID and SOD

SID is a data line for serial input

SOD is a data line for serial output.

Point form of 8085 registers

Fig 1.6: registers organization

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 11
Instruction set:

Instruction: it is a command to the processor to perform a given task on specified

data. It has two parts

 Opcode
 Operand

Opcode: The task to be performed

Operand: data to be operated on

T state: A portion of an operation carried out in one system clock period is called as
T-state

Machine cycle: Time required to access the memory or input/output devices

is called machine cycle

Instruction cycle: it is time required to complete the execution of the

instruction. It consists of 1-5 M/Cs. Fetch, decode and execute are sub tasks
of instruction cycle

Instruction set of 8085 is classified based on size and based on the operation

There are classified according to the size

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 12
  Single byte instructions
 Two byte instructions
 Three byte instructions

1Byte instruction: these instructions requires only one memory location for the storing
in the memory.

Ex: MOV,ADD,SUB,ORA,ANA.INR,DCR

2 Byte instruction: these instructions requires two one memory location for the storing
in the memory.

Ex: All the instructions with ending letter ‘I’, except LXI

3 Byte instruction: these instructions requires only three memory location for the
storing in the memory.

Ex: All instructions which are followed by 16 bit address.

Data transfer(13) Arithmetic(19) Logical(18) Machine

control(14)
MOV RD,RS ADD R ANA R PUSH Rp
MOV M,RS ADD M ANA M PUSH PSW
MOV RD,M ADI 8 Bit Data ANI 8 Bit Data POP Rp
MVI RD, 8 Bit Data ADC R ORA R POP PSW
MVI M, 8 Bit Data ADC M ORA M SPHL
LDA 16 Bit Address ACI 8 Bit Data ORI 8 Bit XTHL
Data
STA SUB R XRA R NOP
LHLD SUB M XRA M HLT
SHLD SUI 8 Bit Data XRI 8 Bit Data EI
LDAX RP SBB R CMP R DI
STAX RP SBB M CMP M RIM
LXI RP, 16 Bit Address SBI 8 Bit Data CPI 8 Bit Data SIM
XCHG INR R RAR IN
INR M RRC OUT
INR RP RAL
DCR R RLC
DCR M STC
DCX RP CMC
DAD RP CMA
DAA

8085 processor instruction set can be classified into 5 categories

Data transfer instruction--13

Arithmetic instructions--20

Logical instructions--19
Branch transfer instructions--8

Machine control instructions--14

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 13
Branching(8)
JUMP conditional/unconditional

CALL conditional/unconditional

RET conditional/unconditional

PCHL
RST-N

Jump conditional CALL conditional RET conditional RST

• JC • CC • RC • RST 0
• JNC • CNC • RNC • RST 1
• JP • CP • RP • RST 2
• JM • CM • RM • RST 3
• JPE • CPE • RPE • RST 4
• JPO • CPO • RPO • RST 5
• JZ • CZ • RZ • RST 6
• JNZ • CNZ • RNZ • RST 7

Data transfer instructions: They copy the data from a register (i/o or memory)
called source to another register (memory or i/o) called the destination.
Destination and the source registers are any of the 7 general purpose registers.
Memory to memory transfer is not available. Data transfer instructions will not
modify any flag after execution of the instructions.

MOV Rd,Rs: 1B-1M/C-4T

B= 000
OP-Code fetch machine cycle C= 001
D= 010
MOV B,C E= 011
H= 100
O1 000 001
L= 101
M= 110
A= 111
MOV M,Rs: the content of the register is transferred to the memory whose
address is specified in the HL register pair without losing the source content.

MOV M,A MOV R,M MOV A,M

01 110 111=77H 1B-2M/C-7T 01 111 110
1B-2M/C-7T OPCODE FETCH-4T
OP-Code fetch 4T MEMORY READ- 3T
Memory write 3T

MVI R, 8Bit data: this instruction directly copies the 8 bit data which is available
in the instruction itself in to the specified register.

MVI B,42H

2B-2M/C-7T

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 14
 Opcode fetch -4T

Memory read-3T

MVI B-0000 0110-06H

MVI C-0000 1110-0EH

MVI D-0001 0110-16H

MVI E-0001 1110-1EH

MVI H-0010 0110-26H

MVI L-0010 1110-2EH

MVI M-0011 0110-36H

MVI L-0011 1110-3EH

A=47H=0100 0111

B=51H=0101 0001

------------------------- S Z - AC - P - CY
A=98H=1001 1000 1 0 X 0 X 0 X 0

A=76H=0111 0110
S Z - AC - P - CY
((HL))=A2H=1010 0010 0 0 X 0 X 1 X 1

-----------------------------

A=118H=1 0001 1000

ACI 57H

A=26H=0010 0110
S Z - AC - P - CY
57H=0101 0111 0 0 X 0 X 1 X 0

------------------------

A=7E=0111 1110

A=XXH,, B=24H,C=98H,D=54H AND E=A1

MOV A,C // A=98H
ADD E // A=A+E 98+A1=139H
MOV L,A // L=39H

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 15
MOV A,B // A=24H
ADC D // A=CY+A+D=1+24+54=79H
MOV H,A //H=79H

S Z - AC - P - CY
0 0 X 0 X 0 X 0

CY=1,A=26H
ACI 57H

A=26H=0010 0110 S Z - AC - P - CY
57H=0101 0111 0 0 X 0 X 1 X 0

CY=1= 1
-------------------------
A=7EH=0111 1110
-----------------------
SUB C
A=37H,C=40H,
A=37H=0011 0111------0011 0111 S Z - AC - P - CY
-C=40H=0100 0000-----1100 0000 1 0 X 0 X 0 X 0

------------------------- ----------------
F7H 1111 0111=-9
A=40H
SUI 37H

S Z - AC - P - CY
A=40H=0100 0000-------0100 0000 0 0 X 0 X 1 X 1

- 37H=0011 0111-------1100 1001

------------------------- --------------
A=03H= 1 0000 1001
INR R/M (Increment register/Memory by 1): The specified register or memory
content is incremented by one and is stored in the same place. No flags are
modified. All the flags are modified except carry flag.
INR R 1B-1M/C-4T Opcode fetch -4T
INR M 1B-3M/C-10T Opcode fetch -4T
Memory read-3T
Memory Write-3T

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 16
Ex: B=25H
INR B S Z - AC - P - CY
0 0 X 0 X 0 X 0
B=25H=0010 0101
+1H=0000 0001
-------------------------
B=26H=0010 0110
Ex: HL=3000H
3000H 71H
71H=0111 0001

+1H=0000 0001
---------------------- S Z - AC - P - CY
0 0 X 0 X 1 X 0
((HL))=A1H=0111 0010
INX Rp: (Increment register pair by 1): The specified register pair content is
incremented by one and is stored in the same place. No flags are modified.
INX Rp 1B-1M/C-6T Opcode fetch -6T

BC=9FFFH
INX B
BC=9FFFFH=1001 1111 1111 1111
+1=0000 0000 0000 0001
-------------------------------------------------
BC=A000H= 1010 0000 0000 0000
DCR R/M (Decrement register/Memory by 1): The specified register or memory
content is decremented by one and is stored in the same place. No flags are
modified. All the flags are modified except carry flag.
DCR R 1B-1M/C-4T Opcode fetch -4T
DCR M 1B-3M/C-10T Opcode fetch -4T
Memory read-3T
Memory Write-3T
Ex: B=00H
DCR B
B=00H=0000 0000 S Z - AC - P - CY
1 0 X 0 X 1 X 0
-1H=1111 1111
-------------------------
B=FFH=1111 1111

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 17
Ex: HL=3000H

A0H=1010 0000 3000H

A0H
-1H=1111 1111
----------------------
((HL))=9FH=1 1001 1111 S Z - AC - P - CY
1 0 X 0 X 1 X 0

DCX Rp(Decrement register pair by 1): the specified register pair content is
decremented by one and is stored in the same place. no flags are modified.
DCX Rp 1B-1M/C-6T Opcode fetch -6T

Ex: DE=1FFFH
DCX D
DE=1FFFFH=0001 1111 1111 1111
-1=1111 1111 1111 1111
-------------------------------------------------
DE=1FFEH=1 0001 1111 1111 1110

DAD Rp: (Add register pair to HL) 16 bit addition: this instruction is used to
add the content of HL with the content of the register pair specified in the
instruction. If the result is greater than 16 bits, then the carry flag is set and no
other flags are modified. This instruction also used to multiply the HL content by
2.

DADRp 1B-3M/C-10T Opcode fetch -4T

Bus ideal-3T
Bus ideal-3T

Ex: HL=0000; SP=2050

DAD SP
HL=0000H=0000 0000 0000 0000
+SP=2050H=0010 0000 0101 0000
---------------------------------------------
HL=2050H=0010 0000 0101 0000
Ex: HL=0242
DAD H
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 18
 HL=0242H=0000 0010 0100 0010
+HL=0242H=0000 0010 0100 0010
---------------------------------------------
=0484H=0000 0100 1000 01000

DAA (Decimal Adjust Accumulator):

DAA 1B-1M/C-4T Opcode fetch -4T

Ex: BC=0012; HL=0039

DAD B //HL=HL+BC
DAA
HL=0039=0000 0000 0011 1001
BC=0012=0000 0000 0001 0010
-----------------------------------------
HL=0051=0000 0000 0100 1011
0110
--------------------------------------------
HL=0051=0000 0000 0101 0001

LOGICAL INSTRUCTIONS
µP is basically a programmable logic chip, hence it can perform all logical
functions through its instructions such as Rotate, AND,OR,EX-OR and NOT. All
the logic operations are performed in the accumulator.

1 AND 3 ANA,R
ANA,M
ANI,8 bit data
2 OR 3 ORA,R
ORA,M
ORI,8bit data
3 EX OR 3 XRA,R
XRA,M
XRI,8bit data
4 Rotate 4 RAR
RRC
RAL

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 19
 RLC
5 NOT 3 STC
CMC
CMA
6 Compare 3 CMP,R
CMP,M
CPI,8 bit data

Addressing modes:
• To perform any operation, we have to give the corresponding instructions to
the microprocessor.
• In each instruction, programmer has to specify 3 things:
– Operation to be performed.
– Address of source of data.
– Address of destination of result.
The method by which the address of source of data or the address of destination
of result is given in the instruction is called Addressing Modes. The term
addressing mode refers to the way in which the operand of the instruction is
specified.
Types of addressing modes:
i) Immediate Addressing Mode
ii)Register Addressing Mode
iii) Direct Addressing Mode
iv) Register Indirect Addressing Mode
v)Implicit Addressing Mode
i)Immediate Addressing Mode: In immediate addressing mode the source
operand is always data. If the data is 8-bit, then the instruction will be of 2 bytes,
if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B, 45 //B=45H
LXI H 3050 // HL=3050H
JMP address //jump to the operand address immediately

ii)Register Addressing Mode: In register addressing mode, the data to be

operated is available inside the register(s) and register(s) is(are) operands.
Therefore the operation is performed within various registers of the
microprocessor.
Examples: MOV A, B // A=B

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 20
 ADD B // A=A+B
INR A // A=A+1
iii)Direct Addressing Mode: In direct addressing mode, the data to be operated
is available inside a memory location and that memory location is directly
specified as an operand. The operand is directly available in the instruction itself.
Examples:
LDA 2050 // (A)=(2050)
LHLD address //(HL)=(contents of 16-bit memory location)
IN 35 //(read the data from port whose address is 35)
iv)Register Indirect Addressing Mode: In register indirect addressing mode, the
data to be operated is available inside a memory location and that memory
location is indirectly specified b a register pair.
Examples:
MOV A, M //(A)=((HL))
LDAX B //(A)=(BC)
LXIH 9570 //(HL)=9570
v)Implied/Implicit Addressing Mode: In implied/implicit addressing mode the
operand is hidden and the data to be operated is available in the instruction
itself.
Examples:
CMA //(A)=1’s complement of the accumulator A)
RRC //(rotate accumulator A right by one bit)
RLC //(rotate accumulator A left by one bit)
Interrupt structure:
When the microprocessor receives any interrupt signal from peripheral(s) which
are requesting its services, it stops its current program execution and program
control is transferred to a sub-routine by generating a CALL signal and after
executing sub-routine by generating RET signal again the program control is
transferred to the main program from where it had stopped.
Mainly in the microprocessor based system the interrupts are used for data
transfer between the peripheral and the microprocessor.
Interrupts can be classified into various categories based on different parameters:
i) Internally generate interrupts & externally generated interrupts
ii) Hardware & Software interrupts
iii) Maskable & non Maskable interrupts
iv) Vector and non vector interrupts
Internally generated interrupts: Interrupts arises due to the use of illegal
instructions or using of erroneous data. These are synchronous signals
Ex: register overflow, divide by zero, using of invalid operation

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 21
Externally generated interrupts: If the request is coming through hardware
pins they are called externally generated interrupts. These are asynchronous
signals
Ex: power supply failure, timing device signals
Hardware and Software Interrupts: When microprocessors receive interrupt
signals through pins (hardware) of microprocessor, they are known
as Hardware Interrupts. There are 5 Hardware Interrupts.
They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts are those which are inserted in between the program which
means these are nemonics of microprocessor. There are 8 software interrupts.
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
Non-Vectored Interrupts: the interrupts whose vector address is not yet
predefined. The interrupting device gives the address of sub-routine for these
interrupts.
Ex: INTR
Non-Vectored Interrupt address generation:

1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that
interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next
instruction on the stack and the program is transferred to ‘call’ location
(ISR Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt within
the program.
8. RET instruction at the end of the ISR allows the MP to retrieve the return
address from the stack and the program is transferred back to where the
program was interrupted.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 22
Vectored Interrupts: Which have fixed vector address (starting address of sub-
routine) and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE
Interrupt Decimal address Vector address
RST-0 0 0000H
RST-1 8 0008H
RST-2 16 0010H
RST-3 24 0018H
RST-4 32 0020H
TRAP 34 0024H
RST-5 40 0028H
RST-5.5 44 002CH
RST-6 48 0030H
RST-6.5 52 0034H
RST-7 56 0038H
RST-7.5 60 003CH
Maskable Interrupts: The interrupts which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-triggered, so
they can be disabled. Ex:INTR, RST 7.5, RST 6.5, RST 5.5

Fig 1.7: masking diagram

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 23
Non-Maskable Interrupts: The interrupts which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level
as well as e dge triggering and is used in critical power failure conditions.
Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are
enabled following the execution of next instruction followed by EI. No flags are
affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling
the interrupts. This instruction is necessary to enable the interrupts again
(except TRAP).
Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-
flop hence disabling all the interrupts. No flags are affected by this instruction.
Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST
7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output
data via the Serial Output Data (SOD) line. First the required value is loaded in
accumulator then SIM will take the bit pattern from it.

RIM: This instruction is used to read the status of the hardware interrupts (RST
7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 24
condition of the mask bits for the interrupts. It also reads the condition of SID
(Serial Input Data) bit on the microprocessor.

Interrupt priority

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 25
Module I the Processor 8086

 Register organization of 8086

 8086 architecture
 Signal description of 8086
 physical memory organization
 I/O addressing capability
 Minimum mode 8086 system and timings, maximum mode 8086system
and timings.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 26
8086 features: 8086 is a 16-bit Integer processor packed in DIP (Dual Inline
Packaged) IC in a 40 pin. 8086 has 14 internal registers, each of 16 bits or 2
Bytes wide. The size of the internal registers indicate how much information the
processor can operate on at a time and how it moves data around internally
within the chip, sometimes also referred to as the internal data bus.

8086 has four 16 bit general purpose registers AX, BX, CX and DX. Store
intermediate values during execution. Each of these has two 8 bit parts (higher
and lower).

Architecture: The internal architecture of Intel 8086 is divided into 2 units:

 Bus Interface Unit (BIU)

 Execution Unit (EU)

These are explained as following below.

Fig 2.1: Architecture of 8086

1. Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the
System Bus. It performs memory read, I/O read etc. to transfer the data between
memory and I/O devices.

BIU performs the following functions-

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 27
  It generates the 20 bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6 byte pre-fetch instruction queue (supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-
fetch queue and an Address Generation Circuit.

Instruction Pointer (IP):

 It is a 16 bit register. It holds offset of the next instructions in the Code

Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20 bit physical address of the Code
Segment.
 Address of the next instruction is calculated as CS x 10H + IP.

Example:

CS = 4321H IP = 1000H
Then CS x 10H = 43210H + offset = 53210H

This is the address of the instruction.

Segment Registers: To complete 1Mbyte memory is divided into 16 logical

segments. With Each segment contains 64Kbyte of memory. There are four
segment registers.

Code Segment register: CS register is a 16-bit register containing address of 64

KB segment with processor instructions. CS holds the base address for the
Code Segment. All programs are stored in the Code Segment and accessed
via the IP register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions. It is
used for addressing a memory location in the code segment of the memory, where
the executable program is stored.

Data Segment registers: Data segment (DS) register is a 16-bit register

containing address of 64KB segment with program data. DS holds the base
address for the Data Segment. By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is
located in the data segment. DS register can be changed directly using POP and
LDS instructions. It points to the data segment memory where the data is
resided.

Stack Segment register: Stack segment (SS) is a 16-bit register containing

address of 64KB segment with program stack i.e the base address for the Stack
Segment. By default, the processor assumes that all the data referenced by the
stack pointer (SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction. It is used for

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 28
addressing stack segment of memory. The stack segment is that segment of
memory, which is used to store stack data.

Extra Segment register: Extra segment (ES) register is a 16-bit register

containing address of 64KB segment, usually with program data. ES holds the
base address for the Extra Segment. By default, the processor assumes that the
DI register references the ES segment in string manipulation instructions. ES
register can be changed directly using POP and LES instructions. It also refers to
segment which essentially is another data segment of the memory. It also
contains data.

Address Generation Circuit:

 The BIU has a Physical Address Generation Circuit.

 It generates the 20 bit physical address using Segment and Offset
addresses using the formula:
 Physical Address = Segment Address x 10H + Offset Address

6 Byte Pre-fetch Queue:

 It is a 6 byte queue (FIFO).

 Fetching the next instruction (by BIU from CS) while executing the current
instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs.

2. The Execution Unit (EU):

Functions of EU

 Fetches instructions from the Queue in BIU, decodes and executes

arithmetic and logic operations using the ALU.
 Sends control signals for internal data transfer operations within the
microprocessor.
 Sends request signals to the BIU to access the external module.
 It operates with respect to T-states (clock cycles) and not machine cycles.

The components of the EU are

 General purpose registers(GPRs)

 ALU
 Special purpose registers(SPRs)
 Instruction Register and Instruction Decoder(IR)
 Flag/Status Register(FR)

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 29
Register organization:

Fig 2.2: Register Organization

General purpose registers (GPRs)

 AX register: It holds operands and results during multiplication and

division operations. Also an accumulator during String operations.
Accumulator register consists of two 8-bit registers AL and AH, which can
be combined together and used as a 16- bit register AX. AL in this case
contains the low-order byte of the word, and AH contains the high-order
byte. Accumulator can be used for I/O operations, rotate and string
manipulation.
 BX register: It holds the memory address (offset address) in indirect
addressing modes. This register is mainly used as a base register. It holds
the starting base location of a memory region within a data segment. It is
used as offset storage for forming physical address in case of certain
addressing mode.
 CX register: It holds count for instructions like loop, rotate, shift and
string operations. It is used as default counter or count register in case of
string and loop instructions.
 DX register: It is used with AX to hold 32 bit values during multiplication
and division. Data register can be used as a port number in I/O operations
and implicit operand or destination in case of few instructions. In integer
32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.

Special purpose registers (16-bit): The pointers contain within the particular
segments. The pointers IP, BP, SP usually contain offsets within the code, data
and stack segments respectively

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 30
  Stack Pointer: It is a 16-bit register to pointing to program stack in the
stack segment, which always Points the top of the stack. It is used during
the instructions like PUSH, POP, CALL, RET etc.
 Base Pointer: It is a 16-bit register pointing the data in stack segment. BP
can hold offset address of any location in the stack segment. It is used to
access random locations of the stack. BP register is used for based, based
indexed or register indirect addressing.
 Source Index: It is a 16-bit register. It holds offset address in Data
Segment during string operations.SI is used for indexed, based indexed and
register indirect addressing, as well as a source data addresses in string
manipulation instructions.
 Destination Index: It is a 16-bit register and is used for indexed, holds
offset address in Extra Segment during string operations. It is used in
based indexed and register indirect addressing, as well as a destination
data addresses in string manipulation instructions.

Instruction Register and Instruction Decoder (IR):

The EU fetches an opcode from the queue into the instruction register. The
instruction decoder decodes it and sends the information to the control circuit for
execution.

Flag/Status register: It is 16 bit register as shown in the fig., only 9 flags are
defined to change or recognize the state of the microprocessor.

Fig 2.3: flag register

Status flags: Status flags are updated after every arithmetic and logic operation.

1. carry flag(CF)
2. parity flag(PF)
3. auxiliary carry flag(AF)
4. zero flag(Z)
5. sign flag(S)
6. Overflow flag(OV)

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 31
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow

from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set
i.e. carry given by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is
used internally by the Processor to perform Binary to BCD conversion.

Parity Flag (PF): This flag is used to indicate the parity of result. If lower order
8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd
number of 1’s, the Parity flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else
it is reset.

Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB
bit. If the result of operation is negative, sign flag is set.

Control flags: The Control flags are used to control certain operations. Control
flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:

o trap flag(TF)
o interrupt flag(IF)
o direction flag(DF)

These flags can be set or reset using control instructions like CLC, STC, CLD,
STD, CLI, STI, etc.

Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set, program
can be run in single step mode.

Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the

maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled.
It can be set by executing instruction sit and can be cleared by executing CLI
instruction.

Direction Flag (DF): It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is reset,
the string bytes are accessed from lower memory address to higher memory
address.

Arithmetic Logic Unit (16 bit): Performs 8 and 16 bit arithmetic and logic
operations.

PIN Diagram:

The pin diagram of 8086 is shown in the fig. Intel 8086 is a 16-bit HMOS
microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply for its
operation. The 8086 uses 20-line address bus. It has a 16-line data bus. The 20
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 32
lines of the address bus operate in multiplexed mode. The 16-low order address
bus lines have been multiplexed with data and 4 high-order address bus lines have
been multiplexed with status signals.

Pins 16-39: It is a multiplexed low order Address/Data bus (AD0-AD15). These are
address bus. When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol
D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.

Pins 35-38(A16/S3, A17/S4, A18/S5, A19/S6): High order address bus multiplexed
with status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

Fig 2.4: 8086 pin diagram

Pin 34(BHE’/S7) : Bus High Enable/Status. During T1 it is low. It is used to

enable data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It is
multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 33
Pin 33(MN/MX’): 8086 will work in two different modes. They are
Minimum/Maximum modes. MN/MX’=0: maximum mode and MN/MX’=1:
minimum mode.

Pin 32(RD’): This is used for read operation. It is an output signal. It is active
when low.

Pins 30-31(RQ’/GT1′, RQ’/GT0′): Request/Grant. These pins are used by local

bus masters used to force the microprocessor to release the local bus at the end
of the microprocessor’s current bus cycle. Each of the pin is bi-directional.
RQ’/GT0′ have higher priority than RQ’/GT1′.

Pin 29( LOCK’) : It is an active low pin. It indicates that other system bus
masters have not been allowed to gain control of the system bus while LOCK’ is
active low (0). The LOCK signal will be active until the completion of the next
instruction.

Pins 26-28(S2, S1, S0): Status pins. These pins are active during T4, T1 and T2
states and is returned to passive state (1,1,1 during T3 or Tw (when ready is
inactive). These are used by the 8288 bus controller for generating all the memory
and I/O operation) access control signals. Any change in S2, S1, S0 during T4
indicates the beginning of a bus cycle.

S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive state

Pins 24-25(QS1,QS0) : Queue Status. These signals indicate the status of the
internal 8086 instruction queue according to the table shown below

Queue Status
Qs1 Qs0 Q status
0 0 Queue is ideal
0 1 1st byte of the opcode
1 0 Queue is empty
1 1 Subsequent byte of queue

Pin 23( TEST’) : This examined by a ‘WAIT’ instruction. If the TEST pin goes
low(0), execution will continue, else the processor remains in an idle state. The
input is internally synchronized during each of the clock cycle on leading edge of
the clock.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 34
Pin 22(READY) : This is the acknowledgement from the memory or slow device
that they have completed the data transfer. The signal made available by the
devices is synchronized by the 8284A clock generator to provide ready input to
the microprocessor. The signal is active high(1).

Pin 21(RESET): This pin requires the microprocessor to terminate its present
activity immediately. The signal must be active high (1) for at least four clock
cycles.

Pin 20( GND) : Ground

Pin 19( CLK) : Clock Input. The clock input provides the basic timing for
processing operation and bus control activity. Its an asymmetric square wave
with a 33% duty cycle.

Pin 18(INTR): Interrupt Request. This is triggered input. This is sampled during
the last clock cycles of each instruction for determining the availability of the
request. If any interrupt request is found pending, the processor enters the
interrupt acknowledge cycle. This can be internally masked after resulting the
interrupt enable flag. This signal is active high(1) and has been synchronized
internally.

Pin 17(NMI): Non maskable interrupt. This is an edge triggered input which
results in a type II interrupt. A subroutine is then vectored through an interrupt
vector lookup table which is located in the system memory. NMI is non-maskable
internally by software. A transition made from low(0) to high(1) initiates the
interrupt at the end of the current instruction. This input has been synchronized
internally.

Pin 40 (Vcc): 8086 microprocessor requires +5.0 V D.C with a supply voltage tolerance of
±10%. The 8086 uses a maximum supply current of 360 mA. Operate in ambient
temperatures of between 32° F and 180° F. 80C86 is CMOS version that requires only 10
mA of power supply current and function in temperature extremes of -40°F through
+225° F.

Minimum mode pins (24-31): Minimum mode operation of the 8086 is obtained by
connecting the MN/ MX’ pin directly to +5.0 V. Do not connect this pin to +5.0 V through
a pull-up register, or it will not function correctly.

Pin 24(INTA’): It is an Interrupt acknowledgement signal in response to the INTR

input pin. This pin is normally used to gate the interrupt vector number onto the
data bus in response to an interrupt request. It is active low (0) during T2, T3 and
Tw of each interrupt acknowledge cycle.

Pin 25(ALE) : Address Latch Enable. ALE is provided by the microprocessor to

latch the address into the 8282 or 8283 address latch. It is an active high(1)
pulse during T1 of any bus cycle. ALE signal is never floated, is always integer.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 35
Pin 26(DEN): Data enable. This pin is provided as an output enable for the
8286/8287 in a minimum system which uses transceiver. DEN is active low(0)
during each memory and input-output access and for INTA cycles.

Pin 27 (DT/R’): Data Transmit/Receive. This pin is required in minimum

systems that want to use an 8286 or 8287 data bus transceiver. The direction of
data flow is controlled through the transceiver.

Pin 28(M/IO’): The M/IO’ pin selects memory or I/O. This pin indicates that the
microprocessor address bus contains either a memory address or an I/O port
address. This pin is at its high-impedance state during a hold acknowledge.

Pin 29(WR’): The write line is a strobe that indicates that the 8086 is outputting
data to a memory or I/O device. During the time that WR’ the is a logic 0, the
data bus contains valid data for memory or I/O. This pin floats to a high
impedance during a hold acknowledge.

Pin 30-31(HOLD/HOLDA): HOLD indicates that another master has been

requesting a local bus .This is an active high (1). The microprocessor receiving the
HOLD request will issue HLDA (high) as an acknowledgement in the middle of a
T4 or T1 clock cycle.

Segmentation is the process in which the main memory of the computer is

logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the computer
system, so that the processor is able to fetch and execute the data from the
memory easily and fast.

Need for Segmentation –

The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.

 Code segment register (CS): is used for addressing memory location in the
code segment of the memory, where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory
where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory
which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to
store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so
as to access one of the 1MB memory locations. The four segment registers
actually contain the upper 16 bits of the starting addresses of the four memory
segments of 64 KB each with which the 8086 is working at that instant of time. A
segment is a logical unit of memory that may be up to 64 kilobytes long. Each
segment is made up of contiguous memory locations. It is an independent,
separately addressable unit. Starting address will always be changing. It will not
be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time.
However, it works only with four 64KB segments within the whole 1MB memory.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 36
Below is the one way of positioning four 64KB segments within the 1M byte
memory space of an 8086.

Types of Segmentation –

1. Overlapping Segment – A segment starts at a particular address and its

maximum size can go up to 64kilobytes. But if another segment starts
along with this 64kilobytes location of the first segment, then the two are
said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and
its maximum size can go up to 64kilobytes. But if another segment starts
before this 64kilobytes location of the first segment, then the two segments
are said to be Non-Overlapped Segment.

Rules of Segmentation Segmentation process follows some rules as follows:

 The starting address of a segment should be such that it can be evenly

divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64
kB.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 37
 Advantages of the Segmentation The main advantages of segmentation
are as follows:

o It provides a powerful memory management mechanism.

o Data related or stack related operations can be performed in different
segments.
o Code related operation can be done in separate code segments.
o It allows to processes to easily share data.
o It allows to extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an addressing
capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.
o It is possible to enhance the memory size of code data or stack
segments beyond 64 KB by allotting more than one segment for each
area.

Physical Memory organization: 8086μP has 20 bit address bus hence it can
address up to 220≈ 1M memory space (00000H-FFFFFH). This is divided in to two
independent banks of 512 KB size each as shown in the fig. Data bytes associated
with an even address (00000, 00002..., FFFFE) reside in the low bank (even
bank). Data bytes associated with an odd addresses (00001, 00003, ....., FFFFF)
reside in the high bank (odd bank). Address bits A1 through A19 are connected to
both the banks to select the accessed memory location. BLE’ (Bus low enable) A0
& BHE’ (Bus high enable) signals are used as bank-select signals for lower and
upper banks respectively. 8086μP has 16 data line to carry the data even though
each memory location holds only 1byte of data. Hence, the even bank transfers
data bytes over D0 -D7 data lines, while the odd bank uses D8-D15 for transfer the
data.

Fig 2.5: Memory organization

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 38
To read/write a byte data, 1M/C is sufficient whereas for a word data transfer, it
may take either 1or 2 bus cycles depending on the starting address of the word.
This is illustrated in table below.

Address Data type BHE’ BLE’(A0) M/C

00000(even) Byte 1 0 1
00001(odd) Byte 0 1 1
00000(even) word 0 0 1
00001(odd) word 0/1 1/0 2

Case 1: To read/write a byte from /into a memory location in the even bank with
the starting address is 00000H. BHE’&A0=10, will select the even bank and
deactivates the odd bank, and a byte will be transferred through D0 -D7 data
lines.

Ex: MOV AH, DS; byte PTR (00000H)

Case 2: To read/write a byte from /into a memory location in the odd bank with
the starting address is 00001H. BHE’&A0=01, will select the odd bank and
disable the even bank, and a byte will be transferred through D8 –D15 data lines.

Ex: MOV AL, DS; byte PTR (00001H)

Case 3: To read/write a word from/into the memory with the starting address is
00000(even). Since A0=0, even bank has selected, and μP will generate BHE’=0,
hence high lower bank also selected. As both the banks have individual data line,
with in 1st bus cycle a word can be transferred.

MOV AX, DS; Word PTR (00000H)

Case 4: To read/write a word from/into the memory with the starting address is
00001(odd). Initially A0=1 hence even bank is disabled, at the same time μP will
grant BHE’=0 signal, hence the odd bank is enabled for the 1st M/C and a byte
will be transferred through D8 –D15 data lines. During the 2nd M/C, μP will send
the address as 00002H, hence A0=0, and processor will generate BHE’ signal as
high, hence even bank selected, now the byte data transfer will be done through
D0 –D7.

Ex: MOV AX, DS; word PTR (00001H)

Timing Diagram:

Fig shows that the signal activities on the 8086 µP buses during read and write
operations.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 39
 Fig. Timing diagram of 8086

During 1st T state of every M/C, the ALE is high to enable the address latches.
After the address passed through latches, 8086 will bring the ALE to low again to
latch the address on the O/Ps of the latches. After the address has latched, µP
removes the address information from AD0-AD15 and outputs desired data on
the data bus. Then it asserts the WR’=0.

If the system is large enough to need buffers on the DB, then DT/R’ will be
connected to the direction input on the buffers. During a write cycle, 8086 will
assert DT/R’ high to put the buffers in the transmit mode. When 8086 asserts
DEN’ low to enable the buffers, data O/P from 86 will pass through buffers to the
addressed port or memory.

Write M/C: During 1st T state, the signal M/IO’ is Low if the write address is
port or High if the write address is memory. Then 8086 outputs BHE’ and the
address, that it will be writing to on AD0-AD19. When the writing is IO port then
A16-A19 will be low.

Modes of Operation: 8086 µP will operate in two modes of operation

 Minimum mode of Operation

 Maximum mode of Operation

Minimum mode of operation: Minimum mode operation is selected with

MN/MX’=1. It is the least expensive way to operate the 8086 microprocessor,
because all the control signals for the memory and I/O are generated by the μP
itself. These control signals are identical to those of 8085A. In 8085, the
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 40
minimum mode allows 8-bit peripherals to be used with the 8086 without any
special considerations. 8086 will take 4T states for IOR, IOW, MEMR and MEMW
machine cycles. µP will provide the address information in AD0-AD15 & A16-A19
line.

Fig 2.6: 8086 minimum mode of operation

Read cycle: ALE makes a transition from low to high during 1st T state of every
machine cycle and then goes from high to low. With the trailing edge of the ALE
the address information is latched at the o/p of the latch and holds throughout
the machine cycle. M/IO’ and DT/R’ settle down accordingly at the beginning of
M/C and remains as it is throughout the M/C. In read M/C, during T2 the RD’
and DEN’ signals makes transition from high to low and is continued throughout
the M/C. During the T3, the µP just waits and in T4 it will draws RD’ and DEN’
signals and whatever the data in the data bus takes it is valid data.

Fig.2.7: Read Machine cycle

Write cycle: ALE makes a transition from low to high during 1st T state of every
machine cycle and then goes from high to low. With the trailing edge of the ALE
the address information is latched at the o/p of the latch and holds throughout
the machine cycle. M/IO’ signal will settle down and DT/R’ makes a transition

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 41
from low to high accordingly at the beginning of the M/C and unchanged
throughout the M/C. In write M/C, during T2 the WR’ and DEN’ make transition
from high to low as they are active low signals. During the T3 µP just waits and
in T4 it will draws WR’ and DEN’ signals and whatever the data in the data bus
takes it is valid data.

Fig 2.8: write machine cycle

If ready pin is low somewhere before end of T2 then at the end of T2 it will be
sampled by the processor and after T3 instead of generating T4 state, the
processor generate one wait state. During the wait state the status of AB, DB and
CBs remains unchanged and the READY pin is sampled by the processor. If it is
still low one more wait state is introduced. This process will be continued until
the READY pin is high. Once the READY pin is high the processor will generate
the T4 T state and ends the machine cycle.

Maximum mode of operation: This mode selects with MN/MX’ pin=0. Maximum
mode is used only when the system contains external coprocessors such as 8087
arithmetic coprocessor and 8089 I/O coprocessor. In this mode, the host
processor and the coprocessors will share the common property of system bus.
Both 8087/8089 has their own instruction set and capable of performing complex
arithmetic operations upon floating point data as well as several I/O operations.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 42
 Fig.2.9: Maximum mode of operation

The program for 8086 and instructions of 8087/8089 can stay together in the
main memory. When it executed by a single processor in ALP, the 8087
instruction is recognized as if the first letter is F. 8086 fetches the whole program
and bytes containing op-codes, addressing mode, address/data reaches the
instruction queue inside the processor. The same type also reaches the queue of
8087. If the particular instruction is for 8086, then 8087 will treat that
instruction as NOP for him and vice versa. Max. mode of operation differs from
the Min. mode in the way some of the control signals must be generated
externally.

The pins 24-31 will have the functions described by the mnemonics next to the
pins. In max mode, 8288 (external bus controller to provide the signals eliminated
from the 8086 by the maximum mode operation, as there are not enough for bus
control during maximum mode) is required to translate the control signals for
system which has two or more µPs sharing the same bus. This additional
circuitry converts the status signals (S2’-S0’) into the I/O and memory transfer
signals as shown in the table. Also generates the control signals required to direct
the data flow and for controlling 8282 octal latches are used to demultiplex the
address signals and 8286 bidirectional transceivers are used to buffer the data
bus so that it can drive a boardful of devices as shown in fig.

Table

S2’S1’ S0’ CPU cycle 8288 command

000 Interrupt Acknowledgment INTA’
001 I/O read IORC’
010 I/O write IOWC’ AIOWC’
011 Halt none
100 Fetch MRDC’
101 Memory read MRDC’
110 Memory write MWTC’ AMWC’
111 Passive none

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 43
Read cycle: Maximum mode is a multiprocessor mode, where the status signals
S2’-S0’ shows which system is activated and which system is deactivated. These
status signal will be active for the first 2 T states and deactivated 2 T states and
again

Fig 2.10: memory read bus cycle

Write cycle: ALE is high for 1st T state, the status signals S2’-S0’ shows which
system is activated and which system is deactivated. These status signal will be
active for the first 2 T states and deactivated 2 T states and again. DT/R’ is high
for data transfer. During 1st T state, the signal M/IO’ is Low if the write address
is port or High if the write address is memory. Then 8086 outputs BHE’ and the
address, that it will be writing to on AD0-AD19. When the writing is IO port then
A16-A19 will be low.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 44
8288 bus controller: Fig illustrates the block diagram and pin-out of the 8288
bus controller. The control bus developed by the 8288 bus controller contains
separate signals for I/O (IORC’ and IOWC’) and memory ( MRDC’ and MWTC’).
Also contains advanced memory (AMWC) and I/O (AIOWC’) write strobes, and
INTA’ signal. These signals replace the minimum mode ALE,WR’,IO/M’,
DT/R’,DEN’, and INTA’, which are lost when the 8086 microprocessors are
operated in the maximum mode.

Fig 2.11: 8288 block diagram

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 45
S2-S0 Status inputs are connected to the status output pins on the
8086 microprocessor. These three signals are decoded to
generate the timing signals for the system
CLK The clock input provides internal timing and must be
connected to the CLK output pin of the 8284A clock
generator.
ALE The address latch enable output is used to demultiplex the
address/data bus
DEN The data bus enable pin controls the bidirectional data bus
buffers in the system. This is an active high output pin that
is the opposite polarity from the DEN’ signal found on the
microprocessor when operated in the minimum mode.
DT/R’ The data transmit/receive signal is output by the 8288 to
control the direction of the bidirectional data bus buffers.
AIOWC’/AMWC’ Advance I/O Write Command/Advance Memory
Write Command. These signals are similar to IOWC
and MWTC except that they are activated one clock
pulse earlier. This gives slow interfaces an extra clock
cycle to prepare to input the data.
AEN’ IOB CEN The control enable input enables the command output pins
on the 8288.

These pins are used in multiprocessor system. With a

single processor in the system, AEN and IOB are
grounded and CEN is tied high. AEN causes the 8288 to
enable the memory control signals. IOB (I/O bus mode)
signal selects either the I/O bus mode or system bus
mode operation. CEN (control enable) input enables the
command output pins on the 8288.
MCE/PDEN’ It controls the mode of operation of 8259. It selects
(Master Cascade cascade operation for 8259 (interrupt controller) if IOB
Enable/Peripheral signal is grounded and enables the I/O bus transceivers
Data Enable) : if IOB is tied high.
MRDC (Memory It instructs the memory to put the contents of the
Read Command) : addressed location on the data bus.
MWTC (Memory : It instructs the memory to accept the data on the data
Write Command) bus and load the data into the addressed memory
location.
IORC (I/O Read It instructs an I/O device to put the data contained in
Command) the addressed port on the data bus.
IOWC (I/0 Write It instructs an I/O device to accept the data on the data
Command) bus and load the data into the addressed port.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 46
 Module 3: Instruction set and Programming

 Machine language instruction format,

 Addressing modes of 8086,

 Instruction set of 8086,

 Assembler directives and example programs (assembly programs).

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 47
8086 INSTRUCTION SET

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

Data Transfer Instructions: These instructions are used to transfer the data from
the source operand to the destination operand. Following are the list of
instructions under this group −

Instruction to transfer a word

 MOV − Used to copy the byte or word from the provided source to the
provided destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the
provided port.

Instructions to transfer the address

 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the
memory
 LES − Used to load ES register and other provided register from the
memory.

Instructions to transfer flag registers

 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 48
Arithmetic Instructions: These instructions are used to perform arithmetic
operations like addition, subtraction, multiplication, division, etc.

Instructions to perform addition

 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s
complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

 DIV − Used to divide the unsigned word by byte or unsigned double word
by word.
 IDIV − Used to divide the signed word by byte or signed double word by
word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of
the lower byte.
 CWD − Used to fill the upper word of the double word with the sign bit of
the lower word.

Bit Manipulation Instructions: These instructions are used to perform

operations where data bits are involved, i.e. operations like logical, shift, etc.

Instructions to perform logical operation

 NOT − Used to invert each bit of a byte or word.

 AND − Used for adding each bit in a byte/word with the corresponding bit
in another byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit
in another byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a
byte/word with the corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 49
Instructions to perform shift operations

 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in
LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in
MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old
MSB into the new MSB.

Instructions to perform rotate operations

 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB
and to Carry Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB
and to Carry Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF
and CF to MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and
CF to LSB.

String Instructions: String is a group of bytes/words and their memory is

always allocated in a sequential order.

 REP − Used to repeat the given instruction till CX ≠ 0.

 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag
ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero
flag ZF = 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to
another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to
the provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the
provided memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a
byte in AL or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string
word into AX.

Program Execution Transfer Instructions (Branch and Loop Instructions): These

instructions are used to transfer/branch the instructions during an execution. It
includes the following instructions −

Instructions to transfer the instruction during an execution without any

condition −

 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next
instruction.

Instructions to transfer the instruction during an execution with some conditions

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 50
  JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction
satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction
satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction
satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction
satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

Processor Control Instructions: These instructions are used to control the

processor action by setting/resetting the flag values.

 STC − Used to set carry flag CF to 1

 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions: These instructions are used to execute the given
instructions for number of times.

 LOOP − Used to loop a group of instructions until the condition satisfies,

i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1
& CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF
= 0 & CX = 0
 JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions: These instructions are used to call the interrupt during
program execution.

 INT − Used to interrupt the program during execution and calling service
specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 51
DATA TRANSFER INSTRUCTIONS
MOV – MOV Destination, Source

It Copies a word/a byte from a specified source to a specified destination. The

destination can be a register or a memory location. The source can be a
register/a memory location/an immediate number. The source and destination
cannot both be memory locations. They must both be of the same type (bytes or
words). MOV instruction does not affect any flag.

 MOV CX, 037AH Put immediate number 037AH to CX

 MOV BL, [437AH] Copy byte in DS at offset 437AH to BL
 MOV AX, BX Copy content of register BX to AX
 MOV DL, [BX] Copy byte from memory at [BX] to DL
 MOV DS, BX Copy word from BX to DS register
 MOV RESULT [BP], AX Copy AX to two memory locations;
AL to the first location, AH to the second;
EA of the first memory location is sum of the
displacement represented by RESULTS and
content of BP.
Physical address = EA + SS.
 MOV ES: RESULTS [BP], AX Same as the above instruction, but physical
address = EA + ES, because of the segment override prefix ES

XCHG – XCHG Destination, Source: Exchanges the content of a register with

the content of another register or with the content of memory location(s). It
cannot directly exchange the content of two memory locations. The source and
destination must both be of the same type (bytes or words). The segment registers
cannot be used in this instruction. This instruction does not affect any flag.

 XCHG AX, DX Exchange word in AX with word in DX

 XCHG BL, CH Exchange byte in BL with byte in CH
 XCHG AL, PRICES [BX] Exchange byte in AL with byte in memory at
EA = PRICE [BX] in DS.

LEA – LEA Register, Source: Determines the offset of the variable or memory
location named as the source and puts this offset in the indicated 16-bit register.
LEA does not affect any flag.

 LEA BX, PRICES Load BX with offset of PRICE in DS

 LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS
 LEA CX, [BX][DI] Load CX with EA = [BX] + [DI]

LDS – LDS Register, Memory address of the first word: Loads new values into
the specified register and into the DS register from four successive memory
locations. The word from two memory locations is copied into the specified
register and the word from the next two memory locations is copied into the DS
registers. LDS does not affect any flag.

 LDS BX, [4326] Copy content of memory at displacement 4326H in DS to

BL, content of 4327H to BH. Copy content at displacement of
4328H and 4329H in DS to DS register.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 52
 LDS SI, SPTR Copy content of memory at displacement SPTR and SPTR + 1in
DS to SI register. Copy content of memory at displacements
SPTR + 2 and SPTR + 3 in DS to DS register. DS: SI now
points at start of the desired string.

LES – LES Register, Memory address of the first word: Loads new values into
the specified register and into the ES register from four successive memory
locations. The word from the first two memory locations is copied into the
specified register, and the word from the next two memory locations is copied into
the ES register. LES does not affect any flag.

 LES BX, [789AH] Copy content of memory at displacement 789AH in DS to BL,

content of 789BH to BH, content of memory at displacement
789CH and 789DH in DS is copied to ES register.
 LES DI, [BX] Copy content of memory at offset [BX] and offset [BX] + 1 in
DS to DI register. Copy content of memory at offset [BX] +
2 and [BX] + 3 to ES register.

ARITHMETIC INSTRUCTIONS

ADD – ADD Destination, Source

ADC – ADC Destination, Source

These instructions add a number from a source to a number in a destination

and place the result in the specified destination. The ADC also adds the status
of the carry flag to the above result. The source may be an immediate number/
a register/a memory location. The destination may be a register/a memory
location. The source and the destination in an instruction cannot both be
memory type. The source and the destination must be of the same type (bytes/
words). To add a byte to a word, you must copy the byte to a word location and
fill the upper byte of the word with 0’s before adding. Flags affected: AF, CF,
OF, SF, ZF.

 ADD AL, 74H //Add immediate number 74H to content of AL. Result in AL
 ADC CL, BL //Add content of BL plus carry status to content of CL
 ADD DX, BX //Add content of BX to content of DX
 ADD DX, [SI] //Add word from memory at offset [SI] in DS to content of DX
 ADC AL, PRICES [BX] //Add byte from effective address PRICES [BX] plus
carry status to content of AL
 ADD AL, PRICES [BX] //Add content of memory at EA address PRICES [BX]
to AL
SUB – SUB Destination, Source

SBB – SBB Destination, Source

These instructions subtract the number in a source from the number in a

destination and place the result in the destination. The SBB instruction also
subtracts the content of carry flag from the destination. The source may be an
immediate number/a register/memory location. The destination also be a
register/a memory location. However, the source and the destination cannot
both be memory location. The source and the destination must both be of the
same type (bytes or words). To subtract a byte from a word, you must first
move the byte to a word location such as a 16-bit register and fill the upper
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 53
 byte of the word with 0’s. Flags affected: AF, CF, OF, PF, SF, ZF.

 SUB CX, BX //CX=CX – BX

 SBB CH, AL //CH=CH-AL-CF
 SUB AX, 3427H //AX=AX-3427H
 SBB BX, [3427H] //BX-[DS*10H+3427H]- CF
 SUB PRICES [BX], 04H //Subtract 04 from byte at effective address
PRICES [BX], if PRICES is declared with DB;
Subtract 04 from word at effective address
PRICES [BX], if it is declared with DW.
 SBB CX, TABLE [BX]//Subtract word from effective address TABLE [BX]
and status of CF from CX.
 SBB TABLE [BX], CX //Subtract CX and status of CF from word in
memory at effective address TABLE [BX].

MUL–MUL Source: This instruction multiplies an unsigned byte/word in source

with an unsigned byte/word in AL/AX register. Source can be a register/a
memory location. When a byte is multiplied by the AL, the result (product) will be
in AX. When a word is multiplied by the content of AX, the result will be in DX
and AX. If the most significant byte of a 16-bit result or the most significant word
of a 32-bit result is 0, CF =OF=0. AF, PF, SF and ZF are undefined after a MUL
instruction.

To multiply a byte with a word, first move the byte to a word location such as
an extended register and fill the upper byte of the word with all 0’s. Cannot use
the CBW instruction for this, because the CBW instruction fills the upper byte
with copies of the most significant bit of the lower byte

 MUL BH AX ←(AL )* (BH)

 MUL CX (DX) (AX) ←(AX )* (CX)
 MUL BYTE PTR [BX] Multiply AL with byte in DS pointed to by [BX]
 MUL FACTOR [BX] Multiply AL with byte at ES FACTOR [BX], if it
is declared as type byte with DB. Multiply AX
with word at effective address FACTOR [BX], if
it is declared as type word with DW.
 MOV AX, MCAND_16 Load 16-bit multiplicand into AX
 MOV CL, MPLIER_8 Load 8-bit multiplier into CL
MOV CH, 00H Set upper byte of CX to all 0’s
 MUL CX (DX) (AX) ←(AX )* (CX)

IMUL – IMUL Source: Multiplies a signed byte/word from a source with a signed
byte/word in AL/AX. Source can be a register/a memory location. When a byte
from source is multiplied with content of AL, the signed result will be in AX.
When a source word is multiplied by AX, the result will be in DX and AX.

If the magnitude of the product does not require all the bits of the destination, the
unused byte / word will be filled with copies of the sign bit. If the upper byte of a
16-bit result or the upper word of a 32-bit result contains only copies of the sign
bit (all 0’s or all 1’s), then CF=OF=0; If it contains a part of the product,
CF=OF=1. AF, PF, SF and ZF are undefined after IMUL.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 54
 To multiply a signed byte with a signed word, first move the byte into a word
location and fill the upper byte of the word with copies of the sign bit. If move
the byte into AL, use the CBW instruction.

 IMUL BH AX ←(AL )* (BH)

 IMUL AX (DX) (AX) ←(AX )* (AX)
 MOV CX, MULTIPLIER Load signed word in CX
MOV AL, MULTIPLICAND Load signed byte in AL
CBW Extend sign of AL into AH

IMUL CX Multiply CX with AX; Result in DX and AX

DIV – DIV Source: Divide an unsigned word by a byte or to divide an unsigned

double word (32 bits) by a word. When a word is divided by a byte, word must be
in the AX register. The divisor can be in a register/ a memory location. After the
division, AL holds 8-bit quotient, and AH holds 8-bit remainder. When a double
word is divided by a word, the most significant word of the double word must be
in DX, and the least significant word must be in AX. After the division, AX
contains the 16-bit quotient and DX contains the 16-bit remainder. If an attempt
is made to divide by 0/if the quotient is too large to fit in the destination (greater
than FFH / FFFFH), then 8086 generates a type 0 interrupt. All flags are
undefined after DIV instruction.

To divide a byte by a byte, first put the dividend byte in AL and fill AH with all
0’s. Likewise, to divide a word by another word, then put the dividend word in
AX and fill DX with all 0’s.

 DIV BL //Divide word in AX by byte in BL; Quotient in AL, remainder in AH

 DIV CX //Divide down word in DX and AX by word in CX; Quotient in AX,
and remainder in DX.
 DIV SCALE [BX] AX / (byte at effective address SCALE [BX]) if SCALE
[BX] is of type byte; or (DX and AX) / (word at effective
address SCALE[BX] if SCALE[BX] is of type word

IDIV – IDIV Source: Used to divide a signed word by a signed byte, or to divide a
signed double word by a signed word. When dividing a signed word by a signed
byte, the word must be in AX register.
The divisor can be in an 8-bit register/ a memory location. After the division, AL
will contain the signed quotient, and AH will contain the signed remainder. The
sign of the remainder will be the same as the sign of the dividend. If an attempt is
made to divide by 0, the quotient is greater than 127 (7FH) or less than –127
(81H), the 8086 will automatically generate a type 0 interrupt.

When dividing a signed double word by a signed word, the most significant
word of the dividend (numerator) must be in the DX register, and the least
significant word of the dividend must be in the AX register. The divisor can be
in any other 16-bit register or memory location. After the division, AX will
contain a signed 16-bit quotient, and DX will contain a signed 16-bit
remainder. The sign of the remainder will be the same as the sign of the
dividend. Again, if an attempt is made to divide by 0, the quotient is greater
than +32,767 (7FFFH) or less than –32,767 (8001H), the 8086 will

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 55
 automatically generate a type 0 interrupt. All flags are undefined after an IDIV.
To divide a signed byte by a signed byte, first put the dividend byte in AL and
sign-extend AL into AH. The CBW instruction can be used for this purpose. To
divide a signed word by a signed word, put the dividend word in AX and extend
the sign of AX to all the bits of DX. The CWD instruction can be used for this
purpose.

 IDIV BL //Signed word in AX/signed byte in BL

 IDIV BP //Signed double word in DX and AX/signed word in BP
 IDIV BYTE PTR [BX] //AX / byte at offset [BX] in DS

INC – INC Destination: The INC instruction adds 1 to a specified register or to a

memory location. AF, OF, PF, SF, and ZF are updated, but CF is not affected.
This means that if an 8-bit destination containing FFH or a 16-bit destination
containing FFFFH is incremented, the result will be all 0’s with no carry.

 INC BL //Add 1 to contains of BL register

 INC CX //Add 1 to contains of CX register
 INC BYTE PTR [BX] // Increment byte in data segment at offset contained
in BX.
 INC WORD PTR [BX] //Increment the word at offset of [BX] and [BX + 1] in
the data segment.
 INC TEMP //Increment byte or word named TEMP in the data segment
Increment byte if MAX_TEMP declared with DB.
Increment word if MAX_TEMP is declared with DW.
 INC PRICES [BX] //Increment element pointed to by [BX] in array PRICES.
Increment a word if PRICES is declared as an array of
words; Increment a byte if PRICES is declared as an array
of bytes.

DEC – DEC Destination: Subtracts 1 from the destination word/byte. The

destination can be a register/ a memory location. AF, OF, SF, PF, and ZF are
updated, but CF is not affected. This means that if an 8-bit destination
containing 00H or a 16-bit destination containing 0000H is decremented, the
result will be FFH or FFFFH with no carry (borrow).

 DEC CL //Subtract 1 from content of CL register

 DEC BP //Subtract 1 from content of BP register
 DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX] in DS.
 DEC WORD PTR [BP] Subtract 1 from a word at offset [BP] in SS.
 DEC COUNT //Subtract 1 from byte or word named COUNT in DS.
Decrement a byte if COUNT is declared with a DB;
Decrement a word if COUNT is declared with a DW.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 56
DAA (DECIMAL ADJUST AFTER BCD ADDITION): Used to make sure the result
of adding two packed BCD numbers is adjusted to be a legal BCD number. The
result of the addition must be in AL for DAA to work correctly. If the lower nibble
in AL after an addition is greater than 9 or AF was set by the addition, then the
DAA instruction will add 6 to the lower nibble in AL. If the result in the upper
nibble of AL in now greater than 9 or if the carry flag was set by the addition or
correction, then the DAA instruction will add 60H to AL.

 Let AL = 59 BCD, and BL = 35 BCD

ADD AL, BL AL = 8EH; lower nibble > 9, add 06H to AL
DAA AL = 94 BCD, CF = 0
 Let AL = 88 BCD, and BL = 49 BCD
ADD AL, BL AL = D1H; AF = 1, add 06H to AL
DAA AL = D7H; upper nibble > 9, add
60H to AL AL = 37 BCD, CF = 1
The DAA instruction updates AF, CF, SF, PF, and ZF; but OF is undefined.

DAS (DECIMAL ADJUST AFTER BCD SUBTRACTION): Used after subtracting one
packed BCD number from another packed BCD number, to make sure the result
is correct packed BCD. The result of the subtraction must be in AL for DAS to
work correctly. If the lower nibble in AL after a subtraction is greater than 9 or
the AF was set by the subtraction, then the DAS instruction will subtract 6 from
the lower nibble AL. If the result in the upper nibble is now greater than 9 or if
the carry flag was set, the DAS instruction will subtract 60 from AL.

 Let AL = 86 BCD, and BH = 57 BCD

SUB AL, BH //AL = 2FH; lower nibble > 9, subtract 06H from AL AL = 29
BCD, CF = 0
 Let AL = 49 BCD, and BH = 72 BCD
SUB AL, BH //AL = D7H; upper nibble > 9, subtract 60H from AL
DAS AL = 77 BCD, CF = 1 (borrow is needed) The DAS instruction updates
AF, CF, SF, PF, and ZF; but OF is undefined.

CBW (CONVERT SIGNED BYTE TO SIGNED WORD): Copies the sign bit of the
byte in AL to all the bits in AH. AH is then said to be the sign extension of AL.
CBW does not affect any flag.

Let AX = 00000000 10011011 (–155 decimal)

 CBW //Convert signed byte in AL to signed word in AX AX =

11111111 10011011 (–155 decimal)

CWD (CONVERT SIGNED WORD TO SIGNED DOUBLE WORD): This instruction

copies the sign bit of a word in AX to all the bits of the DX register. In other
words, it extends the sign of AX into all of DX. CWD affects no flags.

Let DX = 00000000 00000000, and AX = 11110000 11000111 (–3897 decimal)

 CWD //Convert signed word in AX to signed double word in DX:AX DX =

11111111 11111111 AX = 11110000 11000111 (–3897 decimal)

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 57
AAA (ASCII ADJUST FOR ADDITION): Numerical data coming into a computer
from a terminal is usually in ASCII code. In this code, the numbers 0 to 9 are
represented by the ASCII codes 30H to 39H. The 8086 allows to add the ASCII
codes for two decimal digits without masking off the “3” in the upper nibble of
each. After the addition, the AAA instruction is used to make sure the result is
the correct unpacked BCD.

 Let AL = 0011 0101 (ASCII 5), and BL = 0011 1001 (ASCII 9)

ADD AL, BL AL = 0110 1110 (6EH, which is incorrect BCD)
AAA AL = 0000 0100 (unpacked BCD 4)
CF = 1 indicates answer is 14 decimal.

The AAA instruction works only on the AL register. The AAA instruction
updates AF and CF; but OF, PF, SF and ZF are left undefined.

AAS (ASCII ADJUST FOR SUBTRACTION): Numerical data coming into a

computer from a terminal is usually in an ASCII code. In this code the numbers 0
to 9 are represented by the ASCII codes 30H to 39H. The 8086 allows you to
subtract the ASCII codes for two decimal digits without masking the “3” in the
upper nibble of each. The AAS instruction is then used to make sure the result is
the correct unpacked BCD.

 Let AL = 00111001 (39H or ASCII 9), and BL = 00110101

(35H or ASCII 5) SUB AL, BL AL = 00000100 (BCD 04),
and CF = 0
AAS AL = 00000100 (BCD 04), and CF = 0 (no borrow
required)
 Let AL = 00110101 (35H or ASCII 5), and BL = 00111001 (39H or ASCII 9)
SUB AL, BL AL = 11111100 (– 4 in 2’s complement form), and
CF = 1
AAS AL = 00000100 (BCD 06), and CF = 1 (borrow
required)

The AAS instruction works only on the AL register. It updates ZF and CF; but
OF, PF, SF, AF are left undefined.

AAM (BCD ADJUST AFTER MULTIPLY): Before you can multiply two ASCII
digits, you must first mask the upper 4 bit of each. This leaves unpacked BCD
(one BCD digit per byte) in each byte. After the two unpacked BCD digits are
multiplied, the AAM instruction is used to adjust the product to two unpacked
BCD digits in AX. AAM works only after the multiplication of two unpacked BCD
bytes, and it works only the operand in AL. AAM updates PF, SF and ZF but AF;
CF and OF are left undefined.

 Let AL = 00000101 (unpacked BCD 5), and BH = 00001001

(unpacked BCD 9) MUL BH AL x BH: AX = 00000000
00101101 = 002DH
AAM AX = 00000100 00000101 = 0405H (unpacked
BCD for 45)

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 58
AAD (BCD-TO-BINARY CONVERT BEFORE DIVISION)

AAD converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two
unpacked BCD digits in AX by an unpacked BCD byte. After the BCD division,
AL will contain the unpacked BCD quotient and AH will contain the unpacked
BCD remainder. AAD updates PF, SF and ZF; AF, CF and OF are left
undefined.

Let AX = 0607 (unpacked BCD for 67 decimal), and CH = 09H

AAD AX = 0043 (43H = 67 decimal)

DIV CH //AL = 07; AH = 04; Flags undefined after DIV If an attempt is

made to divide by 0, the 8086 will generate a type 0 interrupt.

LOGICAL INSTRUCTIONS

AND – AND Destination, Source: This instruction ANDs each bit in a source
byte or word with the same numbered bit in a destination byte or word. The
result is put in the specified destination. The content of the specified source is
not changed.

The source can be an immediate number/ content of a register/or the content

of a memory location. The destination can be a register/a memory location.
CF=OF= 0 after AND. PF, SF, and ZF are updated by the AND instruction. AF is
undefined. PF has meaning only for an 8-bit operand.

 AND CX, [SI] //AND word in DS at offset [SI] with word in CX

register; Result in CX register
 AND BH, CL AND byte in CL with byte in BH; Result in BH
 AND BX, 00FFH //00FFH Masks upper byte, leaves lower byte unchanged.

OR – OR Destination, Source: This instruction ORs each bit in a source byte or

word with the same numbered bit in a destination byte or word. The result is put
in the specified destination. The content of the specified source is not changed.

The source can be an immediate number, the content of a register, or the

content of a memory location. The destination can be a register or a memory
location. The source and destination cannot both be memory locations. CF and
OF are both 0 after OR. PF, SF, and ZF are updated by the OR instruction. AF
is undefined. PF has meaning only for an 8-bit operand.

 OR AH, CL CL ORed with AH, result in AH, CL not changed

 OR BP, SI SI ORed with BP, result in BP, SI not changed
 OR SI, BP BP ORed with SI, result in SI, BP not changed
 OR BL, 80H //BL ORed with immediate number 80H; sets MSB of BL to 1
 OR CX, TABLE [SI] //CX ORed with word from effective address TABLE [SI];
Content of memory is not changed.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 59
XOR – XOR Destination, Source: This instruction Exclusive-ORs each bit in a
source byte or word with the same numbered bit in a destination byte or word.
The result is put in the specified destination. The content of the specified source
is not changed.

The source can be an immediate number, the content of a register, or the

content of a memory location. The destination can be a register or a memory
location. The source and destination cannot both be memory locations. CF and
OF are both 0 after XOR. PF, SF, and ZF are updated. PF has meaning only for
an 8-bit operand. AF is undefined.

 XOR CL, BH //Byte in BH exclusive-ORed with byte in CL. Result in CL. BH

not changed.
 XOR BP, DI //Word in DI exclusive-ORed with word in BP. Result
in BP. DI not changed.
 XOR WORD PTR [BX], 00FFH Exclusive-OR immediate number 00FFH
with word at offset [BX] in the data segment. Result in memory location [BX]

NOT – NOT Destination: The NOT instruction inverts each bit (forms the 1’s
complement) of a byte or word in the specified destination. The destination can be
a register or a memory location. This instruction does not affect any flag.

 NOT BX Complement content or BX register

 NOT BYTE PTR [BX] Complement memory byte at offset [BX] in data
segment.

NEG – NEG Destination: This instruction replaces the number in a destination

with its 2’s complement. The destination can be a register or a memory location.
It gives the same result as the invert each bit and add one algorithm. The NEG
instruction updates AF, AF, PF, ZF, and OF.

 NEG AL Replace number in AL with its 2’s complement

 NEG BX Replace number in BX with its 2’s complement
 NEG BYTE PTR [BX] Replace byte at offset BX in DX with its 2’s
complement
 NEG WORD PTR [BP] Replace word at offset BP in SS with its 2’s
complement

CMP – CMP Destination, Source: This instruction compares a byte / word in the
specified source with a byte / word in the specified destination. The source can
be an immediate number, a register, or a memory location. The destination can
be a register or a memory location. However, the source and the destination
cannot both be memory locations. The comparison is actually done by
subtracting the source byte or word from the destination byte or word. The source
and the destination are not changed, but the flags are set to indicate the results
of the comparison. AF, OF, SF, ZF, PF, and CF are updated by the CMP
instruction. For the instruction CMP CX, BX, the values of CF, ZF, and SF will be
as follows:

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 60
 CF Z S
F F
CX = BX 0 1 0 Result of subtraction is 0
CX > BX 0 0 0 No borrow required, so CF =
0
CX < BX 1 0 1 Subtraction requires borrow,
so CF = 1

 CMP AL, 01H Compare immediate number 01H with byte in AL

 CMP BH, CL Compare byte in CL with byte in BH
 CMP CX, TEMP Compare word in DS at displacement TEMP with
word at CX
 CMP PRICES [BX], 49H Compare immediate number 49H with byte
at offset [BX] in array PRICES

TEST – TEST Destination, Source: This instruction ANDs the byte / word in the
specified source with the byte / word in the specified destination. Flags are
updated, but neither operand is changed. The test instruction is often used to set
flags before a Conditional jump instruction.

The source can be an immediate number, the content of a register, or the

content of a memory location. The destination can be a register or a memory
location. The source and the destination cannot both be memory locations. CF
and OF are both 0’s after TEST. PF, SF and ZF will be updated to show the
results of the destination. AF is be undefined.

 TEST AL, BH AND BH with AL. No result stored; Update PF,

SF, ZF.
 TEST CX, 0001H AND CX with immediate
number 0001H; No result
stored; Update PF, SF, ZF
 TEST BP, [BX][DI] AND word are offset [BX][DI] in DS with word in
BP.
No result stored. Update PF, SF, and ZF

ROTATE AND SHIFT INSTRUCTIONS

RCL – RCL Destination, Count: This instruction rotates all the bits in a
specified word/byte by some number of bit positions to the left. The operation
circular because the MSB of the operand is rotated into the carry flag and the bit
in the carry flag is rotated around into LSB of the operand. For multi-bit rotates,
CF will contain the bit most recently rotated out of the MSB.

CF MSB LSB

The destination can be a register/a memory location. To rotate the operand by

one bit position, specify this by putting a 1 in the count position of the
instruction. To rotate more than one bit position, load the desired number into
the CL register and put “CL” in the count position of the instruction.

RCL affects only CF and OF. OF will be a 1 after a single bit RCL if the MSB
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 61
 was changed by the rotate. OF is undefined after the multi-bit rotate.

 RCL DX, 1 //Word in DX 1 bit left, MSB to CF, CF to LSB

 MOV CL, 4 //Load the number of bit positions to rotate into CL
RCL SUM [BX], CL //Rotate byte or word at effective address SUM [BX] 4
bits left Original bit 4 now in CF, original CF now in bit 3

RCR – RCR Destination, Count: This instruction rotates all the bits in a
specified word/byte by some number of bit positions to the right. The operation
circular because the LSB of the operand is rotated into the carry flag and the bit
in the carry flag is rotate around into MSB of the operand. For multi-bit rotate,
CF will contain the bit most recently rotated out of the LSB.

CF MSB LSB

The destination can be a register/a memory location. To rotate the operand by

one bit position, specify this by putting a 1 in the count position of the
instruction. To rotate more than one bit position, load the desired number into
the CL register and put “CL” in the count position of the instruction.

RCR affects only CF and OF. OF will be a 1 after a single bit RCR if the MSB
was changed by the rotate. OF is undefined after the multi-bit rotate.

 RCR BX, 1 //Word in BX right 1 bit, CF to MSB, LSB to CF

 MOV CL, 4 //Load CL for rotating 4 bit position
 RCR BYTE PTR [BX], 4 //Rotate the byte at offset [BX] in DS 4 bit positions
right CF = original bit 3, Bit 4 – original CF.

ROL – ROL Destination, Count: This instruction rotates all the bits in a
specified word/byte to the left some number of bit positions. The data bit rotated
out of MSB is circled back into the LSB. It is also copied into CF. In the case of
multiple-bit rotate, CF will contain a copy of the bit most recently moved out of
the MSB. The destination can be a register/a memory location.

CF MSB LSB

To rotate the operand by one bit position, specify this by putting 1 in the count
position in the instruction. To rotate more than one bit position, load the
desired number into the CL register and put “CL” in the count position of the
instruction.
ROL affects only CF and OF. OF will be a 1 after a single bit ROL if the MSB was
changed by the rotate.

 ROL AX, 1 //Rotate the word in AX 1 bit position left, MSB to LSB and CF
 MOV CL, 04H //Load number of bits to rotate in CL ROL BL, CL Rotate BL 4
bit positions
 ROL FACTOR [BX], 1 //Rotate the word or byte in DS at EA = FACTOR [BX]
by 1 bit position left into CF

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 62
ROR – ROR Destination, Count: This instruction rotates all the bits in a
specified word/byte some number of bit positions to right. The operation is
desired as a rotate rather than shift, because the bit moved out of the LSB is
rotated around into the MSB. The data bit moved out of the LSB is also copied
into CF. In the case of multiple bit rotates, CF will contain a copy of the bit most
recently moved out of the LSB.

CF MSB LSB

The destination can be a register/ a memory location. To rotate the operand by

one bit position, specify this by putting 1 in the count position in the
instruction. To rotate by more than one bit position, load the desired number
into the CL register and put “CL” in the count position of the instruction. ROR
affects only CF & OF. OF=1 after a single bit ROR if the MSB was changed by the
rotate.

 ROR BL, 1 //Rotate all bits in BL right 1 bit position LSB to MSB and to CF
 MOV CL, 08H //Load CL with number of bit positions to be rotated ROR
 WORD PTR [BX], CL //Rotate word in DS at offset [BX] 8 bit position right

SAL – SAL Destination, Count SHL – SHL Destination, Count: SAL and SHL
are two mnemonics for the same instruction. This instruction shifts each bit in
the specified destination some number of bit positions to the left. As a bit is
shifted out of the LSB operation, a 0 is put in the LSB position. The MSB will be
shifted into CF. In the case of multi-bit shift, CF will contain the bit most recently
shifted out from the MSB. Bits shifted into CF previously will be lost.

CF MSB LSB 0

The destination operand can be a byte/a word. It can be in a register/a

memory location. To shift the operand by one bit position, specify this by
putting a 1 in the count position of the instruction. To shifts more than 1 bit
position, load the desired number of shifts into the CL register, and put “CL” in
the count position of the instruction.

The flags are affected as follow: CF contains the bit most recently shifted out
from MSB. For a count of one, OF will be 1 if CF and the current MSB are not
the same. For multiple-bit shifts, OF is undefined. SF and ZF will be updated to
reflect the condition of the destination. PF will have meaning only for an
operand in AL. AF is undefined.

 SAL BX, 1 Shift word in BX 1 bit position left, 0 in LSB

 MOV CL, 02h Load desired number of shifts in CL
SAL BP, CL Shift word in BP left CL bit positions, 0 in LSBs
 SAL BYTE PTR [BX], 1 Shift byte in DX at offset [BX] 1 bit position left, 0
in LSB

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 63
SAR – SAR Destination, Count: This instruction shifts each bit in the specified
destination some number of bit positions to the right. As a bit is shifted out of the
MSB position, a copy of the old MSB is put in the MSB position. In other words,
the sign bit is copied into the MSB. The LSB will be shifted into CF. In the case of
multiple-bit shift, CF will contain the bit most recently shifted out from the LSB.
Bits shifted into CF previously will be lost.

MSB MSB LSB CF

The destination operand can be a byte or a word. It can be in a register or in a

memory location. To shift the operand by one bit position, specify this by
putting a 1 in the count position of the instruction. To shifts more than 1 bit
position, load the desired number of shifts into the CL register, and put “CL” in
the count position of the instruction.

The flags are affected as follow: CF contains the bit most recently shifted in
from LSB. For a count of one, OF will be 1 if the two MSBs are not the same.
After a multi-bit SAR, OF will be 0. SF and ZF will be updated to show the
condition of the destination. PF will have meaning only for an 8- bit
destination. AF will be undefined after SAR.

 SAR DX, 1 //Shift word in DI one bit position right, new MSB = old MSB
 MOV CL, 02H //Load desired number of shifts in CL
 SAR WORD PTR [BP], CL //Shift word at offset [BP] in stack segment right
by two bit positions, the two MSBs are now copies of original LSB

SHR – SHR Destination, Count: This instruction shifts each bit in the specified
destination some number of bit positions to the right. As a bit is shifted out of the
MSB position, a 0 is put in its place. The bit shifted out of the LSB position goes
to CF. In the case of multi-bit shifts, CF will contain the bit most recently shifted
out from the LSB. Bits shifted into CF previously will be lost.

0 MSB LSB CF

The destination operand can be a byte/a word in a register/a memory location.

To shift the operand by one bit position, specify this by putting a 1 in the count
position of the instruction. To shifts more than 1 bit position, load the desired
number of shifts into the CL register, and put “CL” in the count position of the
instruction.

The flags are affected by SHR as follow: CF contains the bit most recently
shifted out from LSB. For a count of one, OF will be 1 if the two MSBs are not
both 0’s. For multiple-bit shifts, OF will be meaningless. SF and ZF will be
updated to show the condition of the destination. PF will have meaning only for
an 8-bit destination. AF is undefined.

 SHR BP, 1 Shift word in BP one bit position right, 0 in MSB

 MOV CL, 03H Load desired number of shifts into CL
SHR BYTE PTR [BX] Shift byte in DS at offset [BX] 3 bits right; 0’s in 3
MSBs

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 64
 TRANSFER-OF-CONTROL INSTRUCTIONS
Note:
 The terms above and below are used when referring to the magnitude of
unsigned numbers. Ex: the number 00000111 (7) is above the number
00000010 (2), whereas the number 00000100 (4) is below the number
00001110 (14).
 The terms greater and less are used to refer to the relationship of two signed
numbers. Greater means more positive. The number 00000111 (+7) is
greater than the number 11111110 (-2), whereas the number 11111100 (-4)
is less than the number 11110100 (-6).
 In the case of Conditional jump instructions, the destination address must
be in the range of –128 bytes to +127 bytes from the address of the next
instruction
 These instructions do not affect any flags.

JMP (UNCONDITIONAL JUMP TO SPECIFIED DESTINATION)

This instruction will fetch the next instruction from the location specified in the
instruction rather than from the next location after the JMP instruction. Jump
is two ways

Near jump: If the destination is in the same code segment as the JMP
instruction, then only the instruction pointer will be changed to get the
destination location. This is referred to as a near jump. Near jump is again two
ways
Direct near jump
Indirect near jump
 JMP BX: This instruction replaces the content of IP with the content of BX. BX
must first be loaded with the offset of the destination instruction in CS. This is
a near jump. It is also referred to as an indirect jump because the new value of
IP comes from a register rather than from the instruction itself, as in a direct
jump.
 JMP WORD PTR [BX]: This instruction replaces IP with word from a memory
location pointed to by BX in DX. This is an indirect near jump.

Far Jump: If the destination for the jump instruction is in a segment with a
name different from that of the segment containing the JMP instruction, then
both the instruction pointer and the code segment register content will be
changed to get the destination location. This referred to as a far jump. The JMP
instruction does not affect any flag. Far jump is again two ways

Direct far jump:

Indirect far jump:

JMP DWORD PTR [SI]: This instruction replaces IP with word pointed to by SI
in DS. It replaces CS with a word pointed by SI + 2 in DS. This is an indirect
far jump.

 JMP CONTINUE: This instruction fetches the next instruction from the
address at label CONTINUE. If the label is in the same segment, an offset coded
as part of the instruction will be added to the instruction pointer to produce
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 65
 the new fetch address. If the label is another segment, then IP and CS will be
replaced with value coded in part of the instruction. This type of jump is
referred to as direct because the displacement of the destination or the
destination itself is specified directly in the instruction.

JA / JNBE (JUMP IF ABOVE / JUMP IF NOT BELOW OR EQUAL): If, after a

compare or some other instructions which affect flags, the ZF=CF=0, this
instruction will cause execution to jump to a label given in the instruction. If CF
& ZF are not both 0, the instruction will have no effect on program execution.

 CMP AX, 4371H //Compare by subtracting 4371H from AX

 JA NEXT //Jump to label NEXT if AX above 4371H
 CMP AX, 4371H //Compare (AX – 4371H)
JNBE NEXT //Jump to label NEXT if AX not below or equal to 4371H

JAE / JNB / JNC (JUMP IF ABOVE OR EQUAL / JUMP IF NOT BELOW / JUMP
IF NO CARRY): If, after a compare or some other instructions which affect flags,
the CF=0, this instruction will cause execution to jump to a label given in the
instruction. If CF=1, the instruction will have no effect on program execution.

 CMP AX, 4371H //Compare (AX – 4371H)

JAE NEXT //Jump to label NEXT if AX above 4371H
 CMP AX, 4371H //Compare (AX – 4371H)
JNB NEXT //Jump to label NEXT if AX not below 4371H
 ADD AL, BL //Add two bytes
JNC NEXT //If the result within acceptable range, continue

JB / JC / JNAE (JUMP IF BELOW / JUMP IF CARRY / JUMP IF NOT ABOVE OR

EQUAL): If, after a compare or some other instructions which affect flags, the
CF=1, this instruction will cause execution to jump to a label given in the
instruction. If CF= 0, the instruction will have no effect on program execution.

 CMP AX, 4371H //Compare (AX – 4371H)

JB NEXT //Jump to label NEXT if AX below 4371H
 ADD BX, CX //Add two words
JC NEXT //Jump to label NEXT if CF = 1
 CMP AX, 4371H //Compare (AX – 4371H)
JNAE NEXT //Jump to label NEXT if AX not above or equal to 4371H

JBE / JNA (JUMP IF BELOW OR EQUAL / JUMP IF NOT ABOVE):If, after a

compare or some other instructions which affect flags, either the zero flag or the
carry flag is 1, this instruction will cause execution to jump to a label given in the
instruction. If CF and ZF are both 0, the instruction will have no effect on
program execution.

 CMP AX, 4371H //Compare (AX – 4371H)

JBE NEXT //Jump to label NEXT if AX is below or equal to 4371H
 CMP AX, 4371H //Compare (AX – 4371H)
JNA NEXT //Jump to label NEXT if AX not above 4371H

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 66
JG / JNLE (JUMP IF GREATER / JUMP IF NOT LESS THAN OR EQUAL)

This instruction is usually used after a Compare instruction. The instruction

will cause a jump to the label given in the instruction, if the zero flag is 0 and
the carry flag is the same as the overflow flag.

 CMP BL, 39H //Compare by subtracting 39H from BL

JG NEX //Jump to label NEXT if BL more positive than 39H
 CMP BL, 39H //Compare by subtracting 39H from BL
JNLE NEXT //Jump to label NEXT if BL is not less than or equal to 39H

JGE / JNL (JUMP IF GREATER THAN OR EQUAL / JUMP IF NOT LESS THAN):
This instruction is usually used after a Compare instruction. The instruction will
cause a jump to the label given in the instruction, if the SF=OF.

 CMP BL, 39H Compare by subtracting 39H from BL

JGE NEXT Jump to label NEXT if BL more positive than or
equal to 39H
 CMP BL, 39H Compare by subtracting 39H from BL
JNL NEXT Jump to label NEXT if BL not less than 39H

JL / JNGE (JUMP IF LESS THAN / JUMP IF NOT GREATER THAN OR EQUAL):

This is usually used after CMP instruction. The instruction will cause a jump
to the label given in the instruction if SF≠OF.

 CMP BL, 39H //Compare by subtracting 39H from BL

JL AGAIN //Jump to label AGAIN if BL more negative than 39H
 CMP BL, 39H //Compare by subtracting 39H from BL
JNGE AGAIN //Jump to label AGAIN if BL not more positive than or ≠ 39H

JLE / JNG (JUMP IF LESS THAN OR EQUAL / JUMP IF NOT GREATER): This is
usually used after a CMP instruction. The instruction will cause a jump to the
label given in the instruction if the ZF=1 or if SF≠OF.

 CMP BL, 39H //Compare by subtracting 39H from BL

JLE NEXT //Jump to label NEXT if BL more negative than or equal to 39H
 CMP BL, 39H //Compare by subtracting 39H from BL
JNG NEXT //Jump to label NEXT if BL not more positive than 39H

JE / JZ (JUMP IF EQUAL / JUMP IF ZERO): This instruction is usually used

after a CMP instruction. If the ZF=1, then this instruction will cause a jump to
the label given in the instruction.

 CMP BX, DX //Compare (BX-DX)

JE DONE //Jump to DONE if BX = DX
 IN AL, 30H //Read data from port 8FH SUB AL, 30H Subtract the
minimum value.
JZ START //Jump to label START if the result of subtraction is 0

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 67
JNE / JNZ (JUMP NOT EQUAL / JUMP IF NOT ZERO): This instruction is
usually used after a Compare instruction. If the zero flag is 0, then this
instruction will cause a jump to the label given in the instruction.

 IN AL, 0F8H //Read data value from port

CMP AL, 72 Compare (AL –72)
JNE NEXT Jump to label NEXT if AL 72
 ADD AX, 0002H Add count factor
0002H to AX DEC BX Decrement BX
JNZ NEXT Jump to label NEXT if BX 0

JS (JUMP IF SIGNED / JUMP IF NEGATIVE): This instruction will cause a jump

to the specified destination address if the SF=1, since it indicates a negative
signed number.

 ADD BL, DH Add signed byte in DH to signed byte in DL

JS NEXT Jump to label NEXT if result of addition is
negative number

JNS (JUMP IF NOT SIGNED / JUMP IF POSITIVE): This instruction will cause a
jump to the specified destination address if the SF=0.
 DEC AL //Decrement AL
JNS NEXT //Jump to label NEXT if AL has not decremented to FFH

JP / JPE (JUMP IF PARITY / JUMP IF PARITY EVEN): If the number of 1’s left in
the lower 8 bits of a data word after an instruction which affects the parity flag is
even, then the PF=1. If the parity flag is set, the JP / JPE instruction will cause a
jump to the specified destination address.

 IN AL, 0F8H //Read ASCII character from Port F8H

OR AL, AL //Set flags
JPE ERROR //Odd parity expected, send error message if parity found even
JNP / JPO (JUMP IF NO PARITY / JUMP IF PARITY ODD)

If the number of 1’s left in the lower 8 bits of a data word after an instruction
which affects the parity flag is odd, then the parity flag is 0. The JNP / JPO
instruction will cause a jump to the specified destination address, if the parity
flag is 0.

 IN AL, 0F8H Read ASCII character from

Port F8H OR AL, AL Set flags
JPO ERROR //Even parity expected, send error message if parity found
odd

JO (JUMP IF OVERFLOW): The OF will be set if the magnitude of the result

produced by some signed arithmetic operation is too large to fit in the destination
register or memory location. The JO instruction will cause a jump to the
destination in the instruction, if the OF=1.

 ADD AL, BL Add signed bytes in AL and BL

JO ERROR Jump to label ERROR if overflow from add

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 68
JNO (JUMP IF NO OVERFLOW): The OF will be set if some signed arithmetic
operation is too large to fit in the destination register/memory location. The JNO
instruction will cause a jump to the destination given in the instruction, if the
overflow flag is not set.

 ADD AL, BL Add signed byte in AL and BL

JNO DONE Process DONE if no overflow

JCXZ (JUMP IF THE CX REGISTER IS ZERO): This instruction will cause a jump
to the label to a given in the instruction, if the CX register contains all 0’s. The
instruction does not look at the zero flag when it decides whether to jump or not.

 JCXZ SKIP If CX = 0, skip the process

 SUB [BX], 07H Subtract 7 from data value
SKIP: ADD C Next instruction

LOOP (JUMP TO SPECIFIED LABEL IF CX = 0 AFTER AUTO DECREMENT): This

instruction is used to repeat a series of instructions some number of times. The
number of times the instruction sequence is to be repeated is loaded into CX.
Each time the LOOP instruction executes, CX is automatically decremented by 1.
If CX is not 0, execution will jump to a destination specified by a label in the
instruction. If CX = 0 after the auto decrement, execution will simply go on to the
next instruction after LOOP. The destination address for the jump must be in the
range of –128 bytes to +127 bytes from the address of the instruction after the
LOOP instruction. This instruction does not affect any flag.

 MOV BX, OFFSET PRICES Point BX at first element in array

MOV CX, 40 Load CX with number of elements in array
NEXT: MOV AL, [BX] Get element from array
INC AL Increment the content of AL
MOV [BX], AL Put result back in array
INC BX Increment BX to point to next location
LOOP NEXT Repeat until all elements adjusted

LOOPE / LOOPZ (LOOP WHILE CX ≠ 0 AND ZF = 1): This instruction is used to repeat
a group of instructions some number of times, or until the zero flag becomes 0.
The number of times the instruction sequence is to be repeated is loaded into CX.
Each time the LOOP instruction executes, CX is automatically decremented by 1.
If CX ≠ 0 and ZF = 1, execution will jump to a destination specified by a label in
the instruction. If CX = 0, execution simply go on the next instruction after
LOOPE / LOOPZ. In other words, the two ways to exit the loop are CX = 0 or ZF =
0. The destination address for the jump must be in the range of –128 bytes to
+127 bytes from the address of the instruction after the LOOPE / LOOPZ
instruction. This instruction does not affect any flag.

 MOV BX, OFFSET ARRAY Point BX to address of ARRAY before start of

array
 DEC BX Decrement BX
MOV CX, 100 Put number of array elements in CX
NEXT: INC BX Point to next element in array
CMP [BX], OFFH Compare array element with FFH

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 69
 LOOPE NEXT

LOOPNE / LOOPNZ (LOOP WHILE CX ≠ 0 AND ZF = 0): Used to repeat a group

of instructions some number of times, or until the zero flag becomes a 1. The
number of times the instruction sequence is to be repeated is loaded into the
count-register CX. Each time the LOOPNE / LOOPNZ instruction executes, CX is
automatically decremented by 1. If CX ≠ 0 and ZF = 0, execution will jump to a
destination specified by a label in the instruction. If CX = 0, after the auto
decrement or if ZF = 1, execution simply go on the next instruction after LOOPNE
/ LOOPNZ. In other words, the two ways to exit the loop are CX = 0 or ZF = 1. The
destination address for the jump must be in the range of –128 bytes to +127
bytes from the address of the instruction after the LOOPNE / LOOPZ instruction.
This instruction does not affect any flags.

 MOV BX, OFFSET ARRAY Point BX to adjust before start of array

 DEC BX Decrement BX
MOV CX, 100 Put number of array in CX
NEXT: INC BX Point to next element in array
CMP [BX], ODH Compare array element with 0DH
LOOPNZ NEXT

CALL (CALL A PROCEDURE)

It is used to transfer execution to a subprogram or a procedure. There are two

types of calls near and far.

 A near call is a call to a procedure, which is in the same CS as the CALL

instruction. When the 8086 executes a near CALL instruction, it
decrements the stack pointer by 2 and copies the offset of the next
instruction after the CALL into the stack. This offset saved in the stack is
referred to as the return address, because this is the address that
execution will return to after the procedure is executed. A near CALL
instruction will also load the instruction pointer with the offset of the first
instruction in the procedure. A RET instruction at the end of the
procedure will return execution to the offset saved on the stack which is
copied back to IP.
 A far call is a call to a procedure, which is in a different segment from the
CALL instruction. When it executes, it decrements the SP by 2 and copies
the content of the CS register to the stack. It then decrements the SP by 2
again and copies the offset of the instruction after the CALL instruction to
the stack. Finally, it loads CS with the segment base of the segment that
contains the procedure, and loads IP with the offset of the first instruction
of the procedure in that segment. A RET instruction at the end will return
execution to the next instruction after the CALL by restoring the saved
values of CS and IP from the stack.
 CALL MULT: This is a direct within segment (near or intra segment) call. MULT
is the name of the procedure. The assembler determines the displacement of
MULT from the instruction after the CALL and codes this displacement in as
part of the instruction.

 CALL BX: This is an indirect within-segment (near or intra-segment) call. BX

contains the offset of the first instruction of the procedure. It replaces content
of IP with content of register BX.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 70
 CALL WORD PTR [BX]: This is an indirect within-segment (near or intra-
segment) call. Offset of the first instruction of the procedure is in two memory
addresses in DS. Replaces content of IP with content of word memory location
in DS pointed to by BX.

 CALL DIVIDE: This is a direct call to another segment (far or inter-segment

call). DIVIDE is the name of the procedure. The procedure must be declared far
with DIVIDE PROC FAR at its start. The assembler will determine the code
segment base for the segment that contains the procedure and the offset of the
start of the procedure. It will put these values in as part of the instruction
code.

 CALL DWORD PTR [BX]: This is an indirect call to another segment (far or
inter-segment call). New values for CS and IP are fetched from four-memory
location in DS. The new value for CS is fetched from [BX] and [BX + 1]; the new
IP is fetched from [BX + 2] and [BX +3].

RET (RETURN EXECUTION FROM PROCEDURE TO CALLING PROGRAM)

The RET instruction will return execution from a procedure to the next
instruction after the CALL instruction which was used to call the procedure. If
the procedure is near procedure (in the same code segment as the CALL
instruction), then the return will be done by replacing the IP with a word from
the top of the stack. The word from the top of the stack is the offset of the next
instruction after the CALL. This offset was pushed into the stack as part of the
operation of the CALL instruction. The stack pointer will be incremented by 2
after the return address is popped off the stack.

If the procedure is a far procedure (in a code segment other than the one from
which it is called), then the instruction pointer will be replaced by the word at
the top of the stack. This word is the offset part of the return address put there
by the CALL instruction. The stack pointer will then be incremented by 2. The
CS register is then replaced with a word from the new top of the stack. This
word is the segment base part of the return address that was pushed onto the
stack by a far call operation. After this, the stack pointer is again incremented
by 2.

A RET instruction can be followed by a number, for example, RET 6. In this

case, the stack pointer will be incremented by an additional six addresses after
the IP when the IP and CS are popped off the stack. This form is used to
increment the stack pointer over parameters passed to the procedure on the
stack.

The RET instruction does not affect any flag.

STRING MANIPULATION INSTRUCTIONS

MOVS– MOVS Destination String Name, Source String

Name MOVSB– MOVSB Destination String Name, Source
String Name MOVSW – MOVSW Destination String
Name, Source String Name

This instruction copies a byte or a word from location in the data segment to a

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 71
 location in the extra segment. The offset of the source in the data segment
must be in the SI register. The offset of the destination in the extra segment
must be in the DI register. For multiple-byte or multiple-word moves, the
number of elements to be moved is put in the CX register so that it can
function as a counter. After the byte or a word is moved, SI and DI are
automatically adjusted to point to the next source element and the next
destination element. If DF is 0, then SI and DI will incremented by 1 after a
byte move and by 2 after a word move. If DF is 1, then SI and DI will be
decremented by 1 after a byte move and by 2 after a word move. MOVS does
not affect any flag.

When using the MOVS instruction, you must in some way tell the assembler
whether you want to move a string as bytes or as word. There are two ways to
do this. The first way is to indicate the name of the source and destination
strings in the instruction, as, for example. MOVS DEST, SRC. The assembler
will code the instruction for a byte / word move if they were declared with a DB
/ DW. The second way is to add a “B” or a “W” to the MOVS mnemonic.
MOVSB says move a string as bytes; MOVSW says move a string as words.

 MOV SI, OFFSET SOURCE Load offset of start of source string in

DS into SI MOV DI, OFFSET DESTINATION Load offset of start of
destination string in ES into DI CLD Clear DF to auto increment SI and
DI after move
MOV CX, 04H Load length of string into CX as counter
REP MOVSB Move string byte until CX = 0

LODS / LODSB / LODSW (LOAD STRING BYTE INTO AL OR STRING WORD

INTO AX)

This instruction copies a byte from a string location pointed to by SI to AL, or a

word from a string location pointed to by SI to AX. If DF is 0, SI will be
automatically incremented (by 1 for a byte string, and 2 for a word string) to
point to the next element of the string. If DF is 1, SI will be automatically
decremented (by 1 for a byte string, and 2 for a word string) to point to the
previous element of the string. LODS does not affect any flag.

 CLD Clear direction flag so that SI is

auto-incremented MOV SI, OFFSET SOURCE Point SI to
start of string
LODS SOURCE Copy a byte or a word from string to AL or AX

Note: The assembler uses the name of the string to determine whether the
string is of type bye or type word. Instead of using the string name to do this,
you can use the mnemonic LODSB to tell the assembler that the string is type
byte or the mnemonic LODSW to tell the assembler that the string is of type
word.

STOS / STOSB / STOSW (STORE STRING BYTE OR STRING WORD)

This instruction copies a byte from AL or a word from AX to a memory location

in the extra segment pointed to by DI. In effect, it replaces a string element
with a byte from AL or a word from AX. After the copy, DI is automatically
incremented or decremented to point to next or previous element of the string.
If DF is cleared, then DI will automatically incremented by 1 for a byte string
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 72
 and by 2 for a word string. If DI is set, DI will be automatically decremented by
1 for a byte string and by 2 for a word string. STOS does not affect any flag.

 MOV DI, OFFSET

TARGET STOS
TARGET

Note: The assembler uses the string name to determine whether the string is of
type byte or type word. If it is a byte string, then string byte is replaced with
content of AL. If it is a word string, then string word is replaced with content of
AX.

 MOV DI, OFFSET

TARGET STOSB

“B” added to STOSB mnemonic tells assembler to replace byte in string with
byte from AL. STOSW would tell assembler directly to replace a word in the
string with a word from AX.
CMPS / CMPSB / CMPSW (COMPARE STRING BYTES OR STRING WORDS)

This instruction can be used to compare a byte / word in one string with a byte
/ word in another string. SI is used to hold the offset of the byte or word in the
source string, and DI is used to hold the offset of the byte or word in the
destination string.

The AF, CF, OF, PF, SF, and ZF flags are affected by the comparison, but the
two operands are not affected. After the comparison, SI and DI will
automatically be incremented or decremented to point to the next or previous
element in the two strings. If DF is set, then SI and DI will automatically be
decremented by 1 for a byte string and by 2 for a word string. If DF is reset,
then SI and DI will automatically be incremented by 1 for byte strings and by 2
for word strings. The string pointed to by SI must be in the data segment. The
string pointed to by DI must be in the extra segment.

The CMPS instruction can be used with a REPE or REPNE prefix to compare all
the elements of a string.

 MOV SI, OFFSET FIRST Point SI to source

string MOV DI, OFFSET SECOND Point DI to
destination string
CLD DF cleared, SI and DI will auto-increment after
compare
MOV CX, 100 Put number of string elements in CX
REPE CMPSB Repeat the comparison of string bytes
until end of string or until compared
bytes are not equal

CX functions as a counter, which the REPE prefix will cause CX to be

decremented after each compare. The B attached to CMPS tells the assembler
that the strings are of type byte. If you want to tell the assembler that strings
are of type word, write the instruction as CMPSW. The REPE CMPSW
instruction will cause the pointers in SI and DI to be incremented by 2 after
each compare, if the direction flag is set.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 73
SCAS / SCASB / SCASW (SCAN A STRING BYTE OR A STRING WORD)

SCAS compares a byte in AL or a word in AX with a byte or a word in ES

pointed to by DI. Therefore, the string to be scanned must be in the extra
segment, and DI must contain the offset of the byte or the word to be
compared. If DF is cleared, then DI will be incremented by 1 for byte strings
and by 2 for word strings. If DF is set, then DI will be decremented by 1 for
byte strings and by 2 for word strings. SCAS affects AF, CF, OF, PF, SF, and
ZF, but it does not change either the operand in AL (AX) or the operand in the
string.

The following program segment scans a text string of 80 characters for a

carriage return, 0DH, and puts the offset of string into DI:

 MOV DI, OFFSET STRING

MOV AL, 0DH Byte to be scanned for into AL
MOV CX, 80 CX used as element counter
CLD Clear DF, so that DI auto
increments REPNE SCAS STRING Compare byte in
string with byte in AL

REP / REPE / REPZ / REPNE / REPNZ (PREFIX)

(REPEAT STRING INSTRUCTION UNTIL SPECIFIED CONDITIONS EXIST)

REP is a prefix, which is written before one of the string instructions. It will
cause the CX register to be decremented and the string instruction to be
repeated until CX = 0. The instruction REP MOVSB, for example, will continue
to copy string bytes until the number of bytes loaded into CX has been copied.

REPE and REPZ are two mnemonics for the same prefix. They stand for repeat
if equal and repeat if zero, respectively. They are often used with the Compare
String instruction or with the Scan String instruction. They will cause the
string instruction to be repeated as long as the compared bytes or words are
equal (ZF = 1) and CX is not yet counted down to zero. In other words, there
are two conditions that will stop the repetition: CX = 0 or string bytes or words
not equal.
 REPE CMPSB Compare string bytes until end
of string or until string bytes
not equal.

REPNE and REPNZ are also two mnemonics for the same prefix. They stand for
repeat if not equal and repeat if not zero, respectively. They are often used with
the Compare String instruction or with the Scan String instruction. They will
cause the string instruction to be repeated as long as the compared bytes or
words are not equal (ZF = 0) and CX is not yet counted down to zero.

 REPNE SCASW Scan a string of word until a word in the string

matches the word
in AX or until all of the string has been scanned.

The string instruction used with the prefix determines which flags are affected.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 74
FLAG MANIPULATION INSTRUCTIONS

STC (SET CARRY FLAG): It sets the CF to 1. & does not affect any other flag.

CLC (CLEAR CARRY FLAG): It resets the CF to 0 & does not affect other flags.

CMC (COMPLEMENT CARRY FLAG): It complements the CF & does not affect any
other flag.

STD (SET DIRECTION FLAG): It sets the DF=1. It does not affect any other flag.

CLD (CLEAR DIRECTION FLAG): It resets the DF=0 & does not affect any other
flag.

STI (SET INTERRUPT FLAG): Setting IF=1 enables the INTR interrupt input of the
8086. When the INTR input is enabled, an interrupt signal on this input will
cause the interrupt program execution, push the return address and flags on the
stack, and execute an interrupt service procedure. An IRET instruction at the end
of the interrupt service procedure will restore the return address and flags that
were pushed onto the stack and return execution to the interrupted program. STI
does not affect any other flag.

CLI (CLEAR INTERRUPT FLAG): This instruction resets the IF=0. If the interrupt
flag is reset, the 8086 will not respond to an interrupt signal on its INTR input.
The CLI instructions, however, has no effect on the non-maskable interrupt
input, NMI. It does not affect any other flag.

LAHF (COPY LOW BYTE OF FLAG REGISTER TO AH REGISTER): It copies the

low-byte of the 8086 flag register to AH register. It can then be pushed onto the
stack along with AL by a PUSH AX instruction. LAHF does not affect any flag.

SAHF (COPY AH REGISTER TO LOW BYTE OF FLAG REGISTER): It replaces the

low-byte of the 8086 flag register with a byte from the AH register. SAHF changes
the flags in lower byte of the flag register.

STACK RELATED INSTRUCTIONS

PUSH – PUSH Source

The PUSH instruction decrements the stack pointer by 2 and copies a word
from a specified source to the location in the stack segment to which the stack
pointer points. The source of the word can be general- purpose register,
segment register, or memory. The stack segment register and the stack pointer
must be initialized before this instruction can be used. PUSH can be used to
save data on the stack so that it will not destroyed by a procedure. This
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 75
 instruction does not affect any flag.

 PUSH BX Decrement SP by 2, copy BX to stack.

 PUSH DS Decrement SP by 2, copy DS to stack.
 PUSH BL Illegal; must push a word
 PUSH TABLE [BX] Decrement SP by 2, and copy word from memory in DS
at
EA = TABLE + [BX] to stack
POP – POP Destination

The POP instruction copies a word from the stack location pointed to by the
stack pointer to a destination specified in the instruction. The destination can
be a general-purpose register, a segment register or a memory location. The
data in the stack is not changed. After the word is copied to the specified
destination, the stack pointer is automatically incremented by 2 to point to the
next word on the stack. The POP instruction does not affect any flag.

 POP DX Copy a word from top of stack to DX; increment SP by 2

 POP DS Copy a word from top of stack to DS; increment SP by 2
 POP TABLE [DX] Copy a word from top of stack to memory in DS with
EA = TABLE + [BX]; increment SP by 2.

PUSHF (PUSH FLAG REGISTER TO STACK)

The PUSHF instruction decrements the stack pointer by 2 and copies a word in
the flag register to two memory locations in stack pointed to by the stack
pointer. The stack segment register is not affected. This instruction does to
affect any flag.

POPF (POP WORD FROM TOP OF STACK TO FLAG REGISTER)

The POPF instruction copies a word from two memory locations at the top of
the stack to the flag register and increments the stack pointer by 2. The stack
segment register and word on the stack are not affected. This instruction does
to affect any flag.

INPUT-OUTPUT INSTRUCTIONS

IN – IN Accumulator, Port

The IN instruction copies data from a port to the AL or AX register. If an 8-bit

port is read, the data will go to AL. If a 16-bit port is read, the data will go to
AX. The IN instruction has two possible formats, fixed port and variable port.
For fixed port type, the 8-bit address of a port is specified directly in the
instruction. With this form, any one of 256 possible ports can be addressed.

 IN AL, OC8H Input a byte from port OC8H to AL

 IN AX, 34H Input a word from port 34H to AX

For the variable-port form of the IN instruction, the port address is loaded into
the DX register before the IN instruction. Since DX is a 16-bit register, the port
address can be any number between 0000H and FFFFH. Therefore, up to

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 76
 65,536 ports are addressable in this mode.

 MOV DX, 0FF78H Initialize DX to point to port

IN AL, DX Input a byte from 8-bit port 0FF78H to AL
IN AX, DX Input a word from 16-bit port 0FF78H to AX

The variable-port IN instruction has advantage that the port address can be
computed or dynamically determined in the program. Suppose, for example,
that an 8086-based computer needs to input data from 10 terminals, each
having its own port address. Instead of having a separate procedure to input
data from each port, you can write one generalized input procedure and simply
pass the address of the desired port to the procedure in DX.

The IN instruction does not change any flag.

OUT – OUT Port, Accumulator: The OUT instruction copies a byte from AL or a
word from AX to the specified port. The OUT instruction has two possible forms,
fixed port and variable port. For the fixed port form, the 8-bit port address is
specified directly in the instruction. With this form, any one of 256 possible ports
can be addressed.

 OUT 3BH, AL Copy the content of AL to port 3BH

 OUT 2CH, AX Copy the content of AX to port 2CH

For variable port form of the OUT instruction, the content of AL or AX will be
copied to the port at an address contained in DX. Therefore, the DX register
must be loaded with the desired port address before this form of the OUT
instruction is used.

 MOV DX, 0FFF8H Load desired port address

in DX OUT DX, AL Copy content of AL to port
FFF8H
OUT DX, AX Copy content of AX to port

FFF8H the OUT instruction does not affect any flag.

MISCELLANEOUS INSTRUCTIONS

HLT (HALT PROCESSING): The HLT instruction causes the 8086 to stop fetching
and executing instructions. The 8086 will enter a halt state. The different ways to
get the processor out of the halt state are with an interrupt signal on the INTR
pin, an interrupt signal on the NMI pin, or a reset signal on the RESET input.

NOP (PERFORM NO OPERATION): This instruction simply uses upto three clock
cycles and increments the instruction pointer to point to the next instruction. The
NOP instruction can be used to increase the delay of a delay loop. When hand
coding, a NOP can also be used to hold a place in a program for an instruction
that will be added later. NOP does not affect any flag.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 77
ESC (ESCAPE): This instruction is used to pass instructions to a coprocessor,
such as the 8087 Math coprocessor, which shares the address and data bus with
8086. Instructions for the coprocessor are represented by a 6-bit code embedded
in the ESC instruction. As the 8086 fetches instruction bytes, the coprocessor
also fetches these bytes from the data bus and puts them in its queue. However,
the coprocessor treats all the normal 8086 instructions as NOPs. When 8086
fetches an ESC instruction, the coprocessor decodes the instruction and carries
out the action specified by the 6-bit code specified in the instruction. In most
cases, the 8086 treats the ESC instruction as a NOP. In some cases, the 8086 will
access a data item in memory for the coprocessor.

INT – INT TYPE: The term type in the instruction refers to a number between 0
and 255, which identify the interrupt. When an 8086 executes an INT instruction,
1. Decrement the SP by 2 and push the flags on to the stack.
2. Decrement the SP by 2 and push the content of CS onto the stack.
3. Decrement the SP by 2 and push the offset of the next instruction after the
INT number instruction on the stack.
4. Get a new IP value from an absolute memory address of 4*type number
specified in the instruction. For INT 8 instruction, the new IP will be read
from address 00020H.
5. Get a new CS value from an absolute memory address of 4* type specified
in the instruction+ 2, for INT 8 instruction, the new value of CS will be read
from address 00022H.
6. Reset both IF and TF. Other flags are not affected.

 For, INT 35 the New IP from 0008CH, new CS from 0008EH

 For, INT 03 this is a special form, which has the single-byte code of CCH;
many systems use this as a break point instruction (Get new IP from 0000CH
new CS from 0000EH).

INTO (INTERRUPT ON OVERFLOW)

If the overflow flag (OF) is set, this instruction causes the 8086 to do an
indirect far call to a procedure you write to handle the overflow condition.
Before doing the call, the 8086 will
1. Decrement the SP by 2 and push the flags on to the stack.
2. Decrement the SP by 2 and push CS on to the stack.
3. Decrement the SP by 2 and push the offset of the next instruction after
INTO instruction onto the stack.
4. Reset TF and IF. Other flags are not affected.
5. To do the call, the 8086 will read a new IP value from address 00010H and
a new CS value from address 00012H.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 78
IRET (INTERRUPT RETURN): When the 8086 responds to an interrupt signal or
to an interrupt instruction, it pushes the flags, the current value of CS, and the
current value of IP onto the stack. It then loads CS and IP with the starting
address of the procedure, which you write for the response to that interrupt. The
IRET instruction is used at the end of the interrupt service procedure to return
execution to the interrupted program. To do this return, the 8086 copies the
saved value of IP from the stack to IP, the stored value of CS from the stack to
CS, and the stored value of the flags back to the flag register. Flags will have the
values they had before the interrupt, so any flag settings from the procedure will
be lost unless they are specifically saved in some way.

LOCK –ASSERT BUS LOCK SIGNAL: Many microcomputer systems contain

several microprocessors. Each microprocessor has its own local buses and
memory. The individual microprocessors are connected together by a system bus
so that each can access system resources such as disk drive or memory. Each
microprocessor takes control of the system bus only when it needs to access
some system resources. The LOCK prefix allows a microprocessor to make sure
that another processor does not take control of the system bus while it is in the
middle of a critical instruction, which uses the system bus. The LOCK prefix is
put in front of the critical instruction. When an instruction with a LOCK prefix
executes, the 8086 will assert its external bus controller device, which then
prevents any other processor from taking over the system bus. LOCK instruction
does not affect any flag.

 LOCK XCHG SAMAPHORE, AL

The XCHG instruction requires two bus accesses. The LOCK prefix prevents
another processor from taking control of the system bus between the two
accesses.

WAIT – WAIT FOR SIGNAL OR INTERRUPT SIGNAL: When this instruction is

executed, 8086 enters an idle condition in which it is doing no processing. The
8086 will stay in this idle state until the 8086 test input pin is made low or until
an interrupt signal is received on the INTR or the NMI interrupt input pins. If a
valid interrupt occurs while the 8086 is in this idle state, the 8086 will return to
the idle state after the interrupt service procedure executes. It returns to the idle
state because the address of the WAIT instruction is the address pushed on the
stack when the 8086 responds to the interrupt request. WAIT does not affect any
flag. The WAIT instruction is used to synchronize the 8086 with external
hardware such as the 8087 Math coprocessor.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 79
XLAT / XLATB – TRANSLATE A BYTE IN AL: The XLATB instruction is used to
translate a byte from one code (8 bits or less) to another code (8 bits or less).
Instruction replaces a byte in AL register with a byte pointed to by BX in a lookup
table in the memory. Before the XLATB instruction can be executed, the lookup
table containing the values for a new code must be put in memory, and the offset
of the starting address of the lookup table must be loaded in BX. The code byte to
be translated is put in AL. The XLATB instruction adds the byte in AL to the
offset of the start of the table in BX. It then copies the byte from the address
pointed to by (BX + AL) back into AL. XLATB instruction does not affect any flag.

8086 routine to convert ASCII code byte to EBCDIC equivalent: ASCII code
byte is in AL at the start, EBCDIC code in AL after conversion.
 MOV BX, OFFSET EBCDIC Point BX to the start of EBCDIC table in DS
XLATB Replace ASCII in AL with EBCDIC from table.

Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 80
8086 ASSEMBLER DIRECTIVES

The assembler directives for Intel 8086 macro assembler (ASM86), Borland
Turbo assembler (TASM) and IBM macro assembler (MASM) are

ASSUME: used to tell the assembler the name of the logical segment it
should use for a specified segment.
Example ASSUME CS: CODE //tells the assembler that the instructions
for a program are in a logical segment named CODE.
ASSUME DS: DATA //tells the assembler that for any program
instruction, which refers to the data segment, should use the logical
segment called DATA.

SEGMENT: used to indicate the start of a logical segment. Preceding the

SEGMENT directive is the name of that give to the segment.
Example, CODE SEGMENT // indicates to the assembler the start of a
logical segment called CODE. SEGMENT and ENDS directive are used to
“bracket” a logical segment containing code of data.

ENDS (END SEGMENT): Used with the name of a segment to indicate the
end of that logical segment.

 CODE SEGMENT //Start of logical segment containing

code instruction statements
 CODE ENDS //End of segment named CODE

END (END PROCEDURE): The END directive is put after the last statement
of a program to tell the assembler that this is the end of the program
module. The assembler will ignore any statements after an END directive. A
carriage return is required after the END directive.

DB (DEFINE BYTE): The DB directive is used to declare a byte type variable,

or a set aside one or more storage locations of type byte in memory.

 PRICES DB 49H, 98H, 29H //Declare array of 3 bytes named PRICE

and initialize them with specified values.
 NAMES DB “THOMAS” //Declare array of 6 bytes and initialize with
ASCII codes for the letters in THOMAS.
 TEMP DB 100 DUP (?) //Set aside 100 bytes of storage in memory
and give it the name TEMP. But leave the 100 bytes un-initialized.
 PRESSURE DB 20H DUP (0) //Set aside 20H bytes of storage in
memory give the name PRESSURE and put 0 in all 20H locations.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 81

DW (DEFINE WORD): used to tell the assembler to define a variable of type
word or to reserve storage locations of type word in memory. The statement
MULTIPLIER DW 437AH, for example, declares a variable of type word
named MULTIPLIER, and initialized with the value 437AH when the
program is loaded into memory to be run.

 WORDS DW 1234H, 3456H declare an array of 2 words and

initialize them with the specified values.
 STORAGE DW 100 DUP (0) Reserve an array of 100 words of memory
and initialize all 100 words with 0000. Array is named as STORAGE.
 STORAGE DW 100 DUP (?) Reserve 100 word of storage in memory and
give it the name STORAGE, but leave the words un-initialized.
DD (DEFINE DOUBLE WORD): used to declare a variable of type double
word or to reserve memory locations, which can be accessed as type double
word.
Ex:ARRAY DD 25629261H, //will define a double word named ARRAY and
initialize the double word with the specified value when the program is
loaded into memory to be run. The low word, 9261H, will be put in memory
at a lower address than the high word.

DQ (DEFINE QUADWORD): Used to tell the assembler to declare a variable 4

words in length or to reserve 4 words of storage in memory.

EX:BIG_NUMBER DQ 243598740192A92BH //will declare a variable

named BIG_NUMBER and initialize the 4 words set aside with the specified
number when the program is loaded into memory to be run.

DT (DEFINE TEN BYTES): Used to tell the assembler to declare a variable,

which is 10 bytes in length or to reserve 10 bytes of storage in memory.

EX: PACKED_BCD DT 11223344556677889900 //declare an array named

PACKED_BCD, which is 10 bytes in length. It will initialize the 10 bytes with
the values 11, 22, 33, 44, 55, 66, 77, 88, 99, and 00 when the program is
loaded into memory to be run.

RESULT DT 20H DUP (0) //declare an array of 20H blocks of 10 bytes each
and initialize all 320 bytes to 00 when the program is loaded into memory to
be run.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 82

EQU (EQUATE): used to give a name to some value or symbol. Each time
the assembler finds the given name in the program, it replaces the name
with the value or symbol equated with that name.

Example: FACTOR EQU 03H //at the start of your program, and later in the
program writes the statement ADD AL, FACTOR. When the assembler codes
this instruction statement, it will code it as if you had written the
instruction ADD AL, 03H.

 CONTROL EQU 11000110 B //Replacement MOV AL, CONTROL

Assignment
 DECIMAL_ADJUST EQU DAA Create clearer mnemonic for DAA ADD
AL, BL Add BCD numbers
DECIMAL_ADJUST Keep result in BCD format

LENGTH: Which tells the assembler to determine the number of elements in

some named data item, such as a string or an array.
EX MOV CX, LENGTH STRING1, // will determine the number of elements
in STRING1 and load it into CX. If the string was declared as a string of
bytes, LENGTH will produce the number of bytes in the string. If the string
was declared as a word string, LENGTH will produce the number of words in
the string.

OFFSET: OFFSET is an operator, which tells the assembler to determine the

offset or displacement of a named data item (variable), a procedure from the
start of the segment, which contains it.

Ex MOV BX, OFFSET PRICES //it will determine the offset of the variable
PRICES from the start of the segment in which PRICES is defined and will
load this value into BX.

PTR (POINTER): used to assign a specific type to a variable or a label. It is

necessary to do this in any instruction where the type of the operand is not
clear. When the assembler reads the instruction INC [BX], for example, it
will not know whether to increment the byte pointed to by BX. use the PTR
operator to clarify how want the assembler to code the instruction. The
statement

INC BYTE PTR [BX] //tells the assembler that to increment the byte pointed
to by BX.

INC WORD PTR [BX] //tells the assembler that we want to increment the
word pointed to by BX.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 83

 Also use the PTR operator to clarify the intentions when use indirect
Jump instructions.
JMP [BX], //does not tell the assembler whether to code the instruction
for a near jump. to do a near jump, write the instruction as JMP WORD
PTR [BX].
For a far jump, write the instruction as JMP DWORD PTR [BX].

EVEN (ALIGN ON EVEN MEMORY ADDRESS): As an assembler assembles

a section of data declaration or instruction statements, it uses a location
counter to keep track of how many bytes it is from the start of a segment at
any time. The EVEN directive tells the assembler to increment the location
counter to the next even address, if it is not already at an even address. A
NOP instruction will be inserted in the location incremented over.

 DATA SEGMENT
SALES DB 9 DUP (?) Location counter will point to 0009
after this instruction. EVEN Increment location counter to
000AH
INVENTORY DW 100 DUP (0) Array of 100 words starting on
even address for quicker read DATA ENDS

PROC (PROCEDURE): The PROC directive is used to identify the start of a

procedure. The PROC directive follows a name you give the procedure. After
the PROC directive, the term near or the term far is used to specify the type
of the procedure. The statement DIVIDE PROC FAR, for example, identifies
the start of a procedure named DIVIDE and tells the assembler that the
procedure is far (in a segment with different name from the one that
contains the instructions which calls the procedure). The PROC directive is
used with the ENDP directive to “bracket” a procedure.

ENDP (END PROCEDURE): The directive is used along with the name of the
procedure to indicate the end of a procedure to the assembler. The directive,
together with the procedure directive, PROC, is used to “bracket” a
procedure.

 SQUARE_ROOT PROC Start of

procedure. SQUARE_ROOT ENDP
End of procedure.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 84

ORG (ORIGIN): As an assembler assembles a section of a data declarations
or instruction statements, it uses a location counter to keep track of how
many bytes it is from the start of a segment at any time. The location
counter is automatically set to 0000 when assembler starts reading a
segment. The ORG directive allows you to set the location counter to a
desired value at any point in the program. The statement ORG 2000H tells
the assembler to set the location counter to 2000H, for example.

A “$” it often used to symbolically represent the current value of the

location counter, the $ actually represents the next available byte location
where the assembler can put a data or code byte. The $ is often used in
ORG statements to tell the assembler to make some change in the
location counter relative to its current value. The statement ORG $ + 100
tells the assembler increment the value of the location counter by 100
from its current value.

NAME: The NAME directive is used to give a specific name to each assembly
module when programs consisting of several modules are written.

LABEL: As an assembler assembles a section of a data declarations or

instruction statements, it uses a location counter to be keep track of how
many bytes it is from the start of a segment at any time. The LABEL
directive is used to give a name to the current value in the location counter.
The LABEL directive must be followed by a term that specifics the type you
want to associate with that name. If the label is going to be used as the
destination for a jump or a call, then the label must be specified as type
near or type far. If the label is going to be used to reference a data item, then
the label must be specified as type byte, type word, or type double word.
Here’s how we use the LABEL directive for a jump address.

 ENTRY_POINT LABEL FAR Can jump to here from another segment

NEXT: MOV AL, BL //Cannot do a far jump directly to a label with a
colon The following example shows how we use the label directive for a
data reference.
 STACK_SEG SEGMENT STACK
DW 100 DUP (0) Set aside 100 words for stack
STACK_TOP LABEL WORD Give name to next location after
last word in stack STACK_SEG ENDS

To initialize stack pointer, use MOV SP, OFFSET STACK_TOP.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 85

EXTRN: Used to tell the assembler that the name or labels following the
directive are in some other assembly module. For example, to call a
procedure, which in a program module assembled at a different time from
that which contains the CALL instruction, tell the assembler that the
procedure is external. The assembler will then put this information in the
object code file so that the linker can connect the two modules together. For
a reference to externally named variable, you must specify the type of the
variable, as in the statement EXTRN DIVISOR: WORD. The statement
EXTRN DIVIDE: FAR tells the assembler that DIVIDE is a label of type FAR
in another assembler module. Name or labels referred to as external in one
module must be declared public with the PUBLIC directive in the module in
which they are defined.

 PROCEDURE SEGMENT
EXTRN DIVIDE: FAR //Found in segment PROCEDURES
PROCEDURE ENDS

PUBLIC: Large program are usually written as several separate modules.

Each module is individually assembled, tested, and debugged. When all the
modules are working correctly, their object code files are linked together to
form the complete program. In order for the modules to link together
correctly, any variable name or label referred to in other modules must be
declared PUBLIC in the module in which it is defined. The PUBLIC directive
is used to tell the assembler that a specified name or label will be accessed
from other modules.

SHORT: The SHORT operator is used to tell the assembler that only a 1 byte
displacement is needed to code a jump instruction in the program. The
destination must in the range of –128 bytes to +127 bytes from the address
of the instruction after the jump. The statement JMP SHORT
NEARBY_LABEL is an example of the use of SHORT.

TYPE: It tells the assembler to determine the type of a specified variable.

The assembler actually determines the number of bytes in the type of the
variable. For a byte-type variable, the assembler will give a value of 1, for a
word-type variable, the assembler will give a value of 2, and for a double
word-type variable, it will give a value of 4. It can be used in instruction
such as ADD BX, TYPE- WORD-ARRAY, where we want to increment BX to
point to the next word in an array of words.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 86

GLOBAL (DECLARE SYMBOLS AS PUBLIC OR EXTRN): Used in place of a
PUBLIC directive or in place of an EXTRN directive. For a name or symbol
defined in the current assembly module, the GLOBAL directive is used to
make the symbol available to other modules. The statement GLOBAL
DIVISOR, for example, makes the variable DIVISOR public so that it can be
accessed from other assembly modules.

INCLUDE (INCLUDE SOURCE CODE FROM FILE): Used to tell the

assembler to insert a block of source code from the named file into the
current source module.

Addressing modes: Addressing mode indicates a way of locating data or

operands. Depending up on the data type used in the instruction and the
way the memory access, in 8086 there are 7 addressing modes.
a) Immediate addressing mode
b) Direct addressing mode
c) Register addressing mode
d) Register indirect addressing mode
e) Indexed addressing mode
f) Base + index addressing mode
g) Register relative addressing mode
h) Base relative + index addressing mode

a) Immediate addressing mode: Transfers a source byte/word into the

destination register/memory location.

Ex: MOV CX, 4327 MOV AL, 22

b) Direct addressing mode: Transfers a source byte/word between a
memory location and a register. Memory to memory is not allowed.

Ex: MOV CX,[4327] MOV [4327],AL

c) Register addressing mode: Transfers a source byte/word between a
source register or memory location and destination register or memory
location.

MOV CX, BX MOV CH,AH MOV DX,SI

d) Register indirect addressing mode: Transfers a source byte/word
between a a register and memory location addressed by an index
register (SI or DI) or base register (BX or BP).

MOV [BX], CL MOV AX,[BX] MOV AX, [DI]

ADD AL, [BX] MOV AX, [SI]

e) Indexed addressing mode: The offset of the operand is stored one of
the index registers (SI/DI). DS & ES are the default segments for index

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 87

 registers SI & DI respectively.

Example: MOV AX, [SI]

f) Base + index addressing mode: Transfers a byte/word between a
register and the memory location addressed by a base register (BX or
BP) plus index register (SI or DI) in a default segment.

MOV [BX+DI], AX MOV [BX+SI], CL

g) Register relative addressing mode: Moves a byte/word between a
register and the memory location addressed by an index or base register
(BX/BP/SI/DI) in a default segment plus a displacement (either 8 bit or
16 bit).

MOV AX,[BX+4] MOV CL,[BX+8]

h) Base relative + index addressing mode: Transfers a byte/word
between a register and the memory location addressed by a base
register (BX or BP) and an index register (SI or DI) in a default segment
plus a displacement (either 8 bit or 16 bit).

MOV AX,[BX+DI+4] MOV CL,[BX+SI+8]

Different addressing modes of the 8086 instructions along with the

corresponding MOD, REG and R/M field are given in the table

MODE Memory mode Register

mode

Reg 00 01 10 11
Memory Memory mode with Memory mode with W=0 W-1
mode w/o 8 bit displacement 16 bit displacement
displacement

000 [BX]+[SI] [BX]+[SI]+d8 [BX]+[SI]+d16 AL AX

001 [BX]+[DI] [BX]+[DI]+d8 [BX]+[DI]+d16 CL CX

010 [BP]+[SI] [BP]+[SI]+d8 [BP]+[SI]+d16 DL DX

011 [BP]+[DI] [BP]+[DI]+d8 [BP]+[DI]+d16 BL BX

100 [SI] [SI]+d8 [SI]+d16 AH SP

101 [DI] [DI]+d8 [DI]+d16 CH BP

110 Direct [BP]+d8 [BP]+d16 DH SI

address

111 [BX] [BX]+d8 [BX]+d16 BH DI

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 88

*Default segment for the addressing modes using BP and SP is SS. For all
other addressing modes the default segments are DS or ES.

Machine language instruction format:

Every instruction of 8086 has one or more number of fields associated with
it. The first filled is called operation code field (opcode field), which indicates
the type of operation and the other fields are known as operand fields.

Instruction templates: there are 32 ways to specify the source of the

operand in an instruction. EX: MOV CX, Source

The source can be any one of eight 16 bit registers or a memory location
specified by any one of 24 addressing modes. Therefore there are total 32
different binary codes for specify the source. Similarly, to specify the
destination also there are 32 different binary codes.

Hence there are 64 different codes for MOV instruction where CX can be
used as either source or destination.

Similarly, another 64 codes are for using CL as source or destination.

There are 6 general instruction formats in 8086 and the length of an

instruction may vary from 1 byte to 6 bytes.
 1 byte instructions
 2 byte instructions
 3 or 4 byte instructions
 5 or 6 byte instructions

a) One byte Instruction: This format is one byte long only and may have
the implied data or register operands. The least significant 3 bits of
the opcode are used for specifying the register operand, if any.
Otherwise, all the eight bits form an opcode and the operands are
implied.

EX: CLC; clear carry

CLC=11111000= F8H; no operand

Exchange register with accumulator: contents of the specified register

will be exchanged with the accumulator.

EX: XCHG AX, DX =10010 RRR

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 89

 ASCII Adjust for addition: Here the operand to this instruction is
implicit and it takes the contents of register AL.

AAA = 00110111
b) Two byte Instruction: This format is 2 bytes long. The first byte of the
code specifies the operation code and the width of the operand specifies
by w bit. The second byte of the opcode shows the register operands
and RIM field.

Ex: register to register data transfer: The register represented by the

REG field is one of the operands. The RIM field specifies another
register or memory location (other operand). The register specified by
REG is a source operand if d=0, else it is a destination operand.

MOV Op Code = 100010

MOV CL, AL = 100010 00 11 000 001

Ex: Register to/from memory with no displacement: This is 2 bytes

long and similar to the register to register format except for the MOD
field.

MOD is the MOD of addressing. In case of no displacement MOD = 00

MOV AX,[BX] = 100010 11 00 000 111

c) 3 or 4 byte instruction:

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 90

 Ex: Register to/from Memory with Displacement: This type of
instruction contains one or two additional bytes for displacement along
with 2byte the format of the register to/from memory without
displacement.

MOD = 0 1 - displacement of 8 bytes (instruction is of size 3 bytes)

MOD = 1 0 - displacement of 16 bytes. (Instruction is of size 4 bytes)

In this case, R/M fields indicates a memory when MOD is not 1 1

R/M = 1 1 1 indicates (BX)

Ex: Immediate operand to register: In this, the first byte and the 3
bits of the second byte (REG field) of register to register format are used
for opcode. It also contains one or two bytes of immediate data.

W=0; immediate data size is 8 bits and the size of instruction is 3 bytes.

W=1; immediate data size is 16 bits and the size of instruction is 4

bytes
d) 5 byte/6 byte instruction:
Ex: Immediate operand to memory with 16-bit displacement: This
requires 5 to 6 bytes for coding. The first two bytes contain the
information regarding OPCODE, MOD and R/M fields. The remaining 4
bytes contain 2 bytes of displacement and 2 bytes of data.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 91

 Module IV: Interrupts and Programming

Syllabus

 Interrupts and interrupt service routines

 Interrupt cycle of 8086
 Non mask able interrupt
 maskable interrupt (INTR)
 Interrupt programming
 Programmable Interrupt Controller 8259A

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 92

Interrupt: An interrupt is a condition that halts the processor temporarily
to work on a different task and then return to its previous task. This halt
allows peripheral devices to access the processor. Whenever an interrupt
occurs the processor completes the execution of the current instruction and
starts the execution of an Interrupt Service Routine (ISR). ISR is a program
that tells the processor what to do when the interrupt occurs. After the
execution of ISR, control returns back to the main routine where it was
interrupted. In 8086 microprocessor following tasks is performed when
microprocessor encounters an interrupt:

a) Completes the execution of current instruction in progress.

b) First the value of SP (Stack Pointer) is decremented by 2(SP=SP-2), then
the FR content is pushed to the Stack segment.
c) Clears both IF and TF to 0.
d) SP=SP-2, Pushes the CS (Code Segment) value of return address into the
stack.
e) SP=SP-2, Pushes the IP (Instruction Pointer) value of return address into
the stack.
f) The new IP value is loaded from the word location (Interrupt type) * 04.
g) The new CS value is loaded from the next word location.

Fig 3.1: classification of interrupts

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 93

Types of Interrupts: The following fig shows the types of interrupts in 8086
microprocessor –

Fig 3.2: classification of interrupts

Hardware Interrupts: HI is caused by any peripheral device by sending a

signal through a specified pin to the µP. 8086 has two HI pins, i.e. NMI &
INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt
having lower priority. INTA’ is an interrupt acknowledge.

NMI: Higher priority than INTR and is type 2 interrupt. When this interrupt
is activated, these actions take place

 Steps a to e are same as above

 IP and CS are loaded with the contents of the word location 00008H
and 0000AH. respectively

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 94

INTR: It is lower priority, level sensitive and maskable interrupt. It is
masked by (IF = 0) by CLI instruction and unmasked (IF = 1) by STI
instructions. To respond to this, the µP first completes the current
instruction execution and then, sends ‘0’ through INTA’ pin twice. The first
‘0’ means INTA’ informs the external device to get ready and during the
second ‘0’ the microprocessor receives the 8 bit, say X, from the
programmable interrupt controller. These actions are taken by the
microprocessor

 First completes the current instruction.

 sends the 1st INTA’ to the interrupting device to calculates the vector
number
 Generates 2nd INTA’, to the interrupting device, then it sends the
vector number N to the µP.
 µP multiplies the type no. with 4 and jumps to that location in the IVT
to obtain the ISR address.
 Then steps b to g are same as above

Software Interrupts: These are the instructions inserted within the

program to generate interrupts and 8086 has 256 software interrupts. The
instruction format is INT type where the type ranges from 00 to FF. INT-
type instructions are 2-byte instruction. First byte provides the op-code and
the second byte provides the interrupt type number. IP is loaded from type *
04 H and CS is loaded from the next address give by (type * 04) + 02 H. The
starting address ranges from 00000 H to 003FF H. All These interrupts are
grouped as below.

A. Dedicated interrupts (INT 0…..INT 4): First 5 pointers are dedicated

interrupt pointers.

 TYPE 0 interrupt represents division by zero situation.

 TYPE 1 interrupt represents single-step execution during the
debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 95

  TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
1. INT 0 (Divide Error)-This interrupt occurs whenever there is division
error i.e. when the result of a division is too large to store. Its ISR
address is stored at location 0 x 4 = 00000H in the IVT.

Ex1: Mov AL, 82H

SUB CL,CL
DIV CL
EX2: MOV AX, 0 FFFFH
MOV BL, 2
DIV BL 65,535/2=32767 larger than 255maximum capacity of AL

2. INT 1 (Single Step) - The processor executes this interrupt after every
instruction if the TF is set. It puts processor in single stepping mode
i.e. the processor pauses after executing every instruction. This is very
useful during debugging. Its ISR generally displays contents of all
registers. Its ISR address is stored at location 1 x 4 = 00004H in the
IVT.
3. INT 2 (Non mask-able Interrupt)- The processor executes this ISR in
response to an interrupt on the NMI line. Its ISR address is stored at
location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)-It is a 1-byte instruction having op-code
is CCH. This interrupt is used to cause breakpoints in the program. It
is caused by writing the instruction INT 03H or simply INT. It is useful
in debugging large programs where single stepping is efficient. Its ISR
is used to display the contents of all registers on the screen. Its ISR
address is stored at location 3 x 4 = 0000CH in the IVT.
5. INT 4(INTO)- Interrupt on overflow instruction-It is a 1-byte
instruction and the op-code is CEH. This interrupt occurs if the
overflow flag is set. It is used to detect overflow error in signed
arithmetic operations. Its ISR address is stored at location 4 x 4 =
00010H in the IVT. If the overflow flag is reset then, the execution
continues to the next instruction.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 96

 B. Reserved interrupts (INT 5…..INT 31): Reserved by Intel to use in
higher processors like 80386, Pentium etc. There are 27 reserved interrupts

C. Available interrupts (INT 32…..INT 225): There are 224 user defined
software interrupts. ISRs for these interrupts are written by the users
to service various user defined conditions. These interrupts are
invoked by writing the instruction INT n. Its ISR address is obtained
by the microprocessor from location n x 4 in the IVT.

IVT (Interrupt Vector table): Interrupt vectors are the addresses that inform
the interrupt handler as to where to find the ISR. All interrupts are assigned a
number from 0 to 255, with each of these interrupts being associated with a
specific interrupt vector. The 8086 series of µPs has an IVT situated at
0000:0000 which extends up to 1024 bytes. The IVT holds:

Address Base Base+1 Base+2 Base+3

Content IP Lower IP Higher CS Lower CS Higher

1. IVT is the link between an interrupt type code and the procedure to
service interrupts associated with that code. 8086 supports total 256
types i.e. 00H to FFH.
2. For each type it has to reserve four bytes i.e. double word. This double
word pointer contains the address of the procedure that is to service
interrupts of that type.
3. The higher addressed word of the pointer contains the base address of
the segment containing the procedure.
4. The lower addressed word contains the procedure’s offset from the
beginning of the segment.
5. Thus NEW CS: NEW IP provides NEW physical address from where
user ISR routine will start.
6. Since for each type, four bytes are required; the interrupt pointer table
occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of memory.
7. The total interrupt vector table is divided into three groups namely,

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 97

 A. Dedicated interrupts (INT 0…..INT 4)

B. Reserved interrupts (INT 5…..INT 31)

C. Available interrupts (INT 32…..INT 225)

Fig 4.1: interrupt vector table

The starting address for type 0 interrupt is 000000H, for type1 interrupt is
00004H similarly for type2 is 00008H and ……so on. The interrupts from
Type 5 to Type 31 are reserved for other advanced microprocessors, and
interrupts from 32 to Type 255 are available for user defined interrupts.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 98

 Fig 4.2: flow chart for interrupt acceptance

Interrupt priority:

interrupt priority
Divide error, INT n, INT 0 highest
NMI
INTR
Single Step Lowest

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 99

 Programmable Priority Interrupt Controller- 8259A
For the applications where the interrupts from multiple source, use an
external device called a Priority Interrupt Controller ( PIC ) to the interrupt
signals into a single interrupt input on the processor.The data bus allows
the 8086 to send control words to the 8259A and read a status word from
the 8259A. The RD’ and WR’ inputs control these transfers when the device
is selected by asserting its chip select CS input low. The 8 bit data bus also
allows the 8259A to send interrupt types to the 8086.

Intel 8259A is a programmable interrupt controller specially designed to

work with Intel microprocessor 8080, 8085A, 8086, 8088. The main features
of 8259A are given below:

1) It can handle eight interrupt inputs. This is equivalent to providing

eight interrupt pins on the processor in place of one INTR (in
8085A)/INT(in 8086) pin.
2) The chip can vector an interrupt request anywhere in the memory
map from 0000H to FFFFH in 8085A microprocessor. However, all the
eight interrupts are spaced at an interval of either four or eight
locations. This eliminates the major drawback of 8085A interrupts in
which all interrupts are vectored to memory location on page 00 i.e.,
TRAP, RST7.5, RST6.5 and RST5.5 are vectored to memory locations
0024H, 003CH, 0034H and 002CH respectively.
3) It can resolve eight levels of interrupt priorities in a variety of modes.
The priorities of interrupts can be changed under running condition.
Some of the desired lower priority interrupts may be allowed to be
acknowledged during the service of higher priority interrupts.
4) The status of pending interrupts, in service interrupts, and masked
interrupts can be read at any time similar to RST interrupts of 8085A.
5) The chip can be programmed to accept interrupt requests either as
level triggered or edge triggered However, all interrupts must be either
level triggered or edge triggered.
6) If required, nine 8259As can be cascaded in a master-slave
configuration mode to handle 64 interrupt inputs. In this case, the
interrupting devices send their interrupt requests either to slave
8259A or to master 8259A directly. The slave 8259As send their
interrupt to master interrupt request inputs and the master will send
a single interrupt to microprocessor interrupt pin INTR/INT.

Intel 8259A is one of the most common interrupt controller used in IBM
PCs. It can handle eight vectored priority interrupts for the CPU. It is a 28
pin DIP package and requires a single +5V DC supply for its operation. It is
designed to minimize the software and real time overhead in handling multi-
level priority interrupts. The 8259A is upward compatible with 8259. The
main difference between the two is that the 8259A can be used with Intel

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 100
8086/8088 processor. It also includes additional features such as level
triggered mode, buffered mode and automatic end of interrupt mode.

The pin diagram and internal block diagram of PIC is shown in figure. The
pins are defined as follows:

CS’ (Chip Select signal): To access the chip, CS’ signal must be made low, a
LOW on this pin enables RD’ & WR’ communication between the CPU and
the 8259A. This pin is connected to address bus through the decoder logic
circuit. Interrupt acknowledge functions to transfer the control to interrupt
service subroutine are independent of CS.

WR’ (Write signal): When CS’ is low enables the 8259 A to accept command
words from CPU.

RD’(Read signal): When CS’ is low enables this 8259A to release status
(pending interrupts or in-service interrupts or masked interrupts) on to the
data bus for the CPU. The status includes the contents of IMR (interrupt
mask register) or ISR (interrupt service register) or IRR (interrupt request
register) or a priority level.

PIN Pin Name Description

1 CS’ Chip Select Input

2 WR’ Write control signal

3 RD’ Read control signal

4-11 D7-D0 Data Bus

12-13, 15 CAS0-CAS2 Cascade control

14 GND Ground

16 SP’/EN’ Salve Program/Enable

Buffer

17 INT Interrupt output for

processor

18-25 IRQ0 – IRQ7 Interrupt request inputs

26 INTA’ Interrupt Acknowledge

input

27 A0 Address input

28 VCC +5V supply

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 101
 Fig 4.3: Pin Configuration of Intel 8259A
D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt
vector information is transferred via this data bus. This bus is connected to
BDB of 8086.

CAS2-CAS0 (Cascade lines): The CAS lines form a local 8259A bus to
control multiple 8259As in master-slave configuration, i.e., to identify a
particular slave 8259A to be accessed for transfer of vector information.
These pins are automatically set as output pins for master 8259A and input
pins for a slave 8259A once the chips are programmed as master or slave.

SP/ EN (Salve Program/Enable Buffer): This is a dual function pin. When

the chip is programmed in buffered mode, the pin can be used as an output
and when not in the buffered mode it is used as an input.

In non-buffered mode it is used as an input pin to determine whether the

8259A is to be used as a master (SP/ EN= 1) or as a slave (SP/ EN = 0).

In buffered mode, normally data bus buffers are used. These buffers need to
be enabled or disabled during transfer of vector information depending upon
whether 80259A is connected before the buffer or after the buffer. To
disable/enable the data bus transceivers (buffers) when data are being
transferred from the 8259A to the CPU, this pin is made low or high.

INT (Interrupt output): This pin goes high whenever a valid interrupt
request is asserted. It is used to interrupt the CPU, thus it is connected to
the CPU’s interrupt pin (INTR). In case of master-slave configuration, the
interrupt pin of slave 8259A is connected to interrupt request input of
master 8259A.

INTA’ (Interrupt Acknowledge): This pin is used to enable 8259A interrupt

vector data on the data bus by a sequence of interrupt acknowledge pulses
issued by the CPU.

IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt

request input pins. An interrupt request is executed by raising an IR input
(low to high), and holding it high until it is acknowledged. (Edge triggered
mode) or just by a high level on an interrupt request input (Level triggered
mode).

A0 (A0 address line): This pin acts in conjunction with the RD’ &CS’ pins.
It is used to send various command words from the CPU and to read the
status. It is normally connected to the CPU A0 address line. Two addresses
are assigned/reserved in the I/O address space for each 8259A in the
system-one with A0=0 is called even address and other with A0 = 1 is called
odd address.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 102
Functional Description of 8259A: 8259A is used to manage the interrupt
requirement of the system. It has 8 interrupt input lines through which it
accepts interrupt requests from external devices and determines the priority
of the incoming request and issues an interrupt to the CPU. The interrupt
inputs are extendable up to 64 levels. And subsequently inputs information
related to ISR so that the processor can initialize the program counter with
the ISR address of the interrupting device. It is programmed as an I/O
device and provides number of interrupt modes to the programmer so that
the manner in which the requests are processed by 8259 can be configured
to match the system requirement. Figure below shows the functional
diagram of 8259A.

Fig 4.4: Internal Structure of 8259A

The block diagram shows the following sub components of 8259A

i. Data Bus Buffer

ii. Interrupt Request Register
iii. In-Service register
iv. Priority Resolver
v. Interrupt mask Register
vi. Read / Write Logic
vii. Cascade Buffer/Comparator

Data Bus Buffer: It is a bidirectional 8-bit register. CPU transfers the

Control and status information through this buffer to 8259A; similarly 8259
transfers the vector address information to data bus through this buffer. On
the CPU side it is connected to the 8-bit data bus and on the other side it is
connected internally to the internal data bus.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 103
Interrupt Request register (IRR) and In-Service register (ISR): The
interrupt requests from the external devices IRQ lines are handled by these
two registers in cascade. IRR is used to latch the incoming request and, in
conjunction with priority resolver, allows unmasked requests with sufficient
priority to put a ‘1’ on the INT pin. ISR is used to store all the interrupts
that are being serviced by the CPU.

Priority resolver: The logic block determines the priority of the services
being in-request in the Interrupt Request Register. The highest priority is
selected and sent to the ISR during INTA pulse.

Interrupt Mask Register (IMR) is used to disable (mask) or enable (unmask)

individual interrupt inputs. Each bit in this register corresponds to the
interrupt input with the same number. Unmask an interrupt input by
sending a command word with a 0 in the bit position that corresponds to
that input.The IMR operates on the IRR. Masking of a higher priority
interrupt will not disable or mask the interrupt request lines of lower
priority.

Interrupt (INT) and Interrupt Acknowledgement (INTA’): INT output from

8259A goes to CPU interrupt input. This line is used to inform the CPU
about the interrupting device that is interrupting the processor. INTA pulse
will make the 8259A to release vectored address information of the interrupt
service routine (ISR) onto the data bus.

Read/Write Control Logic: The function of the R/W logic is to accept the
commands from the CPU. It consists of an initialization Command Word
(ICW) registers and Operation Command register (OCW) registers which
store various control formats. It also allows the status of 8259 to be
transferred to data bus. It has the following control signals:

Chip Select (CS’): It is a low active signal is used to select the chip. No
operation is possible until Chip is selected through this input.

Write (WR’) and Read (RD’): These are two low active signal used for read
and write operations. WR is used to write control words (ICWs and OCWs) to
8259A and read (RD’) is used to read the status information of IRR, ISR,
IMR or the interrupt level to the data bus.

Address input (A0): The Address input A0 from the processor can be
directly connected to A0 pin of 8259A and is used with RD’ and WR’ to write
commands and to select various status registers for read operation.

Cascade Buffer / Comparator: For one of the two purposes; either as an

input to determine whether 8259A is to be master (SP’/EN’ = 1) or as slave

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 104
(SP’/EN’ = 0), or as an output to disable the data bus transceiver when data
are being transferred from the 8259A to the CPU.

CAS0 – CAS2 Cascade Lines: This block is of importance when more than
eight interrupts are to be used. This allows multiple 8259A to be cascaded
for this purpose.In cascade mode, a master 8259A along with eight slaves
8259A can provide up to 64 vectored interrupt lines. These three lines act as
select lines for addressing the slave 8259A. CAS0-to-CAS2 is outputs from
8259A when used as master and are inputs when used as slave. As a
master, 8259A sends the IDs of the interrupting slave device onto the CAS0-
CAS2 lines. The selected slave device will send its preprogrammed
subroutine address onto the data bus during the next one or two
consecutive INTA’ pulses.

The device 8259A can be interfaced with any CPU using either Polling or
Interrupt. In polling, the CPU keeps on checking each peripheral device in
sequence to ascertain if it requires any service from the CPU. If any such
service request is noticed, the CPU serves the request and then goes on to
the next device in sequence. The command words are sent to an 8259A to
initialize it. The flow chart is shown for the ICW1 and an ICW2 and sent to
any 8259A in the system. If the system has any slave 8259As (cascade
mode), then an ICW3 must be sent to the master and a different ICW must
be sent to the slave. The 8259A must be initialized by writing two to four
command words into the respective command word registers. These are
called as initialized command words. If A0 = 0 and D4 = 1, the control word
is recognized as ICW1. It contains the control bits for edge/level triggered
mode, single/cascade mode, call address interval and whether ICW4 is
required or not

Command Words: 8259A has two types of command words, initialization

and operational control word.

i. Initialization command word:

a. ICW1 for chip (8259A) control
b. ICW2 for type
c. ICW3 for status control
d. ICW4 for mode control
ii. Operational Command Word: OCW1, OCW2, OCW3

The Initialization Control Words (ICWS): Initialization control words are

normally set by the initialization routine when the computer system is first
brought up and remains constant throughout its operation. The operational
command words are used to dynamically control the processing of the
interrupt. The formats of various command words are given below:

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 105
ICW1 – Interrupt Trigger Type/ Address Interval/ Cascade? / With ICW4?

ICW2–Selects Base Vector Address 00001000 (0x08) for PIC1 and 01110000
(0x70) for PIC2

ICW3 – Master/ Slave Connection Information

ICW4 – The only thing we must set is 8086/8080 Mode which is done using
Bit 0.

Address Read/Write Function

Write Initialization Command Word 1 (ICW1)
Write Operation Command Word 2 (OCW2)
Base Write Operation Command Word 3 (OCW3)
Read Interrupt Request Register (IRR)
Read In-Service Register (ISR)
Write Initialization Command Word 2 (ICW2)
Write Initialization Command Word 3 (ICW3)
Base+1
Write Initialization Command Word 4 (ICW4)
Read/Write Interrupt Mask Register (OCW1)

Initialization Command Word 1 (ICW1)

Bit(s) Function
7:5 Interrupt Vector Addresses for MCS-80/85 Mode.(no use for 8086)
4 Must be set to 1 for ICW1
3 1 Level Triggered Interrupts
LITM 0 Edge Triggered Interrupts

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 106
 2 1 Call Address Interval of 4
ADI(for 8085) 0 Call Address Interval of 8
1 1 Single PIC
SNGL 0 Cascaded PICs
0 1 Will be Sending ICW4
0 Don't need ICW4

Initialization Command Word 2 (ICW2)

Bit 8086/8080 Mode MCS 80/85 Mode
7 I7 A15
6 I6 A14
5 I5 A13
4 I4 A12
3 I3 A11
2 - A10
1 - A9
0 - A8

7 6 5 4 3 2 1 0

Filled from bit 7-3 of the 2nd byte Bit 2-0 are set according to the level of
output by the CPU during the the interrupt request
initialization of 8259A
IR6 would cause bit 2-0 to 110 and so on

Initialization Command Word 3 (ICW3): ICW3 is significant only in

systems including more than one 8259A and is output only if SNGL=0
For Master

Bit Function
7 IR7 is connected to a Slave
6 IR6 is connected to a Slave
5 IR5 is connected to a Slave
4 IR4 is connected to a Slave
3 IR3 is connected to a Slave
2 IR2 is connected to a Slave
1 IR1 is connected to a Slave
0 IR0 is connected to a Slave

For Slave:

Bit(s) Function
7 Reserved. Set to 0
6 Reserved. Set to 0
5 Reserved. Set to 0
4 Reserved. Set to 0
3 Reserved. Set to 0

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 107
 2:0 Slave ID
000 Slave 0
001 Slave 1
010 Slave 2
011 Slave 3
100 Slave 4
101 Slave 5
110 Slave 6
111 Slave 7
Initialization Command Word 4 (ICW4) : ICW4 is output to only if IC4
(ICW1) is set to 1; otherwise, the content of ICW4 is cleared. The bits in
ICW4 are as follows

Bit(s) Function
7 Reserved. Set to 0
6 Reserved. Set to 0
5 Reserved. Set to 0
4 1 Special Fully Nested Mode
SFNM 0 Not Special Fully Nested Mode
3:2 0x Non - Buffered Mode
BUF:M/S (1/0) 10 Buffered Mode - Slave
11 Buffered Mode - Master
1 1 Auto EOI
AEOI 0 Normal EOI
0 1 8086/8080 Mode If 1, the ISR bit that caused the interrupt is cleared at the
uPM end of 2nd INTA’ pulse
0 MCS-80/85

The Operation Control Words (OCWS)

OCW1 – Interrupt Masks: is used for masking the interrupt request; when
the mask bit corresponding to an interrupt request is 1, then the request is
blocked.

OCW2 – Selects how the End of Interrupt (EOI) procedure works.

OCW3 – Bits 0 and 1 enables to read IRR and ISR registers.

OCW2 and OCW3 are used for controlling the mode of the 8259A and
receiving EOI commands.

A byte is transferred to OCW1 by using the odd address (A0=1) associated

with 8259A and bytes are output to OCW2 and OCW3 by using even
address (A0=0). OCW2 is distinguished from OCW3 by the contents of bit-3
of data byte. If bit-3 is 0, the byte is put in OCW2, and if it is 1, the byte is
put in OCW3.

Both OCW2 & OCW3 are distinguished from ICW1, which also uses even
address, by the content f bit-4 of data byte.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 108
If content of bit-4 of data byte is 0, then byte is put in OCW2 or OCW3
according to bit-3. There is no ambiguity in ICW2, ICW3, ICW4 and OCW1
all using the odd address because initialization word must always follow
ICW1 as dictated by initialization sequence.

Operation Control Word 1 (OCW1)

Bit PIC 2 PIC 1
7 Mask IRQ15 Mask IRQ7
6 Mask IRQ14 Mask IRQ6
5 Mask IRQ13 Mask IRQ5
4 Mask IRQ12 Mask IRQ4
3 Mask IRQ11 Mask IRQ3
2 Mask IRQ10 Mask IRQ2
1 Mask IRQ9 Mask IRQ1
0 Mask IRQ8 Mask IRQ0

Operation Control Word 2 (OCW2)

Bit(s) Function
7:5 000 Rotate in Auto EOI Mode (Clear)
001 Non Specific EOI
010 Reserved
011 Specific EOI
100 Rotate in Auto EOI Mode (Set)
101 Rotate on Non-Specific EOI
110 Set Priority Command (Use Bits 2:0)
111 Rotate on Specific EOI (Use Bits 2:0)
4 Must be set to 0
3 Must be set to 0
2:0 000 Act on IRQ 0 or 8
001 Act on IRQ 1 or 9
010 Act on IRQ 2 or 10
011 Act on IRQ 3 or 11
100 Act on IRQ 4 or 12
101 Act on IRQ 5 or 13
110 Act on IRQ 6 or 14
111 Act on IRQ 7 or 15

Operation Control Word 3 (OCW3)

Bit(s) Function
7 Must be set to 0
6:5 00 Reserved
01 Reserved
10 Reset Special Mask
11 Set Special Mask
4 Must be set to 0
3 Must be set to 1
2 1 Poll Command
0 No Poll Command
1:0 00 Reserved
01 Reserved
10 Next Read Returns Interrupt Request Register
11 Next Read Returns In-Service Register

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 109
Interrupt Sequence of 8259A: The addressing capability allows direct or
indirect jumping to specific ISR based on the interrupt number and the
interrupting device. The normal sequence of events during an interrupt
depends on the type of the CPU used and are given below:

i. One or more IR lines (IR7±0) are raised high, setting the corresponding
IRR bit(s).
ii. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
iii. After a bit in the IRR is set to ‘1’ it is compared with the corresponding
mask bit in IMR. If the mask bit is 0, the request is passed to the
priority resolver, but if it is 1, the request is blocked.
iv. When an interrupt is input to the priority resolver its priority is
examined and. If according to the current state of the priority resolver
the interrupt is to be sent to the CPU, the INT line is activated.
v. Assuming that the IF flag in the CPU was set to 1, the CPU will enter
its interrupt sequence at the completion of the current instruction and
return two negative pulses over the INTA’ line
vi. Upon receiving the 1st INTA’ pulse, the IRR latches are disabled, so
that the IRR will ignore further signals on the IR7-IR0 lines. This state
is maintained until the end of the 2nd INTA’ pulse.
vii. The 1st INTA’ pulse will cause the appropriate ISR bits to be set and
the corresponding IRR bit to be cleared.
viii. The 8086 will initiate a second INTA’ pulse. During this pulse, the
8259A releases an 8-bit pointer onto the Data Bus where it is read by
the CPU. The current content of ICW2 to be placed on D7-D0, and the
CPU uses this byte as the interrupt type.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 110
 ix. Now if the automatic end of interrupt (AEOI) bit ICW4 is 1, at the end
of the second INTA’ pulse the ISR bit that was set by 1 st INTA’ pulse is
cleared; otherwise, the ISR bit is not cleared until the proper end of
interrupt (EOI)command is sent to OCW2

8086 Example: A typical program sequence for setting the content of ICWs,
which assume the even address of the 8259A is 0080h, is given below:

MOV AL, 13h; ICW1 indicating request to be edge trigger, use one
8259A, ICW4 to be output

OUT 80h, AL

MOV AL, 18h ; cause 5 MSBs of interrupt type to be set to 00011

OUT 81h

MOV AL, 0Dh ; informs the 8259A that SFNM is not to be used,
SP’/EN’ used to disable TXR, and ; 8259A is master,
EOI used to clear ISR bit, and 8259A is part of 8086
system

OUT 81h, AL First two instructions causes the requests to be edge

triggered, denote that only one 8259A is used

Ex 1:Write a program in 8086 microprocessor to find out the addition of two

8-bit BCD numbers, where numbers are stored from starting memory
address 2000 : 500 and store the result into memory address 2000 : 600
and carry at 2000 : 601.

MEMORY ADDRESS MNEMONICS COMMENT

400 MOV AL, [500] AL<-[500]
404 MOV BL, [501] BL<-[501]
408 ADD AL, BL AL<-AL+BL
40A DAA DECIMAL ADJUST AL
40B MOV [600], AL AL->[600]
40F MOV AL, 00 AL<-00
411 ADC AL, AL AL<-AL+AL+cy(prev)
413 MOV [601], AL AL->[601]
417 HLT END

Ex 2: Write a program to add two 16-bit numbers where starting address is

2000 and the numbers are at 3000 and 3002 memory address and store
result into 3004 and 3006 memory address.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 111
 Mnemonics
MOV CX, 0000
MOV AX, [3000]
MOV BX, [3002]
ADD AX, BX
JNC 2010
INC CX
2010 MOV[3004], AX
MOV[3006], CX
INT 03

Problem – Write an ALP to add two 16 bit BCD numbers with carry in 8086
microprocessor.

Mnemonics Comments
MOV AL, [500] AL ← [500]
MOV BL, [502] BL ← [502]
ADD AL, BL AL ← AL+BL
DAA Decimal Adjust AL
MOV [600], AL AL → [600]
MOV AL, [501] AL ← [501]
MOV BL, 503 BL ← [503]
ADC AL, BL AL ← AL+BL+CY
DAA Decimal Adjust AL
MOV [601], AL AL → [601]
MOV AL, 00 AL ← 00H
ADC AL, AL AL ← AL+AL+CY
MOV [602], AL AL → [602]
INT 03 Stop Execution

Problem – Write an ALP to add the content of memory location 2000 : 0500
with content of memory location 3000 : 0600 and store result into 5000 :
0700 memory location.

MOV CX, 2000

MOV DS, CX
MOV AX, [500]
MOV CX, 3000
MOV DS, CX
ADD AX, [600]
MOV CX, 5000

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 112
 MOV ES, CX
MOV[700], AX
INT 03

Problem – Write an ALP to find out the Subtraction of two 8-bit BCD
numbers, where numbers are stored from starting memory address 2000 :
500 and store the result into memory address 2000 : 600 and carry (borrow)
at 2000 : 601.

MOV AL, [500]

MOV BL, [501]
SUB AL, BL
DAS
MOV [600], AL
MOV AL, 00
ADC AL, AL
MOV [601], AL
INT 03

Problem – Write an ALP to find out the subtraction of two 16-bit BCD
numbers, where numbers are stored from starting offset 500 and store the
result into offset 600.

MEMORY ADDRESS MNEMONICS COMMENT

400 MOV AL, [500] AL<-[500]
404 MOV BL, [502] BL<-[502]
408 SUB AL, BL AL<-AL-BL
40A DAS decimal adjust
40B MOV [600], AL AL->[600]
40F MOV AL, [501] AL<-[501]
413 MOV BL, [503] BL<-[503[
417 SBB AL, BL AL<-AL-BL-borrow
419 DAS decimal adjust
41A MOV [601], AL AL->[601]
41E MOV AL, 00 AL<-00
420 ADC AL, AL AL<-AL+AL+borrow
422 MOV [602], AL A->[602]
426 HLT End

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 113
Problem – Write an ALP to subtract two 16-bit numbers where starting
address is 2000 and the numbers are at 3000 and 3002 memory address
and store result into 3004 and 3006 memory address.

Memory Mnemonics Operands Comment

2000 MOV CX, 0000 [CX] <- 0000
2003 MOV AX, [3000] [AX] <- [3000]
2007 MOV BX, [3002] [BX] <- [3002]
200B SUB AX, BX [AX] <- [AX] – [BX]
200D JNC 2010 Jump if no borrow
200F INC CX [CX] <- [CX] + 1
2010 MOV [3004], AX [3004] <- [AX]
2014 MOV [3006], CX [3006] <- [CX]
2018 HLT Stop

Problem – Write an ALP to multiply two 8-bit numbers, where numbers are
stored from offset 500 and store the result into offset 600.

MEMORY ADDRESS MNEMONICS COMMENT

400 MOV SI, 500 SI=500
403 MOV DI, 600 DI=600
406 MOV AL, [SI] AL<-[SI]
408 INC SI SI=SI+1
409 MOV BL, [SI] BL<-[SI]
40B MUL BL AX=AL*BL
40D MOV [DI], AX AX->[DI]
40F HLT END

Problem – Write an ALP to multiply two 16-bit numbers where starting

address is 2000 and the numbers are at 3000 and 3002 memory address
and store result into 3004 and 3006 memory address.

Memory Mnemonics Operands Comment

2000 MOV AX, [3000] [AX] <- [3000]
2004 MOV BX, [3002] [BX] <- [3002]
2008 MUL BX [AX] <- [AX] * [BX]
200A MOV [3004], AX [3004] <- AX
200E MOV AX, DX [AX] <- [DX]
2010 MOV [3006], AX [3006] <- AX

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 114
 Memory Mnemonics Operands Comment
2014 HLT Stop

Problem – Write an ALP to divide a 16 bit number by an 8 bit number.

MNEMONICS COMMENT
MEMORY ADDRESS
0400 MOV SI, 500 SI <- 500
0403 MOV DI, 600 DI <- 600
0406 MOV BL, [SI] BL <- [SI]
0408 INC SI SI <- SI + 1
0409 MOV AX, [SI] AX <- [SI]
040B DIV BL AX <- AX / BL
040D MOV [DI], AX [DI] <- AX
040F HLT End of program

Explanation – Registers used AX, BL, SI, DI

Problem – Write an ALP to find out the sum of series of even numbers,
where numbers are stored from starting offset 500 and store the result at
offset 600.

MEMORY
MNEMONICS COMMENT
ADDRESS
400 MOV SI, 500 SI<-500
403 MOV CL, [SI] CL<-[SI]
405 INC SI SI<-SI+1
406 MOV CH, 00 CH<-00
408 MOV AL, 00 AL<-00
40A MOV BL, [SI] BL<-[SI]
40C TEST BL, 01 BL AND 01
40F JNZ 413 JUMP IF NOT ZERO
411 ADD AL, BL AL<-AL+BL
413 INC SI SI<-SI+1
JUMP TO 40A IF CX NOT
414 LOOP 40A
ZERO
416 MOV [600], AL AL->[600]
41A HLT END

Problem – Write an ALP to find sum of odd numbers in a given series

containing 8 bit numbers stored in a continuous memory location and store
the result in another memory The starting address of the program is 400.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 115
Address Mnemonics Comments
MOV SI, 500 SI<-500
MOV CL, [SI] CL<-[SI]
INC SI SI<-SI+1
MOV CH, 00 CH<-00
MOV AL, 00 AL<-00
MOV BL, [SI] BL<-[SI]
TEST BL, 01 BL.01
JZ 413 Jump to 413 memory location if zero flag is set
ADD AL, BL AL<-AL+BL
413 INC SI SI<-SI+1
jump to 40A memory location if content of CX is not
LOOP 40A
equal to zero
MOV [600],
[600], AL
AL
HLT end

Problem – Write an ALP to find average of n eight bit numbers.

OFFSET MNEMONICS COMMENT

400 MOV SI, 500 SI <- 500
403 MOV DI, 600 DI <- 600
406 MOV AX, 0000 AX = 0000
409 MOV CL, [SI] CL <- [SI]
40B MOV BL, CL BL <- CL
40D INC SI SI = SI + 1
40E ADD AL, [SI] AL = AL + [SI]
410 ADC AH, 00 AH = AH + 00 + cy
412 INC SI SI = SI + 1
413 DEC CL CL = CL – 1
415 JNZ 40E JUMP if ZF = 0
417 DIV BL AX = AX / BL
419 MOV [DI], AX [DI] <- AX
41B HLT Stop

Problem – Write an assembly language program for calculating the factorial

of a number using 8086 microprocessor

MNEMONICS COMMENTS

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 116
 MNEMONICS COMMENTS
MOV CX, [0500] CX <- [0500]
MOV AX, 0001 AX <- 0001
MOV DX, 0000 DX <- 0000
MUL CX DX:AX <- AX * CX
LOOP 040A Go To [040A] till CX->00
MOV [0600], AX [0600]<-AX
MOV [0601], DX [0601]<-DX
HLT Stop Execution

Problem – Write a program to convert Binary number to Grey code 8-bit

number where starting address is 2000 and the number is stored at 2500
memory address and store result into 2600 memory address.

Mnemonics Operands Comment

MOV AL, [2500] [AL] <- [2500]
MOV BL, AL [BL] <- [AL]
SHR AL, 01 Shift Right one time
XOR BL, AL [BL] <- [BL] @ AL
MOV [2600], BL [2600] <- [BL]
HLT Stop

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 117
 Interface diagram

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 118