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NC Launch

This document contains the summaries of 15 Verilog code labs involving basic digital logic circuits. The labs cover topics such as simple logic gates, decoders, adders, comparators, multiplexers, and their behavioral and dataflow modeling in Verilog. Test benches are provided to simulate and verify the behavior of each circuit. The results of simulating the circuits for different input patterns are also shown.

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Kamalpreet Kaur
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0% found this document useful (0 votes)
122 views40 pages

NC Launch

This document contains the summaries of 15 Verilog code labs involving basic digital logic circuits. The labs cover topics such as simple logic gates, decoders, adders, comparators, multiplexers, and their behavioral and dataflow modeling in Verilog. Test benches are provided to simulate and verify the behavior of each circuit. The results of simulating the circuits for different input patterns are also shown.

Uploaded by

Kamalpreet Kaur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Introduction to VLSI Systems (ECE6660)

Fall-2019

Simulation of Verilog Exercises from Mano Using


NC launch

Submitted by
Meghana Reddy Shaga
Gn7677
LAB 1: SIMPLE CIRCUIT
Verilog Code:

“SMPL_CIRCUIT.V”
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule

Test Bench Code:

“SMPL_CIRCUIT_TB.V”
module smpl_circuit_tb;
reg A,B,C;
wire x,y;
smpl_circuit
sc(A,B,C,x,y); initial
begin
#25 A=0; B=0; C=0;
#25 A=0; B=0; C=1;
#25 A=0; B=1; C=0;
#25 A=0; B=1; C=1;
#25 A=1; B=0; C=0;
#25 A=1; B=0; C=1;
#25 A=1; B=1; C=0;
#25 A=1; B=1; C=1;
end
initial
#200 $finish;
Endmodule
Results:
LAB 2: DELAY IN SIMPLE CIRCUIT
Verilog Code:

“CIRCUIT_WITH_DELAY.V”

module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y;


wire e;

and #(50) g1(e,A,B); or #(10) g3(x,e,y); not #(20) g2(y,C); endmodule

Test Bench Code:

“CIRCUIT_WITH_DELAY_TB.V”

module circuit_with_delay_tb; reg A,B,C;


wire x,y; circuit_with_delay cwd(A,B,C,x,y); initial begin

A=0; B=0; C=0; #100


A=0; B=0; C=1; #100
A=0; B=1; C=0; #100
A=0; B=1; C=1; #100
A=1; B=0; C=0; #100
A=1; B=0; C=1; #100
A=1; B=1; C=0; #100
A=1; B=1; C=1;
end
endmodule
Results:
LAB 3: BOOLEAN EQUATION
Verilog Code:

“CIRCUIT_BLN.V”

module circuit_bln
(x,y,A,B,C,D); input A,B,C,D; output x,y;
assign x = A | (B & C) | (~B & C); assign y = (~B & C) | (B & ~C & ~D); endmodule

Test Bench Code:

“CIRCUIT_BLN_TB.V”

module circuit_bln_tb;
reg A,B,C,D;
wire x,y;
circuit_bln cb(x,y,A,B,C,D); initial

begin
#25 A=0; B=0; C=0; D=0;
#25 A=0; B=0; C=0; D=1;
#25 A=0; B=0; C=1; D=0;
#25 A=0; B=0; C=1; D=1;
#25 A=0; B=1; C=0; D=0;
#25 A=0; B=1; C=0; D=1;
#25 A=0; B=1; C=1; D=0;
#25 A=0; B=1; C=1; D=1;
#25 A=1; B=0; C=0; D=0;
#25 A=1; B=0; C=0; D=1;
#25 A=1; B=0; C=1; D=0;
#25 A=1; B=0; C=1; D=1;
#25 A=1; B=1; C=0; D=0;
#25 A=1; B=1; C=0; D=1;
#25 A=1; B=1; C=1; D=0;
#25 A=1; B=1; C=1; D=1;
end
initial
#200 $finish;
Endmodule
Results:
LAB 4: BINARY ADDER (4 BIT)
Verilog Code:

“BINARY_ADDER.V”
module binary_adder(A, B, Result);
input [3:0] A;
input [3:0] B;
output [3:0] Result;
reg [3:0] Result;
always @ (A or B)
begin
Result <= A + B;
End
endmodule

Test Bench Code:

“BINARY_ADDER_TB.V”
module binary_adder_tb;
reg [3:0] A;
reg [3:0] B;
wire [3:0] Result;
binary_adder Adder(A,B,Result);
initial

begin
A <= 0; B<= 0; //case 0
#100 $display("Result=%b",Result);
A<= 6; B<= 1; //case 1
#100 $display("Result=%b",Result);
A <= 1; B<= 0; //case 2
#100 $display("Result=%b",Result);
A <= 10; B<= 10;//case 3 (overflow occur) #100 $display("Result=%b",Result);
end
endmodule
Results:
LAB 5: 2 to 4 DECODERS (Data Flow)
Verilog Code:

“DECODER_DF.V”

//Dataflow description of a 2-to-4-line decoder module decoder_df (A,B,E,D); input A,B,E;


output [0:3] D;

assign D[0] = ~(~A & ~B & ~E),


D[1] = ~(~A & B & ~E),
D[2] = ~(A & ~B & ~E),
D[3] = ~(A & B & ~E);
Endmodule

Test Bench Code:

“DECODER_DF_TB.V” module decoder_df_tb; reg A,B,E;


wire [0:3]D;

decoder_df
ddf(A,B,E,D); initial
begin
#25 A=0; B=0; E=0;
#25 A=0; B=0; E=1;
#25 A=0; B=1; E=0;
#25 A=0; B=1; E=1;
#25 A=1; B=0; E=0;
#25 A=1; B=0; E=1;
#25 A=1; B=1; E=0;
#25 A=1; B=1; E=1;
end
initial
#200 $finish;
endmodule
Results:
LAB 6: GATE LEVEL ANALYSIS OF DECODER
Verilog Code:

“DECODER_G1.V”

module decoder_g1(A,B,E,D); input A,B,E;


output [0:3]D;
wire

Anot,Bnot,Enot; not
n1 (Anot,A),
n2 (Bnot,B),
n3 (Enot,E); nand
n4 (D[0],Anot,Bnot,Enot), n5 (D[1],Anot,B,Enot), n6 (D[2],A,Bnot,Enot),
n7 (D[3],A,B,Enot); endmodule

Test Bench Code:

“DECODER_G1_TB.V”

module decoder_g1_tb;

reg A,B,E;
wire [0:3]D; decoder_g1
dg(A,B,E,D); initial
begin
#25 A=0; B=0; E=0;
#25 A=0; B=0; E=1;
#25 A=0; B=1; E=0;
#25 A=0; B=1; E=1;
#25 A=1; B=0; E=0;
#25 A=1; B=0; E=1;
#25 A=1; B=1; E=0;
#25 A=1; B=1; E=1;
end
initial
#200
$finish endmodule
Results:
LAB 7: ANALYSIS OF GATES
Verilog Code:

“ANALYSIS.V”
module analysis (A,B,C,F1,F2);
input A,B,C;
output F1,F2;
wire T1,T2,T3,F2not,E1,E2,E3;
or g1 (T1,A,B,C);
and g2 (T2,A,B,C);
and g3 (E1,A,B);
and g4 (E2,A,C);
and g5 (E3,B,C);
or g6 (F2,E1,E2,E3);
not g7 (F2not,F2);
and g8 (T3,T1,F2not);
or g9 (F1,T2,T3);
endmodule

Test Bench Code:

“ANALYSIS_TB.V”

module analysis_tb;
reg [2:0]D;
wire F1,F2;
analysis fig42(D[2],D[1],D[0],F1,F2); initial begin

D = 3'b000;

repeat(7)
#10 D = D + 1'b1;
end
initial
$monitor ("ABC = %b F1 = %b F2
=%b ",D, F1, F2);
Endmodule
Results:
LAB 8: HALF ADDER

Verilog Code:

“HALFADDER.V”

module halfadder (S,C,x,y); input x,y; output S,C;


xor (S,x,y);

and (C,x,y); endmodule

Test Bench Code:

“HALDADDER_TB.V”

module halfadder_tb; reg x,y;


wire S,C;
halfadder ha(S,C,x,y); initial begin

#100 x = 0; y = 0; #100 x = 0; y = 1; #100 x = 1; y = 0; #100 x = 1; y = 1; end

endmodule
Results:
LAB 9: 1-BIT FULL ADDER
Verilog Code:

“FULLADD1BIT.V”

module fulladd1bit (S,C,x,y,z); input x,y,z;


output S,C;
wire S1,D1,D2;

halfadder HA1 (S1,D1,x,y); halfadder HA2 (S,D2,S1,z); or g1(C,D2,D1);


endmodule

Test Bench Code:

“FULLADD1BIT_TB.V”

module fulladd1bit_tb;
reg x,y,z;
wire S,C;
fulladd1bit fa(S,C,x,y,z); initial

begin
x=0; y=00; z=0; #100 x=0; y=0; z=1; #100 x=0; y=1; z=0; #100 x=0; y=1; z=1; #100 x=1; y=0; z=0;
#100 x=1; y=0; z=1; #100 x=1; y=1; z=0; #100 x=1; y=1; z=1; end
endmodule
Results:
LAB 10: 4-BIT FULL ADDER
Verilog Code:

“FULLADD_4BIT.V”

module fulladd (cin,x,y,s,cout); input cin,x,y;


output s,cout;
assign s = x^y^cin;

assign cout =( x & y) | (x & cin) |( y & cin); endmodule


module adder4 ( carryin,x,y,sum,carryout);
input carryin;

input [3:0] x,y;


output [3:0] sum;
output carryout;
wire c1,c2,c3;
fulladd stage0 (carryin,x[0],y[0],sum[0],c1); fulladd stage1 (c1,x[1],y[1],sum[1],c2); fulladd stage2
(c2,x[2],y[2],sum[2],c3); fulladd stage3 (c3,x[3],y[3],sum[3],carryout); endmodule

Test Bench Code:

“FULLADD_4BIT_TB.V”

module fulladd_tb();
reg [3:0] x,y;
reg carryin;
wire [3:0] sum;
wire carryout;
adder4 a1 ( carryin,x,y,sum,carryout); initial

begin
$monitor($time,"SUM=%d",sum);
x = 4'b0000; y= 4'b0000;carryin = 1'b0; #20 x =4'b1111; y = 4'b1010;
#40 x =4'b1011; y =4'b0110;
#40 x =4'b1111; y=4'b1111;
#50 $finish;
end
endmodule
Results:
LAB 11: MAGNITUDE COMPARATOR
Verilog Code:

//Dataflow description of a 4-bit comparator module magcomp (A,B,ALTB,AGTB,AEQB);


input [3:0] A,B; output
ALTB,AGTB,AEQB; assign

ALTB = (A < B), AGTB = (A > B), AEQB = (A == B); Endmodule

Test Bench Code:

“MAGCOMP_TB.V”
module magcomp_tb;
reg [3:0] A,B;
wire ALTB, AGTB, AEQB;
magcomp compare(A,B,ALTB,AGTB,AEQB);
initial
begin
#100 A <= 0; B <= 0;
#100 A <= 6; B <= 1;
#100 A <= 1; B <= 0;
#100 A <= 10; B <= 10;
end
initial
#200 $finish;
Endmodule

Results:
LAB 12: 2x1 MULTIPLEXER
Verilog Code:

module mux2x1 (A,B,S,O); input A,B,S;


output O;
assign O = (S)? A:B; endmodule

Test Bench Code:

module mux2x1_tb;
reg A,B,S;
wire O;
mux2x1 mx(A,B,S,O);
initial
begin
S = 1; A = 0; B =1;
#20 A = 1; B = 0;
#20 S = 0;
#20 A = 0; B =1;
#20 A= 0; B=1;
end
initial
$monitor("select = %b A = %b B = %b OUT = %b time = %0d", S, A, B, O, $time);
Endmodule
Results:
LAB 13: 2x1 MULTIPLEXER Data Flow Analysis
Verilog Code:

“MUX2x1_DF.v”

module mux2x1_df (A,B,select,OUT); input A,B,select;


output OUT;
assign OUT = select ? A : B; endmodule

Test Bench Code:

“MUX2x1_DF_TB.v”
module mux2x1_df_tb;
reg TA,TB,TS; //inputs for mux
wire Y; //output from mux
mux2x1_df mx (TA,TB,TS,Y); // instantiate mux
initial
begin
TS = 1; TA = 0; TB =
1; #10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB =
1; end
initial
$monitor("select = %b A = %b B = %b OUT
= %b time = %0d",
TS, TA, TB, Y, $time);
Endmodule
Results:
LAB 14: 2x1 MULTIPLEXER Behavioral Analysis
Verilog Code:

“MUX2x1_BH.v”

module mux2x1_bh(A,B,select,OUT); input A,B,select;


output OUT;
reg OUT;

always @ (select or A or B)
if (select == 1) OUT =
A; else OUT = B;
Endmodule

Test Bench Code:

“MUX2x1_BH_TB.v”
module mux2x1_bh_tb;
reg A,B,select;
wire OUT;
mux2x1_bh mx(A,B,select,OUT);
initial
begin
select = 1; A = 0; B =
1; #10 A = 1; B = 0;
#10 select = 0;
#10 A = 0; B = 1;
end
endmodule
Results:
LAB 15: 4x1 MULTIPLEXER
Verilog Code:

module mux4_1_tb;
reg [3:0] Input0_t, Input1_t, Input2_t, Input3_t;
reg [1:0] Sel_t;
wire [3:0] Data_out_t;
mux4_1 Mux(Input0_t, Input1_t, Input2_t, Input3_t, Sel_t, Data_out_t); initial
begin
// assign values to input register
Input0_t <= 0;
Input1_t <= 1;
Input2_t <= 2;
Input3_t <= 3;
//case 0 - Input0 value should be display on output
Sel_t <= 0;
#10 $display("Data_out_t = %b", Data_out_t);
//case 1 - Input1 value should be display on output
Sel_t <= 1;
#10 $display("Data_out_t = %b", Data_out_t);
//case 2 - Input2 value should be display on output
Sel_t <= 2;
#10 $display("Data_out_t = %b", Data_out_t);
//case 3 - Input3 value should be display on output
Sel_t <= 3;
#10 $display("Data_out_t = %b", Data_out_t);
// reassign value to input register Input0 and display on output Input0_t = 8;
Sel_t <= 0;
#10 $display("Data_out_t = %b", Data_out_t);
// reassign value to input register Input0 and display on output Input0_t = 4;
Sel_t <= 0;
#10 $display("Data_out_t = %b", Data_out_t);
end
endmodule

Test Bench Code:

module mux4_1(Input0, Input1, Input2,Input3, Sel, Data_out); input [3:0] Input0;


input [3:0] Input1;
input [3:0] Input2;

input [3:0] Input3;


input [1:0] Sel;
output [3:0] Data_out;
reg [3:0] Data_out;
// constant declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @ (Sel or Input0 or Input1 or Input2
or Input3)
begin
case(Sel)
S0: begin
Data_out <= Input0;
end

S1: begin
Data_out <= Input1; end
S2: begin
Data_out <= Input2; end
S3: begin
Data_out <= Input3; end
endcase
end
endmodule

Results:
LAB 16: D LATCHES
Verilog Code:

//Description of D latch (See Fig.5-6)


module D_latch
(q,d,e); output q;
input d,e;

reg q;
always @ (e or
d) begin
if (e) q = d; //Same as: if (control = 1) end
endmodule

Test Bench Code:

module D_latch_tb;
reg e;
reg d;
wire q;
D_latch uut (.e(e),.d(d),.q(q) );
initial begin
d = 0;
e = 0;

end
always #30 e=~e; always #50 d=~d; initial #1000 $stop; endmodule
Results:
LAB 17: D Flip Flop
Verilog Code:

//D flip-flop
module d_ff(q,clk,n_rst,din);
output q;
input clk,din,n_rst;
reg q;
always @(posedge clk or negedge n_rst) begin
if(!n_rst)
q <= 1'b0;
else
q <= din;
end
endmodule

Test Bench Code:

module d_ff_tb;
reg clk, din, n_rst;
wire q, d1, clk1;
d_ff df1 (q, clk, n_rst,din);
assign d1=din;
assign clk1=clk;
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
din = 1'b0;
n_rst = 1'b1;
#20 n_rst = 1'b0;
#10 din = 1'b1;
#20 n_rst = 1'b1;
#18 din = 1'b0;
#1 din = 1'b1;
#20 din = 1'b0;
#10;

end

endmodule
Results:
LAB 18: T Flip Flop
Verilog Code:

//T flip-flop gates


module t_ff(q,qbar,clk,tin,rst); output q,qbar;
input clk,tin,rst;
reg tq;
always @(posedge clk or negedge rst) begin
if(!rst)
tq <= 1'b0;
else
begin
if (tin)
tq <= ~tq;
end
end
assign q = tq;
assign qbar = ~q;
endmodule

Test Bench Code:

module t_ff_tb;
reg clk,tin,rst;
wire q,qbar;
t_ff t1(q,qbar,clk,tin,rst);
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
rst = 1'b0; tin = 1'b0;
#30 rst = 1'b1;
#10 tin = 1'b1;
#205 tin = 1'b0;
#300 tin = 1'b1;
#175 tin = 1'b0;
#280 rst = 1'b0;
#20 rst = 1'b1;
#280 tin = 1'b1;
#10 ;

end
initial
#2000 $finish; Endmodule
Results:
LAB 19: J-K FLIP FLOP
Verilog Code:

module jk_ff(q,q_bar,clk,j,k);
output q,q_bar;
input clk,j,k;
reg tq,q,q_bar;
always @(clk)
begin
if (!clk)
begin
if (j==1'b0 && k==1'b1)
tq <= 1'b0;
else if (j==1'b1 && k==1'b0)
tq <= 1'b1;
else if (j==1'b1 && k==1'b1)
tq <= ~tq;
end
if (clk)

begin
q <= tq; q_bar <= ~tq; end
end
endmodule

Test Bench Code:

module jk_ff_tb;
reg clk,j,k;
wire q,q_bar;
wire clk2,j2,k2;
jk_ff inst(q,q_bar,clk,j,k); assign clk2=clk;
assign j2=j;
assign k2=k;
initial clk = 1'b0;
always #10
clk = ~clk;
initial
begin
j= 1'b0; k= 1'b0;
#60 j= 1'b0; k= 1'b1;
#40 j= 1'b1; k= 1'b0;
#20 j= 1'b1; k= 1'b1;
#40 j= 1'b1; k= 1'b0;
#5 j= 1'b1;
#20 j= 1'b1;
#10;end
endmodule
Results:
LAB 20: S-R FLIP FLOP
Verilog Code:

module sr_ff(q,qbar,s,r,clk); output q,qbar;


input clk,s,r;
reg tq;

always @(posedge clk


) begin
if (s == 1'b0 && r ==
1'b0) tq <= tq;
else if (s == 1'b0 && r ==
1'b1) tq <= 1'b0;
else if (s == 1'b1 && r ==
1'b0) tq <= 1'b1;
else if (s == 1'b1 && r ==
1'b1) tq <= 1'bx;
end
assign q = tq;
assign qbar = ~tq;
endmodule

Test Bench Code:

module
sr_ff_tb; reg
clk,s,r; wire
q,qbar; wire
s1,r1,clk1;
sr_ff sr1(q,qbar,s,r,clk);
assign s1=s;
assign r1=r;
assign clk1=clk;
initial
clk = 1'b0;
always

#10 clk = ~clk; initial


begin
s = 1'b0; r = 1'b0; #30 s = 1'b1;

#29 s = 1'b0;
#1 r = 1'b1;
#30 s = 1'b1;
#30 r = 1'b0;
#20 s = 1'b0;
#19 s = 1'b1;
#200 s = 1'b1; r =
1'b1; #50 s = 1'b0; r =
1'b0; #50 s = 1'b1; r =
1'b0; end

initial
#500 $finish; Endmodule

Results:

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