(Supplement this write up with class notes)

BASIC PROCESSOR-0
(Developed from 4-bit registers)
Instructions non-MRI – IN ; OUT ; MOV A,B ; MOV B,A ; INC ; DEC; CMP; HLT;
MRI - LDA adr ; STA adr ; ADD adr; JMP adr ; JZ adr;
(i)RAM – 16*4 bit, ROM - ; ALL registers of 4-bit size (6 clocks needed – 4 fetch clock and 2 for execution)
(ii) RAM – 256*4bit, ROM- ? , PC, TMP and MAR are 8-bit ,rest of 4-bit (8 clocks needed – 6 fetch clock and 2 for execution)

BASIC PROCESSOR-I (hard-wired)

BASIC PROCESSOR-II (soft-wired)

(control signal connections discussed in the class)

Hardware components-
Memory (2048*16bit)
Instruction register (IR) 16bit
MDR,AC -16bit
MAR, PC -11bit
CAR, SBR- 8bit
Input output registers- INP, OUP - 8bit
ALU works with AC
Input and Output operation also set/reset flags R and W, F is general purpose interrupt
( R sets when external device write data in IN port. Processor resets R when it reads IN port)
(W is reset by processor when new data is written in OUT port. W is set by external device after it reads OUT port)

Instruction set
Memory reference instructions(MRI)-
direct and indirect -AND, OR,XOR,ADD, SUB,ADM,LDA, STA, BUN,BZ,BN (branch unconditional,branch zero, branch negative)

direct only-BSA (branch and save return address) , ISZ (increment memory and skip next instruction if memory becomes zero)

Non Memory reference instructions-

CLR (AC=0) ,CMP (AC=1's complement of A) , SHL (AC shift left) , SHR (AC shift right with sign) ,IN,OUT, HLT (disable sequence
generator) (IN and OUT has been implemented to skip next instruction if R/W flag is set)
Three external interrupts – R(with IN port) , W (with OUT port) and F (general purpose interrupt)
Brief description:
micro-instructions are stored in controller memory as routines. Each macro instruction has its own (unique) routine
(group of micro instructions) in controller memory. Addressing these routines and branching from one routine to other
needs suitable address decoding.
Following steps are needed to decode a instruction-
fetch a instruction ; decode instruction ; execute instruction

Instruction set architecture (ISA)-

Instruction format
d15 d0
I OPCODE EA
1 4 11 ← bits

Instruction set (12 bit offset not shown)

11-bit addr 11-bit addr
00000 ADD direct 10000 ADD indirect
00001 SUB direct 10001 SUB indirect
00010 AND direct 10010 AND indirect
00011 OR direct 10011 OR indirect
00100 XOR direct 10100 XOR indirect
00101 STA direct 10101 STA indirect
00110 LDA direct 10110 LDA indirect
00111 ADM direct 10111 ADM indirect
01000 BZ direct 11000 BZ indirect
01001 BUN direct 11001 BUN indirect
01010 BN direct 11010 BN indirect
01011 CMP direct 11011 BSA direct **
01100 SHL direct 11100 ISZ direct **
01101 SHR direct 11101 IN direct **
01110 CLR direct 11110 OUT direct **
01111 INC direct 11111 HLT direct **

21 instructions – 11 instructions use address (11-bit) as direct or indirect mode to calculate effective address of operand. (instructions with I=0
or 1, the MSB)
2 instructions use direct address mode and remaining 8 instructions are not using 11-bit address.
(For non MRI , 11-bit address can be further decoded to support more non instruction. NOT INCLUDED). **
A special logic ckt is used to map (using d3-d0(opcode bits) to logic ckt. ) for 5 instructions (opcode > 11010 ) CAR[6]=1.

To decode/execute a instruction we need 4 micro instructions in general. Each micro instruction has at most three micro-operations and other
logic/address bits. Therefore 84 (21*4)rows are required in control ROM to store these micro instructions. we take 256 row ROM. The width of
each row is 22 bits.

Micro instruction format

d21 d0
F1 F2 F3 CD BR AD
4 3 2 3 2 8 <-bits

Bits of each Field of micro instruction is connected to suitable size decoder. As only one micro-Control signal can be
activated by one decoder at a time . Multiple micro-control signals (micro-operations) required simultaneously in a
micro-instruction are placed in different field.
F1 micro operations F2 micro operations
Register transfer symbol Register transfer symbol
0000 NOP 000 NOP
0001 AC<- AC+MDR ADD 001 MAR<-MDR DRTAR
0010 AC<- AC-MDR SUB 010 MAR<-PC PCTAR
0011 AC<- AC | MDR OR 011 [MAR]<-MDR WRITE
0100 AC<- AC &MDR AND 100 MDR<-[MAR] READ
0101 AC<- AC+MDR XOR 101 MDR <-AC ACTDR
0110 AC<-complement COM 110 MDR<-MDR+1 INCDR
0111 AC<- shift left SHL 111 PC<-7FFh ,INTF=0 INTPC
1000 AC<- shift right SHR
1001 AC <-0 CLRAC
1010 AC<-AC+1 INCAC F3 micro operations
1011 AC<-MDR DRTAC Register transfer symbol
1100 Inr <-AC,R=0 IRTAC 00 NOP
1101 AC->outr,W=0 ACTOR 01 MDR <-PC PCTDR
1110 PC <-MAR ARTPC 10 PC<-PC+1 INCPC
1111 AR<-7FEh INTAR 11 Clock disabled HLT

The HLT signal deactivates the system clock . System can be reset by external reset button that sets the PC=00 and CAR(IR) to FC h (11111100).
(Same for Power on)

There are 8 flags taken into consideration. There status decide the condition/ flow of microcodes.
CD (condition)
bits condition flag meaning
000 Always 1 U Unconditional branch
001 DR(15) I Indirect opcode
010 AC(15) S Sign bit
011 AC=0 Z Zero value in AC
100 carry C Carry bit from add,sub operation
101 INF R Input port bit , set when new data arrives,reset when read by system
110 OUTF W output port bit , reset when new data written ,set when read by external device
111 INTF F h/w interrupt,current PC is stored at 7FEh , and PC is loaded with 7FFh, reset flag

Interrupt handling-
INTAR micro operation loads 7FEh TO MAR, INTPC loads 7FFh to PC, the address of interrupted programme is stored at 7FEh. Address of
ISR at 7FFh, (branching instruction , normally indirect branch instruction that is BUN xx)
Instruction IN works only if R=1 (read from input port)
Instruction OUT works only if W=1 (write to output port)

BR (branch)
bits
00 IF CD=1 (true) CAR<- AD JMP at AD
ELSE CAR<-CAR+1
01 IF CD=1(true) SBR<-CAR+1 ,CAR<- AD, CALL AD
ELSE CAR<-CAR+1
10 CAR<-SBR RET
11 CAR[5-2]=DR[14-11], CAR[7,6,1,0]=0 MAP* (decoding)
*For opcode > than 11010 , CAR bit 6 is set 1

MAR <- DR[10-0] , PC<- DR[10-0]

AD is 8 bits address, pointing to next memory location in controller memory( ROM).
micro-instructions-
Entries in controller memory (addresses in hexadecimal)
@00 (ADD)
NOP NOP NOP I call indrct
NOP READ NOP U JMP next
ADD NOP NOP U JMP fetch
Similar codes for SUB, AND, OR and XOR (@ 04,@08,@0C and @10)

@ 14 (STA) @18 (LDA)

NOP NOP NOP I call indrct NOP NOP NOP I call indrct
NOP ACTDR NOP U JMP next NOP READ NOP U JMP next
NOP WRITE NOP U JMP fetch DRTAC NOP NOP U JMP fetch

@1C (ADM) ( [MAR] <- AC +[MAR] )

NOP NOP NOP I call indrct
NOP READ NOP U JMP next
ADD NOP NOP U JMP @16

@20 (BZ) @28 (BN)

NOP NOP NOP Z JMP @22 NOP NOP NOP S JMP @2A
NOP NOP NOP U JMP fetch NOP NOP NOP U JMP fetch
NOP NOP NOP I call indrct NOP NOP NOP I call indrct
ARTPC NOP NOP U JMP fetch ARTPC NOP NOP U JMP fetch

@24 (BUN)
NOP NOP NOP I call indrct
ARTPC NOP NOP U JMP fetch

@2C (CMP) @7C (HLT)

CMP NOP NOP U JMP fetch NOP NOP HLT
Similar codes for SHL,SHR,CLR and INC (@30,@34,@38,@3C )

@6C (BSA) @70 (ISZ)

NOP NOP PCTDR U JMP next NOP READ NOP U JMP next
ARTPC NOP NOP U JMP next NOP INCDR NOP U JMP next
NOP WRITE INCPC U JMP fetch NOP WRITE NOP U JMP next
DRTAC NOP NOP U JMP @84

@74 (IN) @78 (OUT)

NOP NOP NOP R JMP @4A NOP NOP NOP W JMP @4E
NOP NOP NOP U JMP fetch NOP NOP NOP U JMP fetch
IRTAC NOP INCPC U JMP fetch ACTOR NOP INCPC U JMP fetch

@84 Int @ 88
NOP NOP NOP Z JMP @86 NOP NOP PCTDR U JMP next
NOP NOP NOP U JMP fetch INTAR NOP NOP U JMP next
NOP NOP INCPC U JMP fetch NOP WRITE NOP U JMP next
NOP INTPC NOP U JMP @FD

fetch @ FC Indrct @80

NOP NOP NOP F JMP @88 NOP READ NOP U JMP next
NOP PCTAR NOP U JMP next NOP DRTAR NOP U RET
NOP READ INCPC U JMP next
NOP DRTAR NOP U MAP