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Sheet 1 - RTL Part1

This document contains 9 questions about computer architecture concepts like register transfer statements, block diagrams of hardware implementations, bus systems, and memory operations. Specifically: 1. It asks to draw the block diagram for a register transfer statement that swaps the values of two registers. 2. It asks to draw the hardware implementation of register transfers dictated by timing variables using registers, multiplexers, and control signals. 3. It asks to represent a conditional control statement using register transfer statements and control functions. 4. It asks how the bus system in a figure would need to be modified to allow transfers between any registers. 5. It asks to draw a bus system diagram using three-state buffers and a decoder instead

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230 views2 pages

Sheet 1 - RTL Part1

This document contains 9 questions about computer architecture concepts like register transfer statements, block diagrams of hardware implementations, bus systems, and memory operations. Specifically: 1. It asks to draw the block diagram for a register transfer statement that swaps the values of two registers. 2. It asks to draw the hardware implementation of register transfers dictated by timing variables using registers, multiplexers, and control signals. 3. It asks to represent a conditional control statement using register transfer statements and control functions. 4. It asks how the bus system in a figure would need to be modified to allow transfers between any registers. 5. It asks to draw a bus system diagram using three-state buffers and a decoder instead

Uploaded by

sad bird
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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E1222 Computer Architecture 2020

Sheet 1
1.* Show the block diagram of the hardware that implements the following register transfer
statement:
yT2 : R2 ← R1, R1 ← R2

2.* The outputs of four registers, R0, R 1, R2, and R3, are connected through 4-to-1-line
multiplexers to the inputs of a fifth register, R5. Each register is eight bits long. The
required transfers are dictated by four timing variables T0 through T3 as follows:
T0 : R5←R0
T1 : R5←R1
T2 : R5←R2
T3 : R5←R3
The timing variables are mutually exclusive, which means that only one variable is equal
to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing
the hardware implementation of the register transfers. Include the connections necessary
from the four timing variables to the selection inputs of the multiplexers and to the load
input of register R0.

3. Represent the following conditional control statement by two register transfer statements
with control functions.
If (P = 1) then (R1 ← R2) else if (Q = 1) then (R1 ← R3)

4. What has to be done to the bus system of Fig. 4-3 to be able to transfer information from
any register to any other register? Specifically, show the connections that must be included
to provide a path from the outputs of register C to the inputs of register A.

5.* Draw a diagram of a bus system similar to the one shown in Fig. 4-3, but use three-
state buffers and a decoder instead of the multiplexers.

1 Electrical Dept., Benha Faculty of Engineering – Benha University


E1222 Computer Architecture 2020
6.* A digital computer has a common bus system for 16 registers of 32 bits each. The bus
is constructed with multiplexers.
a) How many selection inputs are there in each multiplexer?
b) What sizes of multiplexers are needed?
c) How many multiplexers are there in the bus?
7. The following transfer statements specify a memory. Explain the memory operation in
each case.
a) R2← M[AR]
b) *M[AR] ← R3
c) *R5← M[R5]
8. What is wrong with the following register transfer statements?
̅̅̅̅, AR← 0
a) *xT: AR←AR
b) yT: R1←R2, R1← R3
c) zT: PC←AR, PC←PC+1
9. Write the RTL that describes the following system

2 Electrical Dept., Benha Faculty of Engineering – Benha University

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