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1 Serialadd

The document contains Verilog code for an n-bit serial adder system. It includes: 1) Code for the serial adder datapath module that performs serial addition of n-bit inputs and generates the sum and carry outputs. 2) Code for a finite state machine-based controller module that controls the loading, shifting and clearing of the adder. 3) A top module that instantiates the datapath and controller modules and connects their ports. 4) A test bench module for simulation that applies inputs and checks outputs of the serial adder system.

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ayesha
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123 views9 pages

1 Serialadd

The document contains Verilog code for an n-bit serial adder system. It includes: 1) Code for the serial adder datapath module that performs serial addition of n-bit inputs and generates the sum and carry outputs. 2) Code for a finite state machine-based controller module that controls the loading, shifting and clearing of the adder. 3) A top module that instantiates the datapath and controller modules and connects their ports. 4) A test bench module for simulation that applies inputs and checks outputs of the serial adder system.

Uploaded by

ayesha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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UNIVERSITY OF ENGINEERING AND TECHNOLOGY,

TAXILA

DEPARTMENT OF ELECTRONICS ENGINEERING


FPGA – BASED DESIGN

ASSIGNMENT NO: 01
N-BIT SERIAL ADDER
SUBMITTED TO: DR. SYED AZHAR ALI ZAIDI
SUBMITTED BY: AYESHA FARMAN
ROLL NO: 19-ENC-MS-03
FSM BASED CONTROLLER FOR n-BIT SERIALADDER

VERILOG HDL CODE OF SERIAL ADDER

module serial_add
//for parameterized code
#(parameter N = 8)
(
input wire clk,syn_clr,
input wire shft,load_reg,cnt_en,
input wire [N-1:0]din_A, din_B,
output wire [N-1:0]sum,
output reg cout,
output wire max_tick
);
// Signal Declaration
reg a=1'b0,b=1'b0;
reg cout_s=0;
reg sum_s=0;
reg [N-1:0]i1=0;
reg [N-1:0]i2=0;
reg [N-1:0] C_in=0;
reg s_reg;
reg s_next;
// State Register
always@(posedge clk)
if(syn_clr)
s_reg <= 1'b0;
else
s_reg <= cout_s;
// Next state logic
always@(posedge clk)
begin
if(load_reg)
begin
i1 <= din_A;
i2 <= din_B;
end
else if (shft)
begin
a = i1[0];
b = i2 [0];
i1 = {1'b0, i1[N-1:1]}; // shifting using concatenation
i2 = {1'b0, i2[N-1:1]};
C_in <= {sum_s,C_in[N-1:1]};
end
end
//
always @ *
{cout_s,sum_s} = a + b + s_reg;
//
always@*
cout = s_reg;
assign sum = C_in;
endmodule

VERILOG HDL CODE OF CONTROLLER


module controller_s(
input wire clk, reset,
input wire data_ready,max_tick,
output reg syn_clr,shft,load_reg,count_en,op_ready
);
// symbolic state declaration
localparam [1:0] s0=2'b00,
s1=2'b01,
s2=2'b10;
// declaring registers
reg [1:0] state_reg, state_next;
// State Register
always@( posedge clk, posedge reset)
if(reset)
state_reg<= s0;
else
state_reg<=state_next;
// Next state
always@(posedge clk)
begin
state_next= state_reg;
//default values
syn_clr=1'b1;
load_reg=1'b0;
count_en=1'b0;
op_ready=1'b0;
shft=1'b0;
case(state_reg)
s0: // first state
begin
if(data_ready)
begin
state_next=s1;
load_reg=1'b1;
end
end
s1:
begin
syn_clr=1'b0;
count_en=1'b1;
shft=1'b1;
if(max_tick)
begin
state_next=s2;
syn_clr=1'b1;
op_ready=1'b1;
end
end
s2:
state_next=s0;
default: state_next=s0;
endcase
end
endmodule
VERILOG HDL CODE OF COMPLETE SYSTEM
module top_serial(
input wire data_ready,clk,reset,
input wire [7:0]din_A,din_B,
output wire [7:0]sum,
output wire cout,
output wire op_ready
);
//signal declaration
wire shft,load_reg,max_tick,syn_clr,count_en;
//instantiation of datapath and controller
serial_add #(.N(8))
TOP1
(
.clk(clk),
.syn_clr(syn_clr),
.shft(shft),
.load_reg(load_reg),
.din_A(din_A),
.din_B(din_B),
.sum(sum),
.cout(cout));
controller_s TOP2
(
.clk(clk),
.reset(reset),
.data_ready(data_ready),
.max_tick(max_tick),
.syn_clr(syn_clr),
.load_reg(load_reg),
.op_ready(op_ready),
.count_en(count_en),
.shft(shft));
endmodule

SCHEMATICS

TEST BENCH
module tb();
localparam T=20;
reg data_ready,clk,reset;
reg [7:0]din_A,din_B;
wire [7:0]sum;
wire cout;
wire op_ready;
// instantiation
top_serial TB(
.sum(sum),
.data_ready(data_ready),
.clk(clk),
.reset(reset),
.din_A(din_A),
.din_B(din_B),
.op_ready(op_ready),
.cout(cout)
);
//clock
always
begin
clk=1'b1;
#(T/2);
clk=1'b0;
#(T/2);
end
//reset
initial
begin
reset= 1'b1;
#(T/2);
reset= 1'b0;
end
//values
initial
begin
data_ready=1'b0;
#(T);
data_ready=1'b1;
din_A=8'b00000011;
din_B=8'b00000001;
#(15*T);
$stop;
end
endmodule

SIMULATIONS

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