HARI CHANDANA KARNAM

EEE/CSC-280

ASSIGNMENT-4

Question 1:

Describe various DRAM performance improvement techniques. If the goal of your system is to have low
power high bandwidth with a little compromise in latency what kind of optimization in performance
and power, you would choose and what you would ignore?

 Multiple accesses to same row (increases bandwidth)

separate column addresses had to be sent for each transfer with a delay after each new set of
column addresses. Hence DRAMs added timing signals that allow repeated accesses to the row
buffer without another row access time.
 Synchronous DRAM (increases bandwidth but consumes low power due to voltage dropped)
Reduce overhead to synchronize with the controller. The second major change was to add a clock
signal to the DRAM interface, so that the repeated transfers would not bear that overhead
 Wider interfaces (since it must constantly refresh to hold the data, it consumes more power)
DRAMS are made wider
 Double Data Rate (increases bandwidth but consumes low power due to voltage dropped)
Transfer data on both the rising edge and falling edge of the DRAM clock signal, thereby doubling
the peak data rate.
 Multiple banks on each DRAM device(increase bandwidth but consumes more power)
Dedicated cache bank for instruction and Data increases the performance bandwidth.

Since, Low power high bandwidth, increased performance and low power consumption are on high
priority on my system, I would choose Synchronous DRAMs and DDRs ignoring other optimization
techniques.

Question 2:

Describe how architects can provide security and privacy through Virtual Machine Architecture and
Virtual memory. What are the main requirements that an architect must fulfill to create a robust virtual
machine to prevent security lapses ?

1. Page-based virtual memory, including a translation lookaside buffer that caches page table entries, is
the primary mechanism that protects processes from each other.
2. Provide at least two modes, indicating whether the running process is a user process or an operating
system process. This latter process is sometimes called a kernel process or a supervisor process.
3. Provide a portion of the processor state that a user process can use but not write. This state includes
a user/supervisor mode bit, an exception enable/disable bit, and memory protection information.
Users are prevented from writing this state because the operating system cannot control user
processes if users can give themselves supervisor privileges, disable exceptions, or change memory
protection.
4. Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice
versa. The first direction is typically accomplished by a system call, implemented as a special
instruction that transfers control to a dedicated location in supervisor code space. The PC is saved
from the point of the system call, and the processor is placed in supervisor mode. The return to user
mode is like a subroutine return that restores the previous user/supervisor mode.
HARI CHANDANA KARNAM
EEE/CSC-280

5. Provide mechanisms to limit memory accesses to protect the memory state of a process without
having to swap the process to disk on a context switch.

Question 3:
A) Compare the access times of 64 KB caches with 64-byte blocks and a single bank. What are the
relative access times of two-way and four way set associative caches in comparison to a direct mapped
organization?
For Hit time: Assume the ratio of 1way : 2way : 4w ay as 1: 1.16 : 1.38
For Miss rate refer to : Appendix B: Table/Figure B 8 on page B-24
Miss penalty is : 12 times the access time for the faster L1 cache.

The access time for the faster L1 cache is assumed to be 1.

Access time = Hit time + (Miss Rate * Miss Penalty)

1-way Access time = 1 + (0.037*12) = 1.44
2-way Access time = 1.16 + (0.031*12) = 1.532
4-way access time = 1.38 + (0.030*12) = 1.74

Ratio of access time of 2-way = 1.532/1.44 = 1.061

Ratio of access time of 4-way = 1.74/1.44 = 1.205

B) Now assume a different kind of SPEC program with miss rate different than the one in appendix B.
Direct mapped: capacity misses are twice as mentioned in Appendix B.B-24 of the book
2 way: conflict misses are 3 times as much as mentioned in Appendix B : B-24 of the book
4 way: conflict misses are 1.5 times as much as mentioned in Appendix B : B-24 of the book

Which associativity option Is better for the new size cache?

Miss rate 1 way = (0.0001 + 2(0.028) + 0.008) = 0.0641

Miss rate 2 way = (0.0001 + 0.028 + 3(0.003)) = 0.0371
Miss rate 4 way = (0.0001 + 0.028 + 1.5(0.001)) = 0.0296

Access time = Hit time + (Miss Rate * Miss Penalty)

1-way Access time = 1 + (0.0641*12) = 1.7692
2-way Access time = 1.16 + (0.0371*12) = 1.6052
4-way access time = 1.38 + (0.0296*12) = 1.7352

2 Way associative set has the low access time and hence it is considered better option for the new size
cache.

C) Select the associativity with best access time from problem A and now change the cache size to
128Kb. Hit time ratio is twice as much as 64Kb. What is the access time of 128Kb cache? Which option is
better?

1-way access time = 2 + (0.02*12) = 2.252

Thus 1-way Access time is better.
HARI CHANDANA KARNAM
EEE/CSC-280

Question 4:

Whenever a computer is idle, we can either put it in stand by (where DRAM is still active) or we can let
it hibernate. Assume that, to hibernate, we must copy just the contents of DRAM to a nonvolatile
medium such as Flash. If reading or writing a cache line of size 64 bytes to Flash requires 2.56 μJ and
DRAM requires 0.5 nJ, and if idle power consumption for DRAM is 1.6 W (for 8 GB), how long should a
system be idle to benefit from hibernating? Assume a main memory of size 8 GB.

Hint: Hibernating will be useful when the static energy saved in DRAM is at least equal to the energy
required to copy from DRAM to Flash and then back to DRAM.
Time = total power required to hibernate and wake up / total idle time power

Reading or writing a cache line of size 64 bytes to Flash requires 2.56 μJ.
2.56∗106 ∗8∗10−9
Energy required to read and write into Flash = 64
J = 320 J

Reading or writing a cache line of size 64 bytes to DRAM requires 0.5 nJ

0.5∗109 ∗8∗10−9
Energy required to read and write into DRAM = J = 0.0625 J
64

Idle power consumption for DRAM is 1.6 W (for 8 GB)

Time = total power required to hibernate and wake up / total idle time power

2∗(320+0.0625)𝐽
Time = = 400.08 s
1.6 𝐽/𝑠