HARI CHANDANA KARNAM

EEE/CSC-280

ASSIGNMENT-3

Question 1: What are the different categories of Cache misses? Explain briefly.

When a cache cannot find a memory requested by the processor, it results in cache miss. Cache misses
are briefly classified into three, they are
 Compulsory—Every first access to a block results in a cache miss. The block must be brought into
the cache for the very first time. Compulsory cache misses occur even if the size of the Cache is
infinite.
 Capacity—Cache cannot contain all the blocks needed because of the finite size of the cache. So,
they are discarded and retrieved during execution of a program. This results in capacity misses.
 Conflict—If the block placement strategy is not fully associative, conflict misses will occur because
a block may be discarded and later retrieved if multiple blocks map to its set and accesses to the
different blocks are intermingled.

Question 2: Compare and contrast the multi-level cache to multi banked cache. (Explain what multi-
level and multi banked cache are briefly, what are few similarities and difference between them.)

 Multi-level Cache : Adding multiple levels of cache between the original processor cache and main
memory is called multi-level caching.
 Multi-banked Cache : Instead of treating the cache as a single block, it is divided into independent
banks that can support simultaneous accesses.

Similarities :
 Power – multi banked cache and Multi-level consumes lower power.
 Miss penalty - multi banked cache and Multi-level reduces miss penalty.

Differences:
*modern micro processors use a combination of multi-banked in L1 and multi-level in memory
system.
multi-level cache multi-banked cache
Slow processing because of same cache for Faster access time because of simultaneous
both data and instruction. (applies only for accesses of instruction and data.
unified cache in multi-level level)
Increased on-chip area so more hardware. Fewer ports and less hardware.

Question 3: Describe any two optimization techniques that can reduce hit time without compromising
power.

 Small and Simple First-Level Caches - lower Hit Time and low Power consumption.
use of lower levels of associativity can reduce both hit time and power.
 Way prediction – lower hit time and low power consumption
This approach saves power when the way prediction is correct but adds significant time on a way
misprediction, since the access, not just the tag match and selection, must be repeated.
HARI CHANDANA KARNAM
EEE/CSC-280

Question 4: Associate one of these positive and negative attributes with each of these optimization
techniques that makes most sense. There is more than one correct answer in some cases.

Positive: Lower hit time / Lower miss penalty/ Lower miss rate/ Low cost
Negative: Higher hit time/ Higher miss penalty/ Higher miss rate/ Higher cost.

1. Larger block size: lower miss rate but higher miss penalty.
2. Higher associativity: Lower miss rate but higher hit time.
3. Way Prediction: lower hit time but higher cost.
4. Multi banked Caches: low miss penalty but high cost
5. Merging Write Buffer: lower miss penalty high cost.
6. Compiler Optimizations: lower miss rate.

Question 5: If you are designing a memory organization for low power low cost application like PMDs
and you can only budget for 3 out of the 6 basic optimization and 5 out of the 10 advanced optimization
techniques to satisfy the cost/power/performance requirements what would you choose and why ( one
line explanation for each technique chosen)?

PMD’s are designed in such a way that it is faster, consumes low power, takes smaller size and cost
efficient. I would choose the following basic optimization techniques

 Giving priority to read misses over writes to reduce miss penalty – reduces miss penalty without
having greater effect on power consumption.
 Multilevel caches to reduce miss penalty – more power efficient.
 Avoiding address translation during indexing of the cache to reduce hit time – makes the device
faster as it has lower hit time.

I would also choose these following advanced optimized techniques –

 Small and Simple First-Level Caches - lower Hit Time and low Power consumption
 Way prediction – lower hit time makes device faster and low power consumption
 Multi banked Caches – increased cache band width with lower power consumption.
 Merging write buffer - uses the memory more efficiently as multi word writes are faster.
 Compiler optimization – increased performance with low power consumption.