COMSATS University Islamabad (CUI)

Department of Electrical and Computer Engineering

Computer Organization (CPE 343)
Assignment 4

Marks: 100 Due Date: 23/12/2019

Instructor: Dr. Sana Shuja Section: BCE

Instructions:
 Read the questions carefully and try to attempt/answer to the point.

Q1: If the time for an ALU operation can be shortened by 25% (compared to the description in
table below);

a. Will it affect the speedup obtained from pipelining? If yes, by how much? Otherwise, why?

b. What if the ALU operation now takes 25% more time?

Solution:

a. Shortening the ALU operation will not affect the speedup obtained from pipelining. It would
not affect the clock cycle.

b. If the ALU operation takes 25% more time, it becomes the bottleneck in the pipeline. The
clock cycle needs to be 250 ps. The speedup would be 20% less.
Q2: A computer architect needs to design the pipeline of a new microprocessor. She has an
example workload program core with 106 instructions. Each instruction takes 100 ps to finish.

a. How long does it take to execute this program core on a nonpipelined processor?

b. The current state-of-the-art microprocessor has about 20 pipeline stages.

Assume it is perfectly pipelined. How much speedup will it achieve compared to the
nonpipelined processor?

c. Real pipelining is not perfect, since implementing pipelining introduces some overhead per
pipeline stage. Will this overhead affect instruction latency, instruction throughput, or both?

Solution:

a. It takes 100 ps * 106 instructions = 100 microseconds to execute on a nonpipelined processor

(ignoring start and end transients in the pipeline).

b. A perfect 20-stage pipeline would speed up the execution by 20 times.

c. Pipeline overhead impacts both latency and throughput.

Q3: Using a drawing like the Figure. 1 given below, show the forwarding paths needed to execute
the following four instructions:

add $3, $4, $6

sub $5, $3, $2
lw $7, 100($5)
add $8, $7, $2

Figure. 1
Solution:

Q4: Identify all the data dependencies in the following code. Which dependencies are data hazards
that will be resolved via forwarding? Which dependencies are data hazards that will cause a stall?

add $3, $4, $2

sub $5, $3, $1
lw $6, 200($3)
add $7, $3, $6
Solution:

There is a data dependency through $3 between the first instruction and each subsequent
instruction. There is a data dependency through $6 between the lw instruction and the last
instruction. For a five-stage pipeline as shown in Figure 6.7, the data dependencies between the
first instruction and each subsequent instruction can be resolved by using forwarding.

The data dependency between the load and the last add instruction cannot be resolved by using
forwarding.
Q5: Using Figure. 2 below as a guide, use coloured pens or markers to show which portions of
the datapath are active and which are inactive in each of the five stages of the SW instruction. Use
five photocopies of Figure. 2 below to answer this exercise. Be sure to include a legend to explain
your colour scheme.

Figure. 2

Solution:
Any part of the following figure not marked as active is inactive.
Stage 1:

Stage 2:
Stage 3:

Stage 4:

Since this is an sw instruction, there is no work done in the WB stage.

Q6: Consider executing the following code on the pipelined datapath of Figure. 3 below:
add $2, $3, $1
sub $4, $3, $5
add $5, $3, $7
add $7, $6, $1
add $8, $2, $6
At the end of the fifth cycle of execution, which registers are being read and which register will
be written?

Figure. 3
Solution:
At the end of the first cycle, instruction 1 is fetched.

At the end of the second cycle, instruction 1 reads registers.

At the end of the third cycle, instruction 2 reads registers.

At the end of the fourth cycle, instruction 3 reads registers.

At the end of the fifth cycle, instruction 4 reads registers, and instruction 1 writes
registers.

Therefore, at the end of the fifth cycle of execution, registers $6 and $1 are being read and
register $2 will be written.

Q7: With regard to the program in Question 6, explain what the forwarding unit is doing during
the fifth cycle of execution. If any comparisons are being made, mention them. Please note that
the forwarding unit is implementing an if which is checking the conditions all the time when the
instruction is in execution stage.

Solution:

The forwarding unit is seeing if it needs to forward. It is looking at the instructions in the fourth
and fifth stages and checking to see whether they intend to write to the register file and whether
the register written is being used as an ALU input. Thus, it is comparing 3 = 4? 3 = 2? 7 = 4? 7 =
2?

Q8: With regard to the program in Question 6, explain what the hazard detection unit is doing
during the fifth cycle of execution. If any comparisons are being made, mention them. Please note
that the hazard detection unit is implementing an if which is checking the conditions all the time
when the instruction is in decode stage.

Solution:

The hazard detection unit is checking to see whether the instruction in the ALU stage is an lw
instruction and whether the instruction in the ID stage is reading the register that the lw will be
writing. If it is, it needs to stall. If there is an lw instruction, it checks to see whether the destination
is register 6 or 1 (the registers being read).

Q9: We have a program of 103 instructions in the format of "lw, add, lw, add, . . ." The add
instruction depends (and only depends) on the lw instruction right before it. The lw instruction
also depends (and only depends) on the add instruction right before it. If the program is executed
on the pipelined datapath of Figure. 3:

a. What would be the actual CPI?

b. Without forwarding, what would be the actual CPI?

Solution:

a. There will be a bubble of 1 cycle between a lw and the dependent add since the load value is
available after the MEM stage. There is no bubble between an add and the dependent lw since the
add result is available after the EX stage and it can be forwarded to the EX stage for the dependent
lw . Therefore, CPI = cycle/instruction ≈ 1.5.

b. Without forwarding, the value being written into a register can only be read in the same cycle.
As a result, there will be a bubble of 2 cycles between an lw and the dependent add since the load
value is written to the register after the MEM stage. Similarly, there will be a bubble of 2 cycles
between an Add and the dependent lw . Therefore, CPI ≈ 3.

Q10: Consider execution of the following code on the pipelined datapath of Figure. 3:
lw $4, 100($2)
sub $6, $4, $3
add $2, $3, $5
How many cycles will it take to execute this code? Draw a diagram like that of Figure. 4 below
that illustrates the dependencies that need to be resolved and provide another diagram like that of
Figure. 5 that illustrates how the code will be executed (incorporating any stalls or forwarding) to
resolve the identified problems. (Figure 4 and 5 are examples about how you should solve this
problem in two steps).

Solution:

It will take 8 cycles to execute this code, including a bubble of 1 cycle due to the dependency
between the lw and sub instructions.