LC 3 Instruction Set

• The Instruction set architecture (ISA) of

CS 135: Computer Architecture I the LC3
¾ How is each instruction implemented by the
control and data paths in the LC3
¾ Programming in machine code
Instructor: Prof. Bhagi Narahari ¾ How are programs executed
Dept. of Computer Science ¾ Memory layout, programs in machine code
Course URL: www.seas.gwu.edu/~bhagiweb/cs135/ • Assembly programming
¾ Assembly and compiler process
¾ Assembly programming with simple
programs

CS 135

ADD+ 0001 DR SR1 0 00 SR2 LDR+ 0110 DR BaseR offset6

ADD+ 0001 DR SR1 1 imm5 LEA+ 1110 DR PCoffset9

AND+ 0101 DR SR1 0 00 SR2 NOT+ 1001 DR SR 111111

AND+ 0101 DR SR1 1 imm5 RET 1100 000 111 000000

BR 0000 n z p PCoffset9 RTI 1000 000000000000

JMP 1100 000 BaseR 000000 ST 0011 SR PCoffset9

JSR 0100 1 PCoffset11 STI 1011 SR PCoffset9

JSRR 0100 0 00 BaseR 000000 STR 0111 SR BaseR offset6

LD+ 0010 DR PCoffset9 TRAP 1111 0000 trapvect8

LDI+ 1010 DR PCoffset9 reserved 1101

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+ Indicates instructions that modify condition codes + Indicates instructions that modify condition codes

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 LC-3 Overview: Memory and Registers LC-3 Overview: Instruction Set

•Memory •Opcodes
¾ address space: 216 locations (16-bit addresses) ¾ 15 opcodes
¾ Operate instructions: ADD, AND, NOT
¾ addressability: 16 bits
¾ Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI
•Registers ¾ Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP
¾ temporary storage, accessed in a single machine ¾ some opcodes set/clear condition codes, based on result:
cycle ¾ N = negative, Z = zero, P = positive (> 0)

¾ accessing memory generally takes longer than a single cycle •Data Types
¾ eight general-purpose registers: R0 - R7 ¾ 16-bit 2’s complement integer
¾ each 16 bits wide •Addressing Modes
¾ how many bits to uniquely identify a register?
¾ How is the location of an operand specified?
¾ other registers ¾ non-memory addresses: immediate, register
¾ not directly addressable, but used by (and affected by) instructions
¾ memory addresses: PC-relative, indirect, base+offset
¾ PC (program counter), condition codes

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Operate Instructions Data Movement Instructions

•Only three operations: ADD, AND, NOT • GPR ↔ Memory

•Source and destination operands are
registers • GPR ↔ I/O Devices
¾ These instructions do not reference memory.
¾ ADD and AND can use “immediate” mode,
where one operand is hard-wired into the • GPR ← Memory ???
instruction.
•Will show dataflow diagram with each • Memory ← GPR ???
instruction.
¾ illustrates when and where data moves
to accomplish the desired operation

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 Addressing Modes Data Movement Instructions
•Load -- read data from memory to register
• Where can operands be found? ¾ LD: PC-relative mode
¾ LDR: base+offset mode
1 ¾ LDI: indirect mode

•Store -- write data from register to memory

2
¾ ST: PC-relative mode
¾ STR: base+offset mode
3
¾ STI: indirect mode

•Load effective address -- compute address,

save in register
¾ LEA: immediate mode
¾ does not access memory
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PC-Relative Addressing Mode Control Instructions

•Want to specify address directly in the instruction •Used to alter the sequence of instructions
¾ But an address is 16 bits, and so is an instruction! (by changing the Program Counter)
¾ After subtracting 4 bits for opcode •Conditional Branch
and 3 bits for register, we have 9 bits available for address. ¾ branch is taken if a specified condition is true
•Solution: ¾ signed offset is added to PC to yield new PC

¾ Use the 9 bits as a signed offset from the current PC. ¾ else, the branch is not taken
¾ PC is not changed, points to the next sequential instruction

•9 bits: − 256 ≤ offset ≤ +255 •Unconditional Branch (or Jump)

•Can form any address X, such that: PC − 256 ≤ X ≤ PC +255 ¾ always changes the PC

•TRAP
•Remember that PC is incremented as part of the FETCH phase; ¾ changes PC to the address of an OS “service routine”
•This is done before the EVALUATE ADDRESS stage. ¾ routine will return control to the next instruction (after TRAP)

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 Condition Codes Branch Instruction

•LC-3 has three condition code registers: •Branch specifies one or more condition codes.
N -- negative •If the set bit is specified, the branch is taken.
Z -- zero ¾ PC-relative addressing:
P -- positive (greater than zero) target address is made by adding signed offset (IR[8:0])
to current PC.
¾ Note: PC has already been incremented by FETCH
•Set by any instruction that writes a value stage.
to a register ¾ Note: Target must be within 256 words of BR instruction.
(ADD, AND, NOT, LD, LDR, LDI, LEA)
•If the branch is not taken,
the next sequential instruction is executed.
•Exactly one will be set at all times
¾ Based on the last instruction that altered a
register
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Operate Instructions Operate Instructions

•Only three operations: ADD, AND, NOT • NOT

•Source and destination operands are
registers
NOT+ 1001 DR SR 111111
¾ These instructions do not reference memory.
¾ ADD and AND can use “immediate” mode,
where one operand is hard-wired into the • Addressing mode?
instruction.
•Will show dataflow diagram with each
instruction.
¾ illustrates when and where data moves
to accomplish the desired operation

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 NOT (Register) Operate Instructions

• ADD, AND
Must be all 1’s in bits [0:5]

If Dst=010, Src=101 ADD+ 0001 DR SR1 0 00 SR2

R2 = NOT(R3)
ADD+ 0001 DR SR1 1 imm5

AND+ 0101 DR SR1 0 00 SR2

AND+ 0101 DR SR1 1 imm5

• Addressing Mode?
Note: Src and Dst
could be the same register.
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ADD/AND (Register) ADD/AND (Immediate)

this zero means “register mode” this one means “immediate mode”

Note: Immediate field is

If Dst=010, Src1=001, Src2=011 sign-extended.

ADD: If Dst=010, Src1=001, Imm5=00011

ADD R2,R1,#3
Dst= Src1 + Src2
R2 = R1 +3
R2= R1 + R3

AND:
Dst= Src1 AND Src2
R2 = R1 AND R3

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 Using Operate Instructions Data Movement Instructions

•With only ADD, AND, NOT… • GPR ↔ Memory

¾ How do we subtract?
• GPR ↔ I/O Devices
¾ How do we OR?

• GPR ← Memory ???

¾ How do we copy from one register to another?

¾ How do we initialize a register to zero? • Memory ← GPR ???

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Data Movement Instructions Addressing Modes

• Where can operands be found?

LD+ 0010 DR PCoffset9

1

LDI+ 1010 DR PCoffset9 2

LDR+ 0110 DR BaseR offset6
3
LEA+ 1110 DR PCoffset9

ST 0011 SR PCoffset9

STI 1011 SR PCoffset9

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 Basic Format Data Movement Instructions
•Load -- read data from memory to register
¾ LD: PC-relative mode
0010 DR or SR Address generation bits
¾ LDR: base+offset mode
¾ LDI: indirect mode

on
n s •Store -- write data from register to memory
io s
at dre
rm d ¾ ST: PC-relative mode
fo t a
in bi
d e 16 ¾ STR: base+offset mode
co a
en rm ¾ STI: indirect mode
e fo
he s to
T ow
h •Load effective address -- compute address,
save in register
¾ LEA: immediate mode
¾ does not access memory
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PC-Relative Addressing Mode LD (PC-Relative)

•Want to specify address directly in the instruction

¾ But an address is 16 bits, and so is an instruction!
¾ After subtracting 4 bits for opcode
and 3 bits for register, we have 9 bits available for address.
•Solution:
¾ Use the 9 bits as a signed offset from the current PC.

•9 bits: − 256 ≤ offset ≤ +255

•Can form any address X, such that: PC − 256 ≤ X ≤ PC +255

•Remember that PC is incremented as part of the FETCH phase;

•This is done before the EVALUATE ADDRESS stage.

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 ST (PC-Relative) Indirect Addressing Mode

•With PC-relative mode, can only address

data within 256 words of the instruction.
¾ What about the rest of memory?
•Solution #1:
¾ Read address from memory location,
then load/store to that address.
•First address is generated from PC and IR
(just like PC-relative addressing), then
content of that address is used as target for
load/store.

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LDI (Indirect) STI (Indirect)

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 Base + Offset Addressing Mode LDR (Base+Offset)

•With PC-relative mode, can only address

data
within 256 words of the instruction.
¾ What about the rest of memory?
•Solution #2:
¾ Use a register to generate a full 16-bit address.
•4 bits for opcode, 3 for src/dest register,
3 bits for base register -- remaining 6 bits
are used as a signed offset.
¾ Offset is sign-extended before adding to base
register.

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STR (Base+Offset) Load Effective Address

•Computes address like PC-relative (PC

plus signed offset) and stores the result
into a register.

•Note: The address is stored in the register,

not the contents of the memory location.

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 LEA (Immediate) Example

Address Instruction Comments

x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1 ← PC – 3 = x30F4

x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2 ← R1 + 14 = x3102

M[PC - 5] ← R2
x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[x30F4] ← x3102

x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 ← 0

x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2 ← R2 + 5 = 5

M[R1+14] ← R2
x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[x3102] ← 5
R3 ← M[M[x30F4]]
x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3 ← M[x3102]
R3 ← 5

opcode
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Control Instructions Control Instructions

•Used to alter the sequence of instructions

(by changing the Program Counter)
•Conditional Branch BR 0000 n z p PCoffset9

¾ branch is taken if a specified condition is true

JMP 1100 000 BaseR 000000
¾ signed offset is added to PC to yield new PC
¾ else, the branch is not taken 1
JSR 0100 PCoffset11
¾ PC is not changed, points to the next sequential instruction

•Unconditional Branch (or Jump) JSRR 0100 0 00 BaseR 000000

¾ always changes the PC

RET 1100 000 111 000000

•TRAP
RTI 1000 000000000000
¾ changes PC to the address of an OS “service routine”
¾ routine will return control to the next instruction (after TRAP) TRAP 1111 0000 trapvect8

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 Condition Codes Branch Instruction

•LC-3 has three condition code registers: •Branch specifies one or more condition codes.
N -- negative •If the set bit is specified, the branch is taken.
Z -- zero ¾ PC-relative addressing:
P -- positive (greater than zero) target address is made by adding signed offset (IR[8:0])
to current PC.
¾ Note: PC has already been incremented by FETCH
•Set by any instruction that writes a value stage.
to a register ¾ Note: Target must be within 256 words of BR instruction.
(ADD, AND, NOT, LD, LDR, LDI, LEA)
•If the branch is not taken,
the next sequential instruction is executed.
•Exactly one will be set at all times
¾ Based on the last instruction that altered a
register
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BR (PC-Relative) Using Branch Instructions

•Compute sum of 12 integers.

Numbers start at location x3100. Program starts at location
x3000.
¾ Add numbers from location x3100 to x311B
¾ Store first address in R2
¾ R4 has “counter” – counts down from 12 to 0
¾ R1 will store the running Sum

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What happens if bits [11:9] are all zero? All one?

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 Program
R2 <- x3100
R1 <- 0
R4 <- 12 x3000 R2 <- x3100
x3001 R4 <- 0
x3002 R1 <- 0
YES x3003 R4 <- 12
R4 ?= 0 x3004 BRz x300A
x3005 R3 <- M[R2]
NO x3006 R1 <- R1 + R3
x3007 R2 <- R2 + 1
R3 <- M[R2]
R1 <- R1 + R3 x3008 R4 <- R4 - 1
Increment R2 x3009 BRnzp x3004
Decrement R4

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Program JMP (Register)

opcode
x3000 R2 <- x3100 LEA 1110010011111111 •Jump is an unconditional branch -- always taken.
x3001 R1 <- 0 AND 0101001011100000 ¾ Target address is the contents of a register.
x3002 R4 <- 0 AND 0101100010100000
¾ Allows any target address.
x3003 R4 <- 12 ADD 0001100010101100
x3004 BRz x300A BRz 0000010000000101
x3005 R3 <- M[R2] LDR 0110011010000000
x3006 R1 <- R1 + R3 ADD 0001001001000011
x3007 R2 <- R2 + 1 ADD 0001010010100001
x3008 R4 <- R4 - 1 ADD 0001100100111111
x3009 BRnzp x3004 BRnzp 0000111111111010
dest Immediate
source

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 TRAP Instruction TRAP

• Modern computers contain hardware and

software protection schemes to prevent
user programs from accidentally (or •Calls a service routine, identified by 8-bit “trap vector.”
maliciously) interfering with proper vector routine
system function.
x23 input a character from the keyboard
x21 output a character to the monitor
• Suffice it to say, we need a way to x25 halt the program
communicate with the operating system
•When routine is done,
PC is set to the instruction following TRAP.
•(We’ll talk about how this works later.)

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The LC-3 ISA: summary ADD+ 0001 DR SR1 0 00 SR2

ADD+ 0001 DR SR1 1 imm5

• 16 bit instructions and data
• 2’s complement data type AND+ 0101 DR SR1 0 00 SR2

• Operate/ALU instructions: ADD, NOT, AND AND+ 0101 DR SR1 1 imm5

• Data movement Inst: Load and Store

BR 0000 n z p PCoffset9
¾ Addressing mode: PC-relative, Indirect,
Register/Base+Offset,Immediate
JMP 1100 000 BaseR 000000
• Transfer of control instructions
¾ Branch – using condition code registers JSR 0100 1 PCoffset11

¾ Jump – unconditional branch

JSRR 0100 0 00 BaseR 000000
¾ Traps, Subroutine calls – discuss later
• Let’s take a peek at the LC3 datapath and LD+ 0010 DR PCoffset9
controller design
LDI+ 1010 DR PCoffset9

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+ Indicates instructions that modify condition codes

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 LDR+ 0110 DR BaseR offset6 Von Neumann Model: Outline
LEA+ 1110 DR PCoffset9

NOT+ 1001 DR SR 111111

• Basic Components
¾ Memory, Processing Unit, Input & Output, Control
RET 1100 000 111 000000 Unit
RTI 1000 000000000000 • LC-3: An Example von Neumann Machine
• Instruction Processing
ST 0011 SR PCoffset9
¾ The Instruction, The Instruction Cycle
STI 1011 SR PCoffset9 ¾ Fetch, Decode, Evaluate Address, Fetch Operands, Execute, Store
Result
STR 0111 SR BaseR offset6 ¾ Changing the Sequence of Execution
¾ Branches and Jumps
TRAP 1111 0000 trapvect8
¾ Stopping the Computer
reserved 1101

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+ Indicates instructions that modify condition codes

Another device: tri-state buffer

LC-3
• inputs to the bus are Data Path
“tri-state devices,” Revisited
that only place a
signal on the bus
when they are
enabled

• Tri-state buffer Filled arrow

controls when = info to be processed.
Unfilled arrow
current passes = control signal.
through the line
¾ A true “open switch”
¾ When control signal
c=1 then x=z else
“open switch”

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 LC-3 Data Path gateMARMUX gatePC
3
16

DR REG
MARMUX
MARMUX LD.PC PC
16
PCMUX +1 FILE
16 16 2 LD.REG
PCMUX
SR2 SR1
Combinational ZEXT
16
SR2
3
OUT OUT
3
SR1
Logic +
ADDR2MUX
[7:0]
2
ADDR1MUX
ADDR2MUX ADDR1MUX 16 16
16
16 16 16 16
[10:0] 16
SEXT
0
Storage SEXT
16
[8:0] [4:0]
SEXT
FINITE SR2MUX
STATE
[5:0] SEXT
N Z P LD.CC MACHINE B A
2
R ALU
LD.IR IR LOGIC
gateALU
16 16 16
State Machine
16 GateMDR 16
16

LD.MDR LD.MAR
MDR MEMORY MAR INPUT OUTPUT
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MEM.EN, R.W

Data Path Components Data Path Components

•Global bus •ALU

¾ special set of wires that carry a 16-bit signal ¾ Accepts inputs from register file
to many components and from sign-extended bits from IR (immediate field).
¾ inputs to the bus are “tri-state devices,” ¾ Bit 5 of LC3 instruction determines this
that only place a signal on the bus when they are enabled ¾ Output goes to bus.
¾ only one (16-bit) signal should be enabled at any time ¾ used by condition code logic, register file, memory
¾ control unit decides which signal “drives” the bus ¾ Function to apply: determined by opcode – need 2 bits
¾ any number of components can read the bus ALUK
register only captures bus data if it is write-enabled by the control unit
•Register File
¾

¾ Two read addresses (SR1, SR2), one write address (DR)

•Memory ¾ Input from bus
¾ Control and data registers for memory and I/O devices ¾ result of ALU operation or memory read

¾ memory: MAR, MDR (also control signal for read/write) ¾ Two 16-bit outputs
¾ used by ALU, PC, memory address
¾ data for store instructions passes through ALU

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 Data Path Components Data Path Components

•Condition Code Logic

• PC and PCMUX
¾ Looks at value on bus and generates N, Z, P signals
¾ Three inputs to PC, controlled by PCMUX ¾ Registers set only when control unit enables them (LD.CC)
1. PC+1 – FETCH stage ¾ only certain instructions set the codes
2. Address adder – BR, JMP (ADD, AND, NOT, LD, LDI, LDR, LEA)
3. bus – TRAP (discussed later)
•Control Unit – Finite State Machine
¾ On each machine cycle, changes control signals for next phase
of instruction processing
¾ MAR and MARMUX ¾ who drives the bus? (GatePC, GateALU, …)
which registers are write enabled? (LD.IR, LD.REG, …)
Two inputs to MAR, controlled by MARMUX
¾
• ¾ which operation should ALU perform? (ALUK)
1. Address adder – LD/ST, LDR/STR ¾ …
2. Zero-extended IR[7:0] -- TRAP (discussed later) ¾ Logic includes decoder for opcode, etc.

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LC3 data path

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 Implementing the Control Logic

• Given the state diagram one can

implement the controller in many ways
¾ 52 states
¾ Each needs 39 control lines plus 10 to
determine next state = 49 control lines
• What should controller do ?
¾ Generate the 49 control signals at each cycle
• Implement this as a Microprogram
¾ Use 6 bit address to get the microinstruction
¾ Start state and progress through states
based on microinstruction

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Microprogrammed Implementation Course Summary

• Datatypes of machines: Number Representation

¾ 2’s complement integers, Floating point
¾ Arithmetic on 2’s complement
¾ Logic operations
• Digital logic: devices to build the circuits
¾ CMOS transistor is the starting point
¾ Basic logic gates: AND, OR, NOT, NAND, etc.
¾ Combinational logic ‘blocks’: MUX, Decoder, PLA
¾ Sequential Logic: storage element, finite state machines
¾ Putting it all together to build a simple processor- LC3
• Von Neumann Model of computing
• Instruction set architecture (ISA) of LC3
¾ Instructions of a processor – how program execution takes
place
¾ Addressing modes to data movement, branches, operations
¾ Programming in machine language

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