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    Homework6 Ans

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    The document discusses a sequential logic design homework assignment. It includes 5 questions: 1) Analyzing a sequential circuit with 2 D flip-flops, 2 inputs, and 1 output. 2) Determining state transitions and outputs for an input sequence. 3) Deriving the state table and diagram for a circuit with 2 SR flip-flops, 1 input, and 1 output. 4) Calculating timing parameters like path delays for a given sequential circuit. 5) Designing a circuit to produce a repeating output sequence in response to an enable signal.

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    Homework6 Ans

    Uploaded by

    nada abdelrahman
    109 views12 pages
    The document discusses a sequential logic design homework assignment. It includes 5 questions: 1) Analyzing a sequential circuit with 2 D flip-flops, 2 inputs, and 1 output. 2) Determining state transitions and outputs for an input sequence. 3) Deriving the state table and diagram for a circuit with 2 SR flip-flops, 1 input, and 1 output. 4) Calculating timing parameters like path delays for a given sequential circuit. 5) Designing a circuit to produce a repeating output sequence in response to an enable signal.

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    The document discusses a sequential logic design homework assignment. It includes 5 questions: 1) Analyzing a sequential circuit with 2 D flip-flops, 2 inputs, and 1 output. 2) Determining state transitions and outputs for an input sequence. 3) Deriving the state table and diagram for a circuit with 2 SR flip-flops, 1 input, and 1 output. 4) Calculating timing parameters like path delays for a given sequential circuit. 5) Designing a circuit to produce a repeating output sequence in response to an enable signal.

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    © All Rights Reserved
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    109 views12 pages

    Homework6 Ans

    Uploaded by

    nada abdelrahman
    The document discusses a sequential logic design homework assignment. It includes 5 questions: 1) Analyzing a sequential circuit with 2 D flip-flops, 2 inputs, and 1 output. 2) Determining state transitions and outputs for an input sequence. 3) Deriving the state table and diagram for a circuit with 2 SR flip-flops, 1 input, and 1 output. 4) Calculating timing parameters like path delays for a given sequential circuit. 5) Designing a circuit to produce a repeating output sequence in response to an enable signal.

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    of 12

    邏輯設計 Hw#6

    請於6/13(五)下課前繳交
    1. A sequential circuit with two D flip-flops A and B, two inputs X and Y, and
    one output Z is specified by the following input equations:
    DA = X’A + XY DB = X’A + XB Z = XB
    (a) Draw the logic diagram of the circuit.
    (b) Derive the state table. Present Next
    (c) Derive the state diagram. (b) state Inputs state Output
    A B X Y A+ B+ Z
    <Ans.> 0 0 0 0 0 0 0
    0 0 0 1 0 0 0
    (a) 0 0 1 0 0 0 0
    0 0 1 1 1 0 0
    0 1 0 0 0 0 0
    0 1 0 1 0 0 0
    0 1 1 0 0 1 1
    0 1 1 1 1 1 1
    1 0 0 0 1 1 0
    1 0 0 1 1 1 0
    1 0 1 0 0 0 0
    1 0 1 1 1 0 0
    1 1 0 0 1 1 0
    1 1 0 1 1 1 0
    1 1 1 0 0 1 1
    1 1 1 1 1 1 1
    <Ans.> Format: XY/Z
    (c) (x = don’t care)

    0x/0, x0/0 10/1

    0x/0
    00 01

    11/0 10/0 10/1 11/1

    10 11
    0x/0

    11/0 0x/0, 11/1


    2. Starting from state 00 in the diagram of figure, determine the state
    transitions and output sequence that will be generated when an input sequence
    of 10011011110 is applied.

    <Ans.>

    State
    變化 Input Output
    00 1 0
    01 0 1
    00 0 0
    00 1 0
    01 1 0
    11 0 1
    00 1 0
    01 1 0
    11 1 0
    10 1 0
    10 0 1
    00
    3. A sequential circuit has two SR flip-flops, one input X, and one output Y.
    The logic diagram of the circuit is shown in figure. Derive the state table and
    state diagram of the circuit.

    <Ans.>
    SA = B RA = B’
    SB = (X + A)’ RB = X + A
    Y=A+B+X

    A+ = SA + RA’ A = B + (B’)’A = B
    B+ = SB + RB’ B = (X + A)’ + ((X + A)’)’ B = (X + A)’ Format: X/Y
    (x = don’t care)
    Present Next 0/0
    1/1
    state Input state Output
    A B X A+ B+ Y 00 01
    0 0 0 0 1 0
    0 0 1 0 0 1
    0 1 0 1 1 1 x/1 0/1
    0 1 1 1 0 1 1/1
    1 0 0 0 0 1
    1 0 1 0 0 1
    1 1 0 1 0 1 10 11
    x/1
    1 1 1 1 0 1
    4. A sequential circuit is given in figure. The timing parameters for the gates
    and flip-flops are as follows:
    Inverter: tpd = 0.5 ns XOR Gate: tpd = 2.0 ns
    Flip-flop: tpd = 2.0 ns, ts = 1.0 ns and th = 0.25 ns
    (a) Find the longest path delay from an external circuit input passing through
    gates only to an external circuit output.
    (b) Find the longest path delay in the circuit from an external input to positive
    clock edge.
    (c) Find the longest path delay from positive clock edge to output.
    (d) Find the longest path delay from positive clock edge to positive clock edge.
    (e) Determine the maximum frequency of operation of the circuit in megahertz
    (MHz).
    <Ans.>
    (a) tdelay = tpdXOR × 2
    = 4.0 ns

    (b) tdelay = tpdXOR + tpbINV + tsFF


    = 3.5 ns
    4.
    (c) Find the longest path delay from positive clock edge to output.
    (d) Find the longest path delay from positive clock edge to positive clock edge.
    (e) Determine the maximum frequency of operation of the circuit in megahertz
    (MHz).
    <Ans.>

    (c) tdelay = tpdFF + tpdXOR + tpdXOR


    = 6.0 ns

    (d) tdelay = tpdFF + tpdXOR + tpdINV + tsFF


    = 2.0 ns + 2.0 ns + 0.5 ns + 1.0 ns
    = 5.5 ns

    (e) Maximum frequency = 1 / tdelay_max = 1 / 6.0 ns = 166.67 MHz


    5. A Universal Serial Bus (USB) communication link requires a circuit that
    produces the sequence 00000001. You are to design a synchronous sequential
    circuit that starts producing this sequence for input E = 1. Once the sequence
    starts, it completes. If E = 1, during the last output in the sequence, the
    sequence repeats. Otherwise, if E = 0, the output remains constant at 1.
    (a) Draw the Moore state diagram for the circuit.
    (b) Find the state table and make a state assignment.
    (c) Design the circuit using D flip-flops and logic gates. A reset should be
    include to place the circuit in the appropriate initial state at which E is
    examined to determine if the sequence or constant 1’s is to be produced.
    <Ans.> (b)因為有0~7共8個states，所以用D2D1D0 3 bits 表示。
    (a) Present Next state
    S0/ S1/ S2/ S3/ state For input Output
    0 0 0 0 D2D1D0 E = 0 E = 1 Z
    0 0 0 0 0 1 0
    E=1 0 0 1 0 1 0 0
    0 1 0 0 1 1 0
    S7/ S6/ S5/ S4/ 0 1 1 1 0 0 0
    1 0 0 0 1 0 0 1 0 1 0
    1 0 1 1 1 0 0
    Format: state/output 1 1 0 1 1 1 0
    E=0
    1 1 1 111 000 1
    5.
    (c) Design the circuit using D flip-flops and logic gates. A
    reset should be include to place the circuit in the appropriate
    initial state at which E is examined to determine if the
    sequence or constant 1’s is to be produced.

    <Ans.>

    (c) 根據 (b)
    Z = D2D1D0
    D2+ = D2D1’ + D2D0’ + D2’D1D0 + D2D1D0E
    D1+ = D1♁D0 + D2D1D0E
    D0+ = D0’ + D2D1D0E

    題目要求reset的作用是讓state初始化成，
    看E等於多少決定要產生00000001還是一
    直是1，這跟state 7的行為完全相同，所
    以將reset接到每個D flip-flop的set。
    6. Find the logic diagram for the circuit having the state table given in table.
    Use J-K flip-flops. Present Next Flip-Flop
    <Ans.> state Input state Output Inputs
    A B X A+ B+ Z JA KA JB KB
    先寫出右圖的 flip-flop inputs 0 0 0 0 0 0 0 X 0 X
    再寫出 input output equations 0 0 1 0 1 0 0 X 1 X
    JA = BX 0 1 0 0 0 0 0 X X 1
    KA = B’ 0 1 1 1 1 0 1 X X 0
    JB = X 1 1 0 1 0 0 X 0 X 1
    KB = X’ 1 1 1 1 1 0 X 0 X 0
    Z = AB’X 1 0 0 0 0 0 X 1 0 X
    1 0 1 0 1 1 X 1 1 X
    補充題 1：State Reduction
    化簡下列state diagram，求出化簡後的state table
    <Ans.>
    Step 0. 根據右圖列出 state table
    Step 1. I/O behavior 不同者打X
    Step 2. 列出 next state 關係
    Step 3. 持續檢查因既有的 X 而不可能相同者打 X
    round 1. 綠色 X Present Next state Output
    round 2. 發現沒有再打 X => A = C = F, D = E state I=0 I=1 I=0 I=1
    A C D 1 0
    Present Next state Output B F B 1 0
    state I=0 I=1 I=0 I=1 C A E 1 0
    C=F
    B B=D A A D 1 0 D B C 0 0
    A=C A=F
    B A B 1 0 E B F 0 0
    C D=E B=E D B A 0 0 F A E 1 0
    D
    B=B
    E C=F

    A=C A=F A=A


    F D=E B=E E=E

    A B C D E
    補充題 2：State Assignment
    Given the following state diagram, select a good state assignment. Show your
    assignment in a state map and justify your answer in terms of the state
    assignment guidelines.
    Present Next state Output
    state I=0 I=1 I=0 I=1
    a a b 0 0
    b c d 0 0
    c a d 0 0
    d e d 0 1
    e a d 0 1
    Highest: states that share a common next state
    (b, c, d, e) (a, c, e)
    Medium: states that share a common ancestor state
    (a, b) (c, d) (a, d) (d, e) (a, d) => (a, b) (a, d) × 2 (c, d) (d, e)
    Lowest: states that have common output behavior
    (a, b, c, d, e) (a, b, c) (d, e) Q1Q0
    Q2 00 01 11 10
    * 紅色底線表可符合之條件 a d
    0
    * 答案非唯一
    1 c e b

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