F

Faculty: Engineering & Technology

Process Control &

Department: Computer Systems

Course: National Diploma

Engineering: Computer Systems

Title: Digital Systems 1 (ERDIS1C)

Compiled By: AC Smit

Year: Semester 2 – 2018

 PART 1
MODULE INFORMATION

RULES AND REGULATIONS ……………………………………………………………………………………………….Page 2

INFORMATION ………………………………………………………………………………………………… …. Page 2

ATTENDANCE OF LECTURES…………………………………………………………………………………. Page 2

TESTS………………………………………………………..……………………………………………………….. Page 2

PRACTICAL MARK ……………………………………………………………………………………………..……………. Page 2

SEMESTER/YEAR MARK………………………………………………………………………………………………. Page 3

EXAMINATION ………………………………………………………………………………….…………………….. Page 3

PRESCRIBED LEARNING MATERIAL ……………………………………………………………….…….. Page 3

MODULE CONTENT ……………………………………………………………………………………………….. Page 4

APPENDIX A: SUMMARY OF FORMULAS …………………………………………………………………… Page 40

1
RULES AND REGULATIONS
The Vaal University of Technology’s rules and regulations regarding student and learner behavior are
applicable. The following rules are of specific importance to note by students using the facilities offered by
the Process Control and Computer Systems Department:
• Do not litter in passages, enclosed areas, and classrooms.
• Classrooms must be kept as tidy as possible.
• Students are not allowed to eat and/or drink in the classrooms and laboratories.
• Do not disturb learners attending lectures by disrupting a lecture in progress or unnecessary
loudness in passages and enclosed areas.

INFORMATION
The Notice Boards are situated on the ground floor between auditoriums T002 and T003, on the top floor
between T205 and T206 and opposite T206. The semester marks and preliminary exam time table, as well as
other computer systems related items such as bursaries, work opportunities, competitions, and new
developments will be displayed on these boards. Visit these boards regularly.
• Secretary to the HOD: room R003.
• Examination rules and regulations: obtainable from the examination offices.
• Library – Goldfields Library Building.

ATTENDANCE OF LECTURERS
Students guilty of bad behavior or disturbing other learners in classes or laboratories, can be requested by
the lecturer to leave the room. Absence from lectures must be kept to a minimum. If absent from lectures,
learners must catch-up work done on their own.

TESTS
Theoretical knowledge should be assessed by at least three compulsory tests of more or less equal
importance. Notification of a test must be given at least 1 week in advance. Absence from tests will only be
granted for medical and legal reasons. Learners must notify the lecturer and hand in the original or certified
copy of the doctor’s certificate or proof of court appearance within 3 days after the expiring date thereof , to
the lecturer or secretary of the HOD (at room R003). No personal reasons (i.e. appointments for bursary
applications, driver’s license, dental appointments, application for work, etc.) will be accepted. Absence
from tests, without an acceptable reason, will result in a mark of 0% for that test. Absentees, with an
acceptable reason, can be asked to write a ‘substitute test’ immediately at the lecturer’s discretion.

It is advised that no rewrites should be allowed, and that each test should carry an equal weight to establish
the mark for theory. Due to circumstances it might be necessary to deviate from these rules and allow a
rewrite or alter the relative weight of each test. Any change, if necessary, must be communicated to learners
in good time (± 1 week).

PRACTICAL MARK
The practical mark is established by the Senior Laboratory Assistant. Full information in this regard can be
obtained from him. Students must achieve a pass-mark (50%) for practical in order to be admitted to the
examination,

2
SEMESTER/YEAR MARK
The semester marks are published on the notice boards during the week following on the last test. The
semester mark is the weighted average of the mark for theory at 75% and the mark for practical at 25%.

When calculating the final semester mark, percentage class attendance could be taken into consideration in
borderline cases.

Once the semester mark is released, it is the learner’s responsibility to check the semester mark and to
report a possible error immediately to the relevant lecturer.

EXAMINATION

A 3-hour examination paper is written in June and November respectively.

Normal examination rules and regulations are applicable to this subject.

Admission to the examination is granted to learners obtaining a semester mark and practical mark of 50% or
more, respectively.

To pass this subject a final mark of at least 50% must be obtained, with a sub-minimum of 40% achieved in
the examination. The final mark is calculated as: (Semester mark + Examination mark) ÷ 2. Both marks
therefore carry a weight of 50%.

PRESCRIBED LEARNING MATERIAL

Title: Digital Fundamentals

Author: Thomas L Floyd
Publisher: Prentice-Hall International
ISBN-13: 978-1-292-07598-3

3
 Module Content
LEARNING UNIT 1 [ FORMATIVEASSESSMENT 1]

Chapter 1: Introductory Concepts

Section 1-1: Digital and Analog Quantities

Section 1-2: Binary Digits, Logic Levels and Digital Waveforms
Section 1-3: Basic Logic Functions

Practical Assessment 1: Multisim 10.1

LEARNING UNIT 2 [ FORMATIVE ASSESSMENT 2]

Chapter 2: Number Systems, Operations and Codes

Section 2-1: Decimal Numbers

Section 2-2: Binary Numbers
Section 2-3: Decimal-to-Binary Conversion
Section 2-4: Binary Arithmetic
Section 2-5: Compliments of Binary Numbers
Section 2-6: Signed Numbers
Section 2-7: Arithmetic Operations with Signed Numbers
Section 2-8: Hexadecimal Numbers
Section 2-9: Octal Numbers
Section 2-10: Binary Coded Decimal (BCD)
Section 2-11: Digital Codes
Section 2-12: Error Codes

Practical Assessment 2: Multisim 10.1

LEARNINGUNIT 3 [FORMATIVE ASSESSMENT 3]

Chapter 3: Logic Gates

Section 3-1: The Inverter

Section 3-2: The AND gate
Section 3-3: The OR gate
Section 3-4: The NAND Gate
Section 3-5: The NOR Gate
Section 3-6: The Exclusive-OR and Exclusive-NOR Gates
Section 3-8: Fixed-Function Logic Gates

Practical Assessment 3: Multisim 10.1

4
 LEARNINGUNIT 4[FORMATIVE ASSESSMENT 4]

Chapter4Boolean Algebra and Logic Simplifications

Section 4-1: Boolean Operations and Expressions

Section 4-2: Laws and Ru le s o f Bo o le an Alge b ra
Section 4-3: DeMorgan’s Theorems
Section 4-4: Boolean Analysis of Logic Circuits
Section 4-5: Logic Simplifications using Boolean Algebra
Section 4-6: Standard Forms of Boolean Expressions
Section 4-7: Boolean Expressions and Truth Tables
Section 4-8: The Karnaugh Map
Section 4-9: Karnaugh Map SOP Minimization
Section 4-10: Karnaugh Map POS Minimization

Practical Assessment 4: Multisim 10.1

LEARNING UNIT 5 [FORMATIVE ASSESSMENT 5]

Chapter 5 Combinational Logic Analysis

Section 5-1: Basic Combinational Logic Circuits

Section 5-2: Imp lemen t in g Combinational Logic
Section 5-3: Th e Un ive rsal P ro p e rt y of N AN D an d N OR gat e s
Section 5-4: Combinational Logic using N A N D an d N OR gat e s
Section 5-5: Pulse Waveform Operation

Practical Assessment 5: Multisim 10.1

LEARNING UNIT 6 [FORMATIVE ASSESSMENT 5]

Chapter 6 Fu n c t i o n s o f Combinational Logic

Section 6-1: Half and Full Adders

Section 6-2: P aralle l Bin ary Add e rs
Section 6-3: Rip ple Carry an d Lo o k - Ah e ad Carry Ad d ers
Section 6-4: Comparators
Section 6-5: Decoders
Section 6-6: Encoders
Section 6-7: Code Converters
Section 6-8: Multiplexers (Data Selectors)
Section 6-9: Demultiplexers
Section 6-10: Parity Generators/Checkers

Practical Assessment 5: Multisim 10.1

5
 Part 2
LEARNING UNITS INFORMATION
LECTURER/LEARNER WORK SCHEDULE
LEARNING UNIT 1
CHAPTER 1
Introductory Concepts
Section 1-1: Digital and Analog Quantities
OUTCOMES
• Define analog
• Define digital
• Explain the difference between digital and analog quantities
• State the advantages of digital over analog

Section 1-1: LECTURER WORK SCHEDULE

Section 1-1: Content Detail

LESSON 1
Digital and Analog Quantities.......................................................................16
An Analog System............................................................................................17
A System Using Digital and Analog Methods...............................................18

Section 1-1: LEARNER WORK SCHEDULE

Section 1-1: Checkup

No: 1, 2, 3, 4………………………………………………………………………………………………………...19

Section 1-1: Self-Test

No: 1……………………………………………………………………………………………………………………58

Section 1-1: Problems

No: 1, 2, 3………………………………………………………………………………………………………….59

Section 7-1: Practical

No: – MultiSim
6
 Section 1-2: Binary Digits, Logic Levels and Digital
Waveforms
OUTCOMES
• Define binary
• Define bit
• Explain how voltage levels are used to represent bits
• Describe the general characteristics of a pulse
• Determine the amplitude, rise time, fall time and pulse width of a pulse
• Determine the amplitude, period, frequency and duty cycle of a digital waveform

Section 1-2: LECTURER WORK SCHEDULE

Section 1-2: Content Detail
LESSON 2

Binary Digits.....................................................................................................19
Logic Levels...................................................................................................20
Digital Waveforms.........................................................................................20
A Digital Waveform Carries Binary Information ..........................................22
Data Tranfer………………………………………………………..........................................23

Section 1-2: LEARNER WORK SCHEDULE

Section 1-2: Checkup

No: 1, 2, 3, 4, 5, 6, 7, 8…………………………….…………………………………….........................25

Section 1-2: Self Test

No: 2, 3, 4, 5………………………………………………………………………………….……………………..59

Section 1-2: Problems

No: 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14……….……………………………………………………..….…59

Section 1-2: Practical

No: – MultiSim

7
 Section 1-3: Basic Logic Functions
OUTCOMES
• List three basic logic functions
• Define the NOT function
• Define the AND function
• Define the OR function

Section 1-3: LECTURER WORK SCHEDULE

Section 1-3: Content Detail

LESSON 3

Basic Logic Functions.........................................................................................25

Section 1-3: LEARNER WORK SCHEDULE

Section 1-3: Checkup

No: 1, 2, 3, 4, 5………….…………………………….…………………………………….........................27

Section 1-3: Self Test

No: 6, 7, 8…..………………………………………………………………………………….……………………..59

Section 1-3: Problems

No: 15, 16, 17, 18…………………………………….……………………………………………………..….…59

8
 LEARNING UNIT 2
CHAPTER 2
Number Systems, Operations and Codes

Section 2-1: Decimal Numbers

OUTCOMES
• Explain why the decimal number system is a weighted system
• Explain how powers of ten are used in the decimal system
• Determine the weight of each digit in a decimal number

Section 2-1: LECTURER WORK SCHEDULE

Section 2-1: Content Detail

LESSON 4
Decimal Numbers...........................................................................................66
Example 2-1…...................................................................................................67
Example 2-2……................................................................................................67

Section 2-1: LEARNER WORK SCHEDULE

Section 2-1: Checkup

No: 1, 2….…………………………………………………………………………………………………………..67

Section 2-1: Self-Test

No: 1, 2.…………………………………………………………………………………….……….................117

Section 2-1: Problems

No: 1, 2, 3, 4……………………………………………………..….…………………………………………..117

9
 Section 2-2: Binary Numbers
OUTCOMES
• Count in binary
• Determine the largest decimal number that can be represented by a given number of
bits
• Convert a binary number to a decimal number

Section 2-2: LECTURER WORK SCHEDULE

Section 2-2: Content Detail

LESSON 5
Counting in Binary.........................................................................................68
The Weighting Structure of Binary Numbers….............................................69
Example 2-3…..................................................................................................70
Example 2-4…..................................................................................................70

Section 2-2: LEARNER WORK SCHEDULE

Section 2-2: Checkup

No: 1, 2, 3……….…..………………………………………………….…………………………………………...70

Section 2-2: Self-Test

No: 3,…….….…….……………………………………………………………………………………..............116

Section 2-2: Problems

No: 5, 6, 7, 8, 9, 10,………………………………………..….……………………………………………....117

10
 Section 2-3: Decimal-to-Binary Conversion
OUTCOMES
• Convert a decimal number to binary using the sum-to-weight method
• Convert a decimal whole number to binary using the repeated division-by-2 method
• Convert a decimal fraction to binary using the repeated multiplication-by-2 method

Section 2-3: LECTURER WORK SCHEDULE

Section 2-3: Content Detail

LESSON 6
Sum-of-Weight Method...............................................................................71
Example 2-5..................................................................................................71
Repeated Division-by-2 Method.................................................................71
Example 2-6..................................................................................................72
Converting Decimal Fractions to Binary......................................................73

Section 2-3: LEARNER WORK SCHEDULE

Section 2-3: Checkup

No: 1, 2………….…..………………………………………………….…………………………………………...70

Section 2-3: Self-Test

No: 4, 5….…….………………………………………………………………..……………………..............116

Section 2-3: Problems

No: 11, 12, 13, 14………………………………………..….……………………………………………....118

11
 Section 2-4: Binary Arithmetic
OUTCOMES
• Add binary numbers
• Subtract binary numbers
• Multiply binary numbers
• Divide binary numbers

Section 2-4: LECTURER WORK SCHEDULE

Section 2-4: Content Detail

LESSON 7
Binary Addition..............................................................................................74
Example 2-7....................................................................................................74
Binary Subtraction............................................................................................75
Example 2-8....................................................................................................75
Example 2-9....................................................................................................75
Binary Multiplication………………………………………………………………………… .…….76
Example 2-10..................................................................................................76
Binary Division..................................................................................................76
Example 2-11..................................................................................................76

Section 2-4: LEARNER WORK SCHEDULE

Section 2-4: Checkup

No: 1, 2, 3………………………..…………………………………………………………………………………...77

Section 2-4: Self-Test

No: 6…..……………….……………………………………………………………………………………..........116

Section 2-4: Problems

No: 15, 16, 17, 18…….………………………………………..….…………………………………………..118

12
 Section 2-5: Complements of Binary Numbers
OUTCOMES
• Convert a binary number to its 1’s complement
• Convert a binary number to its 2’s complement

Section 2-5: LECTURER WORK SCHEDULE

Section 2-5: Content Detail

LESSON 8
Finding the 1’s Complement........................................................................77
Finding the 2’s Complement........................................................................78
Example 2-12 ................................................................................................78
Example 2-13.................................................................................................78

Section 2-5: LEARNER WORK SCHEDULE

Section 2-5: Checkup
No: 1, 2…..…………………..………………………………………………………………………….………....79

Section 2-5: Self Test

No: 8, 9…………….……………………………………………………………………………………...........117

Section 2-5: Problems

No: 19, 20, 21, 22…….………………………………………..….…………………………………………118

13
 Section 2-6: Signed Numbers
OUTCOMES
• Express positive and negative numbers in sign-magnitude
• Express positive and negative numbers in 1’s complement
• Express positive and negative numbers in 2’s complement
• Determine the decimal value of signed binary numbers
• Express a binary number in floating-point format

Section 2-6: LECTURER WORK SCHEDULE

Section 2-6: Content Detail

LESSON 9
The Sign Bit ……………………….........................................................................79
Sign-Magnitude Form………..........................................................................79
1’s Complement Form .................................................................................80
2’s Complement Form .................................................................................80
Example 2-14 ................................................................................................80
The Decimal Value of Signed Numbers .......................................................80
Example 2-15 ................................................................................................81
Example 2-16 ................................................................................................81
Example 2-17 ................................................................................................82
Range of Signed Integer Numbers ..............................................................82
Example 2-18 ................................................................................................84

Section 2-6: LEARNER WORK SCHEDULE

Section 2-6: Checkup
No: 1, 2, 3, 4 ……………..………………………………………………………………………….………....84

Section 2-6: Self Test

No: 10, 11, 12, 13 ..………………………………………………………………………………...........117

Section 2-6: Problems

No: 23, 24, 25, 26, 27, 28, 29, 30 ..…………………..….…………………………………………118

14
Section 2-7: Arithmetic Operations with Signed Numbers
OUTCOMES
• Add signed binary numbers
• Define overflow
• Explain how computers add strings of numbers
• Subtract signed binary numbers
• Multiply signed binary numbers using the direct addition method
• Multiply signed binary numbers using the partial products method
• Divide signed binary numbers

Section 2-7: LECTURER WORK SCHEDULE

Section 2-7: Content Detail

LESSON 10
Addition ………………………..............................................................................85
Example 2-19 ................................................................................................86
Subtraction………..........................................................................................86
Example 2-20 ................................................................................................87
Multiplication …………...................................................................................88
Example 2-21 ................................................................................................88
Example 2-22 ................................................................................................89
Division……………………...................................................................................90
Example 2-23 ................................................................................................91

Section 2-7: LEARNER WORK SCHEDULE

Section 2-7: Checkup
No: 1, 2, 3, 4, 5, 6, 7 …..………………………………………………………………………….………....84

Section 2-7: Problems

No: 31, 32, 33, 34, 35, 36 ……………..…………………..….…………………………………………119

15
 Section 2-8: Hexadecimal Numbers
OUTCOMES
• Count in hexadecimal
• Convert from binary to hexadecimal
• Convert from hexadecimal to binary
• Convert from hexadecimal to decimal
• Convert from decimal to hexadecimal
• Add hexadecimal numbers
• Determine the 2’s complement of a hexadecimal number
• Subtract hexadecimal numbers

Section 2-8: LECTURER WORK SCHEDULE

Section 2-8: Content Detail

LESSON 11
Hexadecimal Numbers ….….........................................................................92
Counting in Hexadecimal………....................................................................93
Binary-to-Hexadecimal Conversion …………………………………………….…………93
Example 2-24 ................................................................................................93
Hexadecimal-to-Binary Conversion ............................................................93
Example 2-25 ................................................................................................93
Hexadecimal-to-Decimal Conversion .........................................................94
Example 2-26 and 2-27 ..................................................................................94
Decimal-to-Hexadecimal Conversion..........................................................95
Example 2-28 ................................................................................................95
Hexadecimal Addition .................................................................................95
Example 2-29 ................................................................................................95
Hexadecimal Subtraction ...........................................................................96
Example 2-30 ................................................................................................97

Section 2-8: LEARNER WORK SCHEDULE

Section 2-8: Checkup
No: 1, 2, 3, 4 ……………..………………………………………………………………………….………....97

Section 2-8: Self Test

No: `15, 16 ..…………………………………………………………………………………………...........117

Section 2-8: Problems

No: 37, 38, 39, 40, 41, 42 ..…………………..….…………………………………………119
16
 Section 2-9: Octal Numbers
OUTCOMES
• Write the digits of the octal number system
• Convert from octal to decimal
• Convert from decimal to octal
• Convert from octal to binary
• Convert from binary to octal

Section 2-9: LECTURER WORK SCHEDULE

Section 2-9: Content Detail

LESSON 12
Octal-to-Decimal Conversion .....................................................................98
Decimal-to-Octal Conversion………..............................................................98
Octal-to-Binary Conversion ........................................................................99
Example 2-31 ................................................................................................99
Binary-to-Octal Conversion .........................................................................99
Example 2-32 ...............................................................................................100

Section 2-9: LEARNER WORK SCHEDULE

Section 2-9: Checkup
No: 1, 2, 3, 4 ……………..…………………………………………………….…………………….………..100

Section 2-9: Self Test

No: 14 ..………………………………………………….………….……………….…………………...........117

Section 2-9: Problems

No: 43, 44, 45, 46 ………………………..…………………..….………….………………………………118

17
 Section 2-10: Binary Coded Decimal (BCD)
OUTCOMES
• Convert each decimal digit to BCD
• Express decimal numbers in BCD
• Convert from BCD to decimal
• Add BCD numbers

Section 2-10: LECTURER WORK SCHEDULE

Section 2-10: Content Detail

LESSON 13
The 8421 BCD Code ...................................................................................100
Example 2-33 ...............................................................................................101
Example 2-34 ...............................................................................................101
BCD Addition ................................................................................................102
Example 2-35 ...............................................................................................102
Example 2-36 ...............................................................................................102

Section 2-10: LEARNER WORK SCHEDULE

Section 2-10: Checkup
No: 1, 2, 3, 4 ……………..…………………………………………………….…………………….………..103

Section 2-10: Self Test

No: 17 ..…………………………………………………………….……………….…………………...........117

Section 2-10: Problems

No: 47, 48 , 49, 50, 51, 52, 53, 54 ………………………..…………….……………………………120

18
 Section 2-11: Digital Codes
OUTCOMES
• Explain the advantage of the Gray code
• Convert between Gray code and binary
• Use the ASCII code
• Discuss the Unicode

Section 2-11: LECTURER WORK SCHEDULE

Section 2-11: Content Detail

LESSON 14

The Gray Code ............................................................................................104

Example 2-37 ...............................................................................................105
Alphanumeric Codes ..................................................................................107
Example 2-38 ...............................................................................................107
Extended ASCII Characters ........................................................................109
Unicode……..................................................................................................109

Section 2-11: LEARNER WORK SCHEDULE

Section 2-11: Checkup
No: 1, 2, 3 ……………..……………………………………………………….…………………….………..103

Section 2-11: Self Test

No: 18 ..…………………………………………………………….……………….…………………...........117

Section 2-11: Problems

No: 55, 56, 57, 58, 59, 60, 61, 62 ………………………...…………….……………………………120

19
 Section 2-12: Error Codes
OUTCOMES
• Determine if there is an error in a code based on the parity bit
• Assign the proper parity bit to a code
• Explain the cyclic redundancy (CRC) check
• Describe the Hamming code

Section 2-12: LECTURER WORK SCHEDULE

Section 2-12: Content Detail

LESSON 15

Parity Method for Error Detection ............................................................110

Example 2-39 ...............................................................................................111
Example 2-40 ...............................................................................................111
Cyclic Redundancy Check ...........................................................................111
Example 2-41 ...............................................................................................113
Example 2-42 ...............................................................................................114
Hamming Code ...........................................................................................114

Section 2-12: LEARNER WORK SCHEDULE

Section 2-12: Checkup
No: 1, 2, 3, 4, 5 ……………..……………….……………………………….…………………….………..103

Section 2-12: Self Test

No: 19, 20 ..……………………………………………………….……………….…………………...........117

Section 2-12: Problems

No: 63, 64, 65, 66, 67, 68, 69 ……………………………...…………….……………………………121

20
 LEARNING UNIT 3
CHAPTER 3
Logic Gates

Section 3-1: The Inverter

OUTCOMES
• Identify negation and polarity indicators
• Produce the truth table for an inverter
• Describe the logical operation of an inverter

Section 3-1: LECTURER WORK SCHEDULE

Section 3-1: Content Detail

LESSON 16

The Negation and Polarity Indicators.........................................................126

Inverter Truth Table…………..……………………………………………………………………127
Inverter Operation………………………………………………………………………………..…127
Timing Diagrams………………………………………………………………………………………127
Example 3-1 ..................................................................................................127
Logic Expression for an Inverter .................................................................128
An Application .............................................................................................128

Section 3-1: LEARNER WORK SCHEDULE

Section 3-1: Checkup

No: 1, 2…....…………………..…………………………………………………………………………………...129

Section 3-1: Self Test

No: 1, 2……………….……………………………………………………………………………………..........178

Section 3-1: Problems

No: 1, 2, 3 ………..…….………………………………………..….…………………………………………..179

Section 3-1: Practical

No: – MultiSim

21
 Section 3-2: The AND Gate
OUTCOMES
• Identify an AND gate by its symbol
• Describe the operation of an AND gate
• Generate the truth table for an AND gate with any number of inputs
• Produce a timing diagram for an AND gate with any specified input waveforms
• Write the logic expression for an AND gate with any number of inputs
• Discuss examples of AND gate applications

Section 3-2: LECTURER WORK SCHEDULE

Section 3-2: Content Detail

LESSON 17
The Operation of an AND Gate ........................................................................129
AND Gate Truth Table .....................................................................................130
Example 3-2 ..................................................................................................130
AND Gate Operation with Waveform Inputs ..............................................131
Example 3-3 ..................................................................................................131
Example 3-4 ..................................................................................................132
Example 3-5 ..................................................................................................132
Logic Expressions for an AND Gate ............................................................133
Applications.................................................................................................134

Section 3-2: LEARNER WORK SCHEDULE

Section 3-2: Checkup

No: 1, 2, 3 ………………………..…………………….………………………………………………………...133

Section 3-2: Self Test

No: 3 ………………………………………………………………………………………………………...........178

Section 3-2: Problems

No: 4, 5, 6, 7, 8 ………….………………………………………..….………………………………………..180

Section 3-2: Practical

No: – MultiSim

22
 Section 3-3: The OR Gate
OUTCOMES
• Identify an OR gate by its symbol
• Describe the operation of an OR gate
• Generate the truth table for an OR gate with any number of inputs
• Produce a timing diagram for an OR gate with any specified input waveforms
• Write the logic expression for an OR gate with any number of inputs
• Discuss examples of OR gate applications

Section 3-3: LECTURER WORK SCHEDULE

Section 3-3: Content Detail

LESSON 18
The Operation of an OR Gate .........................................................................136
OR Gate Truth Table ......................................................................................137
OR Gate Operation with Waveform Inputs ................................................137
Example 3-7 ..................................................................................................137
Example 3-8 ..................................................................................................138
Example 3-9 ..................................................................................................138
Logic Expressions for an OR Gate ...............................................................139
Applications..................................................................................................139

Section 3-3: LEARNER WORK SCHEDULE

Section 3-3: Checkup

No: 1, 2, 3 ………………………..…………………….………………………………………………………...140

Section 3-3: Self Test

No: 4 ………………………………………………………………………………………………………...........178

Section 3-3: Problems

No: 9, 10, 11, 12, 13, 14, 15, 16 ..………………………..….…………………………….…………..181

Section 3-3: Practical

No: – MultiSim

23
 Section 3-4: The NAND Gate
OUTCOMES
• Identify a NAND gate by its symbol
• Describe the operation of a NAND gate
• Generate the truth table for a NAND gate with any number of inputs
• Produce a timing diagram for a NAND gate with any specified input waveforms
• Write the logic expression for a NAND gate with any number of inputs
• Describe NAND gate operation in terms of its negative-OR equivalent

Section 3-4: LECTURER WORK SCHEDULE

Section 3-4: Content Detail

LESSON 19
The Operation of a NAND Gate .......................................................................141
NAND Gate Operation with Waveform Inputs ...........................................141
Example 3-10 ................................................................................................141
Example 3-11 ................................................................................................142
Example 3-12 ................................................................................................142
Example 3-13 ................................................................................................143
Example 3-14 ................................................................................................144
Logic Expressions for a NAND Gate ............................................................144

Section 3-4: LEARNER WORK SCHEDULE

Section 3-4: Checkup

No: 1, 2, 3, 4 ………………………..…………………….………………..…………………………………...145

Section 3-4: Self Test

No: 5 ………………………………………………………………………………………………………...........178

Section 3-4: Problems

No: 17, 18, 19, 20 ..………………………..……………………...…………………………….…………..181

Section 3-4: Practical

No: – MultiSim

24
 Section 3-5: The NOR Gate
OUTCOMES
• Identify a NOR gate by its symbol
• Describe the operation of a NOR gate
• Generate the truth table for a NOR gate with any number of inputs
• Produce a timing diagram for a NOR gate with any specified input waveforms
• Write the logic expression for a NOR gate with any number of inputs
• Describe NOR gate operation in terms of its negative-AND equivalent
• Discuss examples of NOR gate applications

Section 3-5: LECTURER WORK SCHEDULE

Section 3-5: Content Detail

LESSON 20
The Operation of a NOR Gate .........................................................................145
NOR Gate Operation with Waveform Inputs ..............................................146
Example 3-15 ................................................................................................146
Example 3-16 ................................................................................................146
Example 3-17 ................................................................................................147
Example 3-18 ................................................................................................147
Example 3-19 ................................................................................................148
Logic Expressions for a NOR Gate ...............................................................149

Section 3-6: LEARNER WORK SCHEDULE

Section 3-6: Checkup

No: 1, 2, 3, 4 ………………………..…………………….………………..…………………………………...149

Section 3-6: Self Test

No: 6 ………………………………………………………………………………………………………...........178

Section 3-6: Problems

No: 21, 22, 23, 24 ..………………………..……………………...…………………………….…………..182

Section 3-6: Practical

No: – MultiSim
25
 Section 3-6: The Exclusive-OR and Exclusive-NOR Gate
OUTCOMES
• Identify the exclusive-OR and exclusive-NOR gate by its symbol
• Describe the operation of exclusive-OR and exclusive-NOR gate
• Generate the truth table for exclusive-OR and exclusive-NOR gates
• Produce a timing diagram for a NOR gate with any specified input waveforms
• Discuss examples of exclusive-OR and exclusive-NOR gate applications

Section 3-6: LECTURER WORK SCHEDULE

Section 3-6: Content Detail

LESSON 20
The Exclusive-OR Gate ....................................................................................149
The Exclusive-NOR Gate ..................................................................................151
Operation with Waveform Inputs ...............................................................151
Example 3-21 .................................................................................................152
An Application ..............................................................................................152

Section 3-6: LEARNER WORK SCHEDULE

Section 3-6: Checkup

No: 1, 2, 3 ….………………………..…………………….………………..…………………………………...179

Section 3-6: Self Test

No: 7 ………………………………………………………………………………………………………...........178

Section 3-6: Problems

No: 25, 26, 27, 28 ..………………………..……………………...…………………………….…………..182

Section 3-6: Practical

No: – MultiSim

26
 Section 3-8: Fixed-Function Logic Gates
OUTCOMES
• List common 74 series gate logic functions
• List the major integrated circuit technologies
• Obtain data sheet information
• Define propagation delay time
• Define power dissipation
• Define unit load and fan-out
• Define speed-power product

Section 3-8: LECTURER WORK SCHEDULE

Section 3-8: Content Detail

LESSON 21
74 Series Logic Gate Function ..........................................................................161
74 Series Logic Circuit Families ........................................................................164
Performance Characteristics and Parameters ............................................164
Example 3-23 .................................................................................................167
Example 3-24 .................................................................................................168

Section 3-6: LEARNER WORK SCHEDULE

Section 3-6: Checkup

No: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 .…………………….………………..…………………………………...179

Section 3-6: Self Test

No: 17 …………………………………………………………………………………….………………...........178

Section 3-6: Problems

No: 33, 34, 35, 36, 37, 38 .……………..……………………...…………………………….…………..182

Section 3-6: Practical

No: – MultiSim

27
 LEARNING UNIT 4
CHAPTER 4
Boolean Algebra and Logic Simplification
Section 4-1: Boolean Operations and Expressions
OUTCOMES
• Define variable
• Define literal
• Identify sum and product terms
• Evaluate sum and product terms
• Explain Boolean addition and multiplication

Section 4-1: LECTURER WORK SCHEDULE

Section 4-1: Content Detail

LESSON 22

Boolean Addition ........................................................................................192

Example 4-1 ..................................................................................................192
Boolean Multiplication …………..………………………………………..………………………193
Example 4-2 ...................................................................................................193

Section 4-1: LEARNER WORK SCHEDULE

Section 4-1: Checkup

No: 1, 2, 3 ..…………………..…………………………………………………………………………………...193

Section 4-1: Self Test

No: 1, 2, 3, 4 ……….……………………………………………………………………………………..........250

Section 4-1: Problems

No: 1, 2, 3, 4, 5, 6 ………..…….………………………………………..….………………………………..251

Section 4-1: Practical

No: – MultiSim

28
 Section 4-2: Laws and Rules of Boolean Algebra
OUTCOMES
• Apply the commutative laws of addition and multiplication
• Apply the associative laws of addition and multiplication
• Apply the distributive law
• Apply twelve basic rules of Boolean algebra

Section 4-2: LECTURER WORK SCHEDULE

Section 4-2: Content Detail

LESSON 23

Laws of Boolean Algebra ............................................................................194

Rules of Boolean Algebra ............................................................................195

Section 4-2: LEARNER WORK SCHEDULE

Section 4-2: Checkup

No: 1, 2 ..…………………..……………………………………………………………………………………...199

Section 4-2: Self Test

No: 5, 6, 7, 8, 9 ……….………………………………………………………………………………..........250

Section 4-2: Problems

No: 7, 8 ………..…….………………………………………..……………….………………………………..251

Section 4-2: Practical

No: – MultiSim

29
 Section 4-3: DeMorgan’s Theorems
OUTCOMES
• State DeMorgan’s theorems
• Relate DeMorgan’s theorems to the equivalent of NAND and negative-OR gates
• Relate DeMorgan’s theorems to the equivalent of NOR and negative-AND gates
• Apply DeMorgan’s theorems to the simplification of Boolean expressions

Section 4-3: LECTURER WORK SCHEDULE

Section 4-3: Content Detail

LESSON 24

DeMorgan’s Theorems ................................................................................199

Example 4-3 ...................................................................................................200
Example 4-4 ...................................................................................................200
Example 4-5 ...................................................................................................201
Example 4-6 ...................................................................................................202
Example 4-7 ...................................................................................................203

Section 4-3: LEARNER WORK SCHEDULE

Section 4-3: Checkup

No: 1 ..…………………..………………………………………………………………………………………....203

Section 4-3: Self Test

No: 10, 11 ……….…………………………………………………………………..…………………..........250

Section 4-3: Problems

No: 9, 10, 11 ..…….………………………………………..……………….………………………………..251

Section 4-3: Practical

No: – MultiSim

30
 Section 4-4: Boolean Analysis of Logic Circuits
OUTCOMES
• Determine the Boolean expression for a combination of gates
• Evaluate the logic operation of a circuit from the Boolean expression
• Construct a truth table

Section 4-4: LECTURER WORK SCHEDULE

Section 4-4: Content Detail

LESSON 25

Boolean Expression for a Logic Circuit ........................................................203

Constructing a Truth Table for a Logic Circuit ............................................203
Example 4-8 ...................................................................................................204

Section 4-4: LEARNER WORK SCHEDULE

Section 4-4: Checkup

No: 1, 2 ………………..………………………………………………………………………………………....205

Section 4-4: Self Test

No: 11 ……….………………………………………………………………………...…………………..........250

Section 4-4: Problems

No: 12, 13, 14, 15, 16, 17, 18 ………………………..……………….………………………………..252

Section 4-4: Practical

No: – MultiSim

31
 Section 4-5: Logic Simplification Using Boolean Algebra
OUTCOMES
• Apply the laws, rules, and theorems of Boolean Algebra to simplify general expressions

Section 4-5: LECTURER WORK SCHEDULE

Section 4-5: Content Detail

LESSON 26

Logic Simplification Using Boolean Algebra .......................................................205

Example 4-10 .................................................................................................206
Example 4-11 .................................................................................................207
Example 4-12 .................................................................................................208
Example 4-13 .................................................................................................208

Section 4-5: LEARNER WORK SCHEDULE

Section 4-5: Checkup

No: 1, 2 ………………..………………………………………………………………………………….……....209

Section 4-5: Problems

No: 19, 20, 21, 22 …………………………………………………………….………………………………..252

Section 4-5: Practical

No: – MultiSim

32
 Section 4-6: Standard Form of Boolean Expressions
OUTCOMES
• Identify a sum-of-product expression
• Determine the domain of a Boolean expression
• Convert any sum-of-product expression to a standard form
• Evaluate a standard sum-of-product expression in terms of binary values
• Identify a product-of-sums expression
• Convert any product-of-sums expression to a standard form
• Evaluate a standard product-of-sums expression in terms of binary values
• Convert from one standard form to the other

Section 4-6: LECTURER WORK SCHEDULE

Section 4-6: Content Detail

LESSON 27

The Sum-of-Products (SOP) form ................................................................210

Conversion of a General Expression to SOP Form ......................................211
Example 4-14 .................................................................................................211
The Standard SOP Form …………………………………………………………………………………211
Example 4-15 .................................................................................................212
Example 4-16 .................................................................................................212
The Product-of-Sum (POS) form ..................................................................213
The Standard POS Form …………………………………………………………………………………213
Example 4-17 .................................................................................................214
Example 4-18 .................................................................................................215
Converting Standard SOP to Standard POS .................................................215
Example 4-19 .................................................................................................215
Section 4-6: LEARNER WORK SCHEDULE
Section 4-6: Checkup
No: 1, 2, 3 .……………..………………………………………………………………………………………....216

Section 4-6: Self Test

No: 12, 13, 14 ……….……………………………………………………………...…………………..........250

Section 4-6: Problems

No: 23, 24, 25, 26, 27, 28, 29, 30 …..…………………..…………….………………………………..253

Section 4-6: Practical

No: – MultiSim
33
 Section 4-7: Boolean Expressions and Truth Tables
OUTCOMES
• Convert a standard SOP expression to into truth table format
• Convert a standard POS expression to into truth table format
• Derive a standard expression from a truth table
• Properly interpret truth table data

Section 4-7: LECTURER WORK SCHEDULE

Section 4-7: Content Detail

LESSON 28

Converting SOP Expression to Truth Table Format ....................................216

Example 4-20 .................................................................................................216
Converting POS Expression to Truth Table Format ....................................217
Example 4-21 .................................................................................................217
Determining Standard Expressions from a Truth Table . ............................218
Example 4-22 .................................................................................................218

Section 4-7: LEARNER WORK SCHEDULE

Section 4-7: Checkup
No: 1, 2, 3 .……………..………………………………………………………………………………………....219

Section 4-7: Problems

No: 31, 32, 33, 34, 35, 36 ……………..…………………..…………….………………………………..254

Section 4-7: Practical

No: – MultiSim

34
 Section 4-8: The Karnaugh Map
OUTCOMES
• Construct a Karnaugh map for three or four variables
• Determine the binary value of each cell in a Karnaugh map
• Determine the standard product term represented by each cell in a Karnaugh map
• Explain cell adjacency and identify adjacent cells

Section 4-8: LECTURER WORK SCHEDULE

Section 4-8: Content Detail

LESSON 29

The 3-Variable Karnaugh Map ……...............................................................220

The 4-Variable Karnaugh Map .....................................................................220
Cell Adjacency ..............................................................................................220

Section 4-8: LEARNER WORK SCHEDULE

Section 4-8: Checkup

No: 1, 2, 3, 4 …………..………………………………………………………………………………………....222

Section 4-8: Self Test

No: 15, 16 ……….……………………………………………………………...…………………................251

Section 4-8: Problems

No: 37, 38, 39 …..…………………..…………….…………………………………………………………...254

Section 4-8: Practical

No: – MultiSim

35
 Section 4-9: Karnaugh Map SOP Minimization
OUTCOMES
• Map a standard SOP expression on a Karnaugh map
• Combine the 1’s on the map into maximum groups
• Determine the minimum products term to form a minimum SOP expression
• Convert a truth table into a Karnaugh map for simplification
• Use don’t care conditions on a Karnaugh map

Section 4-9: LECTURER WORK SCHEDULE

Section 4-9: Content Detail

LESSON 30

Mapping a Standard SOP Expression ..........................................................222

Example 4-23 .................................................................................................223
Example 4-24 .................................................................................................224
Mapping a Nonstandard SOP Expression ....................................................224
Example 4-25 .................................................................................................225
Example 4-26 .................................................................................................225
Karnaugh Map Simplification of SOP Expressions ......................................226
Example 4-27 .................................................................................................226
Example 4-28 .................................................................................................228
Example 4-29 .................................................................................................228
Example 4-30 .................................................................................................229
Example 4-31 .................................................................................................230
Mapping Directly from a Truth Table ..........................................................230
Don’t Care Conditions ..................................................................................230
Example 4-32 .................................................................................................232

Section 4-9: LEARNER WORK SCHEDULE

Section 4-9: Checkup

No: 1, 2, 3 …..…………..………………………………………………………………………………………....232

Section 4-9: Problems

No: 40, 41, 42, 43, 44, 45, 46, 47 ………….…………………………………………………………...254

Section 4-9: Practical

No: – MultiSim

36
 Section 4-10: Karnaugh Map POS Minimization
OUTCOMES
• Map a standard POS expression on a Karnaugh map
• Combine the 0’s on the map into maximum groups
• Determine the minimum sum term to form a minimum SOP expression
• Combine the minimum sum terms to form a minimum POS expression
• Use the Karnaugh map to convert between POS and SOP

Section 4-10: LECTURER WORK SCHEDULE

Section 4-10: Content Detail

LESSON 31

Mapping a Standard POS Expression ..........................................................233

Example 4-33 .................................................................................................233
Karnaugh Map Simplification of POS Expressions ......................................234
Example 4-34 .................................................................................................234
Example 4-35 .................................................................................................235
Converting Between POS and SOP Using the Karnaugh Map .....................235
Example 4-36 .................................................................................................236

Section 4-10: LEARNER WORK SCHEDULE

Section 4-10: Checkup

No: 1, 2, 3 …..…………..………………………………………………………………………………………....237

Section 4-10: Problems

No: 48, 49, 50, 51, 52 …………………………….…………………………………………………………...255

Section 4-10: Practical

No: – MultiSim

37
 LEARNING UNIT 5
CHAPTER 5
Combination Logic Analysis
Section 5-1: Basic Combinational Logic Circuits
OUTCOMES
• Analyze and apply AND-OR circuits
• Analyze and apply AND-OR-Invert circuits
• Analyze and apply exclusive-OR gates
• Analyze and apply exclusive-NOR gates

Section 5-1: LECTURER WORK SCHEDULE

Section 5-1: Content Detail

LESSON 32

AND-OR Logic ..............................................................................................262

Example 5-1 ..................................................................................................263
AND-OR-Invert Logic …………..………………………………………..…………………….……263
Example 5-2 ...................................................................................................264
Exclusive-OR Logic .......................................................................................265
Exclusive-NOR Logic .....................................................................................265
Example 5-3 ...................................................................................................266
Example 5-4 ...................................................................................................266

Section 5-1: LEARNER WORK SCHEDULE

Section 5-1: Checkup

No: 1, 2, 3, 4 ..…………………..………………………………………………….…………………………...266

Section 5-1: Self Test

No: 1, 2, 3, 4 ……….……………………………………………………………………………………..........300

Section 5-1: Problems

No: 1, 2, 3, 4, 5, 6, 7 ……..…….………………………………………..….………………………………..301

Section 5-1: Practical

No: – MultiSim

38
 Section 5-2: Implementing Combinational Logic
OUTCOMES
• Implement a logic circuit from a Boolean expression
• Implement a logic circuit from a truth table
• Minimize a logic circuit

Section 5-2: LECTURER WORK SCHEDULE

Section 5-2: Content Detail

LESSON 33

From a Boolean Expression to a Logic Circuit .............................................267

From a Truth Table to a Logic Circuit ..........................................................269
Example 5-5 ...................................................................................................269
Example 5-6 ...................................................................................................270
Example 5-7 ...................................................................................................271
Example 5-8 ...................................................................................................272

Section 5-2: LEARNER WORK SCHEDULE

Section 5-2: Checkup

No: 1, 2, 3 ….…………..………………………………………………………………………………………....272

Section 5-2: Self Test

No: 5, 6 ………….……………………………………………………………...…………………................300

Section 5-2: Problems

No: 8, 9, 10, 11, 12, 13, 1, 15, 16, 17, 18, 19 ……….…………………………………………...302

Section 5-2: Practical

No: – MultiSim

39
 Section 5-3: The Universal Property of NAND and NOR
Gates
OUTCOMES
• Use NAND gates to implement the inverter, AND, OR and NOR gate
• Use NOR gates to implement the inverter, AND, OR and NOR gate

Section 5-3: LECTURER WORK SCHEDULE

Section 5-3: Content Detail

LESSON 34

The NAND Gate as a Universal Logic Element .............................................273

The NAND Gate as a Universal Logic Element .............................................273

Section 5-3: LEARNER WORK SCHEDULE

Section 5-3: Checkup

No: 1, 2 ….…………..……………………………………………………………………………………………...274

Section 5-3: Self Test

No: 7 ………….……………………………………………………………...………………………................300

Section 5-3: Problems

No: 20, 21, 22, 23 ……….……………………………………………………………………………………..304

Section 5-3: Practical

No: – MultiSim

40
 Section 5-4: Combinational Logic Using NAND and NOR
Gates
OUTCOMES
• Use NAND gates to implement a logic function
• Use NOR gates to implement a logic function
• Us the appropriate dual symbol in a logic diagram

Section 5-4: LECTURER WORK SCHEDULE

Section 5-4: Content Detail

LESSON 35

NAND Logic ...................................................................................................275

Example 5-9 ...................................................................................................277
Example 5-10 .................................................................................................277
NOR Logic .....................................................................................................277
Example 5-11 .................................................................................................279

Section 5-4: LEARNER WORK SCHEDULE

Section 5-4: Checkup

No: 1, 2 ….…………..……………………………………………………………………………………………...279

Section 5-4: Self Test

No: 8, 9, 10 ………….…………………………………………………...………………………................300

Section 5-4: Problems

No: 24, 25, 26, 27 ……….……………………………………………………………………………………..304

Section 5-4: Practical

No: – MultiSim

41
 Section 5-5: Pulse Waveform Operation
OUTCOMES
• Analyze combinational logic with pulse waveform inputs
• Develop a timing diagram for any given combinational logic circuit with specified inputs
• Us the appropriate dual symbol in a logic diagram

Section 5-5: LECTURER WORK SCHEDULE

Section 5-5: Content Detail

LESSON 36

Pulse Waveform Operation .........................................................................279

Example 5-12 .................................................................................................280
Example 5-13 .................................................................................................280
Example 5-14 .................................................................................................281
Example 5-15 .................................................................................................282

Section 5-5: LEARNER WORK SCHEDULE

Section 5-5: Checkup

No: 1, 2 ….…………..……………………………………………………………………………………………...282

Section 5-5: Problems

No: 28, 29, 30, 31, 32, 33 …………………………………………………………………………………..304

Section 5-5: Practical

No: – MultiSim

42
 LEARNING UNIT 6
CHAPTER 6
Functions of Combination Logic
Section 6-1: Half and Full Adders
OUTCOMES
• Describe the function of a half-adder
• Draw a half-adder logic diagram
• Describe the function of a full-adder
• Draw a full-adder logic diagram using half adders
• Implement a full-adder using AND-OR logic

Section 6-1: LECTURER WORK SCHEDULE

Section 6-1: Content Detail

LESSON 37

The Half-Adder ............................................................................................314

The Full-Adder .............................................................................................315
Example 6-1 ..................................................................................................316

Section 6-1: LEARNER WORK SCHEDULE

Section 6-1: Checkup

No: 1, 2 ..……..…………………..………………………………………………….…………………………...317

Section 6-1: Self Test

No: 1, 2, 3 ………….……………………………………………………………………………………..........372

Section 6-1: Problems

No: 1, 2, 3 …………………..…….………………………………………..….………………………………..373

Section 6-1: Practical

No: – MultiSim

43
 Section 6-2: Parallel Binary Adders
OUTCOMES
• Use full-adders to implement a parallel binary adder
• Explain the addition process in a parallel binary adder
• Use the truth table for a 4-bit parallel adder
• Apply two 74HC283 IC’s for the addition of two 8-bit numbers
• Expand the 4-bit adder to accommodate 8-bit or 16-bit addition

Section 6-2: LECTURER WORK SCHEDULE

Section 6-2: Content Detail

LESSON 38

Parallel binary Adders .................................................................................317

Example 6-2 ..................................................................................................318
Four-bit Parallel Adders ..............................................................................319
Example 6-3 ..................................................................................................319
Adder Expansion ..........................................................................................321
Example 6-4 ...................................................................................................322

Section 6-2: LEARNER WORK SCHEDULE

Section 6-2: Checkup

No: 1, 2 ..……..…………………..………………………………………………….…………………………...317

Section 6-2: Self Test

No: 4, 5 ………….………………………………………………………………………………….……..........372

Section 6-2: Problems

No: 4, 5, 6, 7, 8, 9, 10 ....…….………………………………………..….………………………………..374

Section 6-2: Practical

No: – MultiSim

44
 Section 6-3: Ripple Carry and Look-Ahead Carry Adders
OUTCOMES
• Discuss the difference between a ripple carry adder and a look-ahead carry adder
• State the advantage of look-ahead carry addition
• Define carry generation and carry propagation and explain the difference
• Develop look-ahead carry logic
• Explain why cascaded 74HC283 IC’s exhibit both ripple carry and look-ahead carry
properties

Section 6-3: LECTURER WORK SCHEDULE

Section 6-3: Content Detail

LESSON 39

The Ripple Carry Adder ...............................................................................324

The Look-Ahead Carry Adder ......................................................................325
Combination Look-Ahead and Ripple Carry Adders ...................................327

Section 6-3: LEARNER WORK SCHEDULE

Section 6-3: Checkup

No: 1, 2 ..……..…………………..………………………………………………….…………………………...327

Section 6-3: Problems

No: 11, 12 ………………......…….………………………………………..….………………………………..375

Section 6-3: Practical

No: – MultiSim

45
 Section 6-4: Comparators
OUTCOMES
• Use the exclusive-NOR gate as a basic comparator
• Analyze the internal logic of a magnitude comparator that has both equality and
inequality outputs
• Apply the 74HC85 comparator to compare the magnitudes of two 4-bit numbers
• Cascade 74HC85 IC’s to expand a comparator to eight or more bits

Section 6-4: LECTURER WORK SCHEDULE

Section 6-4: Content Detail

LESSON 40

Equality ……………………..................................................................................328
Example 6-5 ..................................................................................................328
Inequality ....................................................................................................329
Example 6-6 ..................................................................................................329
Example 6-7 ..................................................................................................331

Section 6-4: LEARNER WORK SCHEDULE

Section 6-4: Checkup

No: 1, 2 ..……..…………………..………………………………………………….…………………………...317

Section 6-4: Self Test

No: 6 …..………….………………………………………………………………………………….……..........372

Section 6-4: Problems

No: 13, 14, 15 ....…….………………………………………..….…………………..…………………..…..376

Section 6-4: Practical

No: – MultiSim

46
 Section 6-5: Decoders
OUTCOMES
• Define decoder
• Design a logic circuit to decode any combination of bits
• Describe the 74HC154 binary-to-decimal decoder
• Expand decoders to accommodate larger numbers of bits in a code
• Describe the 74HC42 BCD-to-decimal decoder
• Describe the 74HC7 BCD-to-7 segment decoder
• Discuss zero suppression in 7-segment displays

Section 6-5: LECTURER WORK SCHEDULE

Section 6-5: Content Detail

LESSON 41

The Basic Binary Decoder ...........................................................................332

Example 6-8 ..................................................................................................332
The 4-bit Decoder .......................................................................................333
Example 6-9 ..................................................................................................335
BCD-to-Decimal Decoder ............................................................................336
Example 6-10 ................................................................................................337
BCD-to-7 Segment Decoder ........................................................................338

Section 6-5: LEARNER WORK SCHEDULE

Section 6-5: Checkup

No: 1, 2, 3 ..……..…………………..…………………………………………………..……………………...341

Section 6-5: Self Test

No: 7, 8 ………….………………………………………………………………………………….……..........373

Section 6-5: Problems

No: 16, 17, 18, 19, 20, 21, 22 ..………………………..….…………………..…………………..…..377

Section 6-5: Practical

No: – MultiSim

47
 Section 6-6: Encoders
OUTCOMES
• Determine the logic for a decimal-to-BCD encoder
• Explain the purpose of the priority feature in encoders
• Describe the 74HC147 Decimal-to-BCD encoder

Section 6-6: LECTURER WORK SCHEDULE

Section 6-6: Content Detail

LESSON 42

The Decimal-to-BCD Encoder .....................................................................341

Example 6-11 ................................................................................................343

Section 6-6: LEARNER WORK SCHEDULE

Section 6-6: Checkup

No: 1, 2 ..……..…………………..…………………………………………………..………………………....344

Section 6-6: Self Test

No: 9, ………….…………………………………………………………………………………….……..........373

Section 6-6: Problems

No: 23, 24 …………………………....………………………..….…………………..…………………..…..377

Section 6-6: Practical

No: – MultiSim

48
 Section 6-7: Code Converters
OUTCOMES
• Explain the process for converting BCD to binary
• Use exclusive-OR gates for conversions between binary and Gray codes

Section 6-7: LECTURER WORK SCHEDULE

Section 6-7: Content Detail

LESSON 43

BCD-to-Binary Conversion ..........................................................................345

Example 6-12 ................................................................................................346
Example 6-13 ................................................................................................347

Section 6-7: LEARNER WORK SCHEDULE

Section 6-7: Checkup

No: 1, 2 ..……..…………………..…………………………………………………..………………………....347

Section 6-7: Problems

No: 25, 26, 27 …………………………....………………………..….……………..…………………..…..377

Section 6-7: Practical

No: – MultiSim

49
 Section 6-8: Multiplexers (Data Selectors)
OUTCOMES
• Explain the basic operation of a multiplexer
• Describe the 74HC153 and the 74HC151 multiplexer
• Expand a multiplexer to handle more data inputs
• Use the multiplexer as a logic function generator

Section 6-8: LECTURER WORK SCHEDULE

Section 6-8: Content Detail

LESSON 44

Multiplexers (Data Selectors) .....................................................................347

Example 6-14 ................................................................................................349
Example 6-15 ................................................................................................352
Example 6-16 ................................................................................................354
Example 6-17 ................................................................................................355

Section 6-8: LEARNER WORK SCHEDULE

Section 6-8: Checkup

No: 1, 2, 3, 4 ..…………………..…………………………………………………..………………………....356

Section 6-8: Self Test

No: 10, 11 ………….……………………………….…………………………………………….……..........373

Section 6-8: Problems

No: 28, 29, 30 …………………………....………………………..….…………………..…………….…..378

Section 6-8: Practical

No: – MultiSim

50
 Section 6-9: Demultiplexers
OUTCOMES
• Explain the basic operation of a demultiplexer
• Describe how a 4-line-to-16-line decoder can be used as a demultiplexer
• Develop the timing diagram for a demultiplexer with specified data and data selection
inputs

Section 6-9: LECTURER WORK SCHEDULE

Section 6-9: Content Detail

LESSON 45

Demultiplexers ……………………......................................................................356
Example 6-18 ................................................................................................357
4-Line-to-16-Line Decoder as a Demultiplexor .........................................357

Section 6-9: LEARNER WORK SCHEDULE

Section 6-9: Checkup

No: 1, 2 ……....…………………..…………………………………………………..………………………....358

Section 6-9: Problems

No: 31 …………………………....………………………………..…..….…………………..…………….…..378

Section 6-9: Practical

No: – MultiSim

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 Section 6-10: Parity Generators/Checkers
OUTCOMES
• Explain the concept of parity
• Implement a basic parity circuit with exclusive-OR gates
• Describe the operation of basic parity generating and checking logic
• Discuss the 74HC280 9-bit parity generator/checker

Section 6-10: LECTURER WORK SCHEDULE

Section 6-10: Content Detail

LESSON 45

Basic Parity Logic ........................................................................................359

A Data Transmission System with Error Detection .... ...............................360

Section 6-10: LEARNER WORK SCHEDULE

Section 6-10: Checkup

No: 1, 2, 3 ..…………………..……………………………………………………..………………………....362

Section 6-10: Self Test

No: 12 ………….……………………………….…………………………………………….……...............372

Section 6-10: Problems

No: 32, 33 ………………………………....………………………..….…………………..…………….…..379

Section 6-10: Practical

No: – MultiSim

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 Part 3
PRACTICALASSIGNMENTS
POLICY FOR PRACTICAL CLASSES
1. Drinking and eating are not allowed in the practical classroom.
2. You will be allocated to a position in the practical classroom which is marked with a number.
You are responsible for the equipment allocated to this position. The technician will make a
note of your position.
3. Every learner must do his own practical, however students are allowed to help one another in
a constructive manner.
4. All learners must have their own practical guide, no second hand book or a copy of the
practical assignment book will be allowed.
5. Practical assignments must be build by the learner him/herself during the practical period. All
Practical assignments must be done on the opposite page of the assignment you are busy with,
in the practical assignments guide.
6. Preparation of practical assignments will be evaluated using the following criteria:
Neatness, Logic circuit layout, Completeness and Initiative.
7. Construction of practical assignment will be evaluated using the following criteria:
Overall neatness
Correct wiring techniques
Correct layout of components
Correct working of circuit
Student’s knowledge of circuit
Correct method for wiring the bus bar
Safety precautions (Supply off when building logic circuit)
Ability to do fault finding
8. Learners must prepare their practical assignments before attempting to build any of the logic
circuits. Due to the limited time available during a practical period this preparations must be
done before entering the practical room.
9. No learners are allowed in the technician’s area at the back of the laboratory.
10. All practical work (preparations etc.) must be done in practical book.
11. Students not obeying to these rules could face disciplinary steps against him/her which can
lead to the expulsion of the practical class.
12. Completed practical assignment book must be handed in at the end of the semester.
13. Students must also contribute to the neatness of the lab.
14. Do not play with the computer, changing background etc.

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 Multisim Circuit Simulation
CHAPTER 7
Section 7.1: Latches
OBJECTIVE:

Testing the operation of a latch with enable & disable functions.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Start simulation by pressing the F5 key or by clicking on the simulated switch in the top right
handcorner of the screen. To stop simulation press the F5 key or the simulated key again.
5. Use the Space key on the keyboard to change the switch between 1 and 0. This will enable or
disable the latch.
6. If the circuit is properly connected the LED will flash on and off (blink) if the latch is enabled
andstay in one condition if disabled.
7. Double click on the scope to observe the output pulse in relation to the input. The top pulse is
theinput and the bottom pulse the output. Again enable and disable the latch, while observing
theoutput on the oscilloscope.

(Note: If the enable, disable switch does not work while simulating on the scope, first pause
simulation, then switch to enable or disable, then disable pause.)

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 Section 7.2: Flip/Flops
OBJECTIVE:

Testing the operation of a J-K F/F with Preset and Clear.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Double click on the scope to observe the output pulse in relation to the input.
5. Switch 1 (S2) is connected to the S (PRESET) input. Use the A key on the keyboard to change
to a “1" or “0". Notice the change in the output pulse and the LED when doing so.
6. Switch 2 (S2) is connected to the R (CLR) input. Use the B key on the keyboard to change to a
“1" or “0". Notice the change in the output pulse and the LED when doing so.
7. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.
8. Test the following conditions: Toggle, Preset and Clear.

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Section 8.1: Bi-directional Shift Register
OBJECTIVE:

Testing the operation of a 4-bit bi-directional shift register.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Double click on the logic analyser to observe the output pulse in relation to the input.
5. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.
6. Clear the register using Key 1.
7. Make switch J2 (S0) a 1 and J1 (S2) a 0. The register will now be in the shift right mode and
since the Serie-Right (SR) input is connected to 1 the register will be filled with 1’s.
8. Make switch J2 (S0) a 0 and J1 (S2) a 10. The register will now be in the shift left mode and
since the Serie-Left (SL) input is connected to 0 the register will be filled with 0’s.

44
Section 8.2: Register Counters – Johnson Counter
OBJECTIVE:

Testing the operation of a Johnson Counter.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Double click on the logic analyser to observe the output pulse in relation to the input.
5. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.

45
Section 8.3: Register Counters – Ring Counter
OBJECTIVE:

Testing the operation of a Ring Counter.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Switch J1 (Key 1) will clear all the outputs of the register.
4. Switch J2 (Key 2) will Preset the register with a “1" when changed to the “0" position.
5. Complete the wiring using the circuit below as a guideline.
6. Double click on the logic analyser to observe the output pulse in relation to the input.
7. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.

46
Section 9.1: 4-Bit Asynchronous Counter
OBJECTIVE:

Testing the operation of a 4-Bit asynchronous counter.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Double click on the logic analyser to observe the output pulse in relation to the input.
5. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.
6. Also do the necessary connections to simulate a Modulus 12 counter.

47
Section 9.2: 4-Bit Synchronous Counter
OBJECTIVE:

Testing the operation of a 4-bit synchronous counter with Clear and Loadconnections.

INSTRUCTIONS:
1. Double click on the Multisim Icon located on the desktop.
2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Switch J is connected to the clear (CLR) input of the counter. Use key 1 on the keyboard to
clearthe output. “0" = Clear
5. Switch J6 is connected to the load input of the counter. Use key 1 on the keyboard to change
toa “1" or “0". “0" = Load. “1" = Count
6. Switches J1 (A), J2 (B), J3 © and J4 (D) represent the binary value that will be loaded into the
counter when the load signal is LOW.
7. Press F5 on the keyboard or the simulated switch on the screen to simulate the circuit and also
toterminate the simulation process.
8. Simulate the following conditions: CLR, Load and Counting.

48
Section 9.3: Synchronous Up/Down Counter
OBJECTIVE:

Testing the operation an Up/Down counter.

INSTRUCTIONS:

1. Double click on the Multisim Icon located on the desktop.

2. Open the file on the hard disk.
3. Complete the wiring using the circuit below as a guideline.
4. Switch J1 Key 1 is connected to the U/D control input of the counter. Use key 1 on the
keyboardto make the counter counting up or down.
5. The load option is not used because we have done that in the previous practical. Therefore the
LOAD signal is directly connected to VCC.
6. Press F5 on the keyboard or the simulated switch on the screen to simulate the up/down
countingof the circuit and also to terminate the simulation process.

49