Page No... 1 ECé4.— USN Sixth Semester B.E. Degree Examination, July/August 2005 Electronics and Communication /Telecommunications Engineering Digital System Design using VHDL “Time: 3 brs.) (MaxMarks : 100 Note: Answer any FIVE full questions. Alll questions carry equal marks. 1. (@) Write a behavioral description of JK flipflop with. active low clock, set and reset using process statement, (6 Marke) (0) Write a data flow description for the given ‘equation using process statement (i/p:2, elk o/p:z) Z=X1Qh4+XQs OF = Bs A =O 5 OF =O:Q2A24+ X1QiGE +X Qi QL marks) (©) Differentiate between signal assignment and variable assignment with a suitable aanpl, 2. (@) Evaluate the given expression. Is it true ? Qh and not B oc for and D) = 1000.1 1" where Ax"1 0 1”: Be‘ 11"; ="1000 10"; D="110 (marks) (b) Specify the declaration form for package and package body with an example. — (6 Marks) (©) Write a VHDL description for a SR latch. i) use a conditional assignment statement il) Use a characteristic equation iil) Use two logic gates (8 Marks) 3. (@) White a VHDL description for a 74194 4-bit bidirectional shift register. (6 Marks) Se a a = }__ SDL ‘SDR “sr Po— curs 7aI94 80 CLK pil vd ot ToePage No... 2 EC64 (0) Find the reduced PLA table to realize the following functions : fa(a,b,¢,d) = Sym (4,5,10, 11, 12) fr(a,b,¢,d) = > m (0,1,3,4,8,11) and fa(a;b,¢,d) = Sym (0,4,10,11, 14) (6 Marts) (c) Write a VHDL code for 4-bit adder with Rise/Fall time modeling using generic bas tn] (6 Marks) 4, (a) Implement the traffc-light controller using 74163 counter with added logic. Use a ROM to generate the ops. (6 Maks) (0) Design a keypad scanner for the following Keypad layout & 4 & & . . 7 i R 7 c R E D Ro (8 Marks) (c) Bring out the differences between transport delay and internal delay with suitable examples. (6 tarts) 5. (a) Design a 4bit binary mulipfier and generate the control state graph and table which defines the operation of a binary muttipier. (@ Marks) (0) Realize the control circuit of 4-bit serial muttiptor using a PLA and D flip flops. (@ Marks) (©) Write a VHDL code for 2 input Nor gate with Rise/Fall time modeling using generic ‘statement. (4 Marks) 6. (@) Wtite a VHDL description for 4-bit binary multiplier for the SM chart as shown below. (8 Marks) $3/Done Contd... 3Page No... 3 EC64 (®) Write a VHDL description for a divider thal divides an 8-bit dividend by a 6-bit divisor to give a Sbit quotient. The dividend register should be loaded when St=1 (@ Marks) (©) Write a VHDL code for synthesis of a sequential IF statement (4 Marks) 7. (@) The PLA realization of a Dice game is as shown in-figure. Write a VHDL code for the same. (@ Marks) (b) Implement a 4.x 4 array multiplier using Xilinx 4000 series. (mates) (6) Write a behavioral description of RAM 6116 using process statement. (6 Maris) 8. (a) Implement a 8-1 Mux using an Altera 7000 series device. Give the logic equations and determine the number of macro cells required if parallel expandars are used. (6 Marks) (0) Write a VHDL code for the floating point subtracter. (6 Marks) (©) Write a VHDL model for an N-bit bidirectional shift register using a generic statement, Define a component that represents one bit of the shift register. The component port shouid be port (L.R, CLR, CLK, Pin, Lin, Rin: in bit; Q : out bit); such that LR = 00 , do nothing ; LR = 04, shift ight : LR=10, shit i=11 parallel load. (@ Marks)Reg. No. Sixth Semester B.E. Degree Examination, January/February 2006 Electronics & Communication/Telecommunication Engineering Digital System Design Using VHDL Time: 3 hrs.) (Mox.Marks : 100 Note: Answer any FIVE full questions, 1. @ Explain briefly : Entity architecture pair jt) Package in VHDL (645 Marks) () Write a VHDL code for a full subtracter using logic equation. (6 Marks) (@) If A=1100, B=1110, C=1001, compute Yj = not A and B nor 2 ¥; = Bsa 2 and Cal 2 (4 Maris) 2. (@) What Is meant by variables, signals and constants in VHOL? Compare signais with variables, give an example for each. (10 Marrs) (©) Write a VHDL module for a universal shift register with folowing functions. MR Active low, a synchronous reset I/P that resets all fipflops, Two control inputs (515p) when 00, no action, when 10, register is shifted right and serial data SR enters Qo, when 01, 4 bit data shifted left and SL enters Qs. If $159 = 11, 4 bit data is loaded parallaly. (@ Marks) (©) Specify the general form of case statement. (2 Marks) 3. (@) Realize the following functions using PLA. Fy =D m(2,3,5,7,8,9,10,11, 13,15) Fy = Dm(2,3,5,6,7,10,11, 14,15) Fy = Dm(6,7,8,9,13, 14,18) Write VHDL code for implementation of F,, Fs and Fy (6+6 Maks) Contd... 2Page No... 2 EC64 (®) Write a VHDL code for D filptiop that reports error for setup and hold time violation. Assume set up time = hold time = Sns and display text string as violation of setup (Or hold time. (@ Mars) (@) Wilte state diagram that generates control signals for 4x4 bit multiplier. Explain with block diagram, (8 Marks) (©) Design signed multiplier and write a VHDL code to muttiply two signed numbers. (646 Marks) (@) Derive a SM chart to realize DICE game. (10 Marks) (®) Using PLA and D flip flops realize the $M chart for the dice game. 10 Marks) (@ Explain briefly with neat sketch Kilink 3000 seties I/O block, (@ Marks) (®) Write o function Fadd ion VHDL to realize full adder operation. Design 4 bit porallel ‘adder using full adders and write behavioral model for 4 bit parallel adder that uses function Fada, (6+6 Marks) (@) What is meant by attributes. Explain signal attribution with an example for each. (246 Marks) (b) Write a VHDL code for Tfipfiop. Using T fipflop as component write structural model for 8 bit up Counter. Assume active low asynchronous clear input and falling edge triggered clock. Use Generate statement (2+4 Marks) (©) Write @ VHDL module for memory model (RAM61 16). Assume 8 bit address lines, 8 bit data lines, active low chip enable and active low write enable. (6 Marks) Write short notes on any FOUR (@) Transport ond inertial delay (b) Generic (©) Signet resolution (@) Modeling mealy machine (@) VHDL procedures. (6x4=20 Marks)Page No...1 EC 64 Sixth Semester B.E. Degree Examination, July 2006 E&C Digital System Design using VHDL Time: 3 brs.] (Max. Marks: 100 Note: Answer any FIVE full questions. 1 a. Explain structural and behavioral description with examples (08 Marks) b. Differentiate between : i) Signal and variable assignment ii) Event and transactions. (06 Marks) co. Write @ VHDL program for detecting the number of 1’s in an cight bit-vector. If even, it should output ‘0’; if odd, output = *1'. (06 Marks) 2 a IF A=110101 B=110010,compute(A $112) OR (B SIA3) (04 Marks) b. A Moore sequential machine with two inputs x1 and x2 and output z has the following state table. State | X1 X2 | Z aoe o 0 iat rf i) 2 41 1 Write the VHDL code at behavioral level. State changes occur afier 5 ns and output changes occur 5 ns after state changes. (08 Marks) cc. Realize using ROM and DFF and write the VHDL code using ROM table for PS NS W=0 W-1 Z 00 00 O01 0 01 00 10 0 10 10 O01 0 11 10 01 21 (08 Marks) 3a. Find aminimum row PLA table to implement the following sets of functions £,(AB.CD) = m(3,46,9,11) £, (ABCD) = Dm (2,48,10,11,12) (ABCD) = Ym(3,6.7,10,11) and realize these functions using a PLA. (06 Marks) ‘A counter has the count sequence as shown. Realise the counter using 16 R4 PAL. Draw the section of the PAL where this function is implemented, > (0, ee D Ce bee (10 Marks) Write a VHDL code for the resolution function for X, 0, 1, 2 logic. (04 Marks) Contd...2Page No. 4a b. Soa b. 6 a 6 7 4 b. ° 8 a, b e. 2 EC 64 Draw and explain the block diagram of a 3 digit BCD to binary converter and draw the state graph for the same. (08 Marks) Draw the block diagram, state graph and VHDL program for the behavioral model ofa4 x 4 multiplier, (02 Marks) Design and explain an 8 bit divider wherein dividend is 8 bit and divisor is 4 bit. The shift and subtract action should take place in the same cycle. Draw the block diagram and state diagram, (10 Marks) Give the contents of the dividend register with respect to clock eycle for the given dividend and divisor. Shift and subtract in separate clock cycles. Dividend-01 11000010 divisor 100 01 (10 Marks) For the following Sm chart give the timing diagram showing the clock, states , input and output. Give the PLA table, Fig. 6(a) (10 Marks) Implement a bit binary counter using one Xilinx 3000 series logic cell. Qx is the LSB bit and Qy is the MSB of the counter. The counter has an asynchronous reset and a synchronous load. The counter operates as follows : En=0 no change En=1. Ld=1 load Qx and Qy with inputs u and v Er Ld=0 2 increment count ’) Give the next state equations for Qx and Qy ii) Label the inputs on the FG mode diagram and show the connection paths (10 Marks) Write a VHDL code for a static Ram with truth table (08 Marks) CS OF «WE mode Vo pins HX —-X_— notselected high z LH -H_outputdisabled high z L L H read data out qt x L write Data in Write 2 VHDL’ function that will find the dot product Yai * bi of two integer vectors a and b. (06 Marks) Explain signal attributes with examples. (06 Marks) Explain the Xilinx 3000 series logic cell (07 Maris) Explain transport and inertial delays with examples. (06 Marks) Write a VHDL code and synthesized circuit for case statement. (07 Marks)Page No...1 EC64 Sixth Semester B.E. Degree Examination, Dec. 06 / Jan. 07 EC/TE Digital System Design Using VHDL Time: 3 hrs.] [Max. Marks:100 Note: Answer any FIVE full questions. 1a. Usinga single bit subtractor, write a VHDL code for 4-bit subtractor. (08 Marks) b. Differenciate between the conditional assignment statement and single assignment statement with respect to 4: 1 Mux. (06 Marks) c. What are the predefined unconstrained arrays? Explain each with an example. (06 Marks) 2 a. Bring out the differences between VHDL function and VHDL procedure with an example. (06 Marks) b. Draw the structure of a 8-bit counter using 74163. Write a VIDDL description for a 8- bit counter using 74163 model. (08 Marks) ©. Write a VHDL code for synthesis of a sequential CASE statement. (06 Marks) 3. a. Write a VHDL description that converts a 5-bit bit_vector to an integer. (08 Marks) b. Realize the following functions using PLA : (06 Marks) fi(ab,e.d )= Yom (23,5,7,8,9,10,11,13,15) , fifabed) = Som (2,3,5,6,7,10,11,14,15) and fy(a,b.ed) = 9m (6,7.8,9.13,14.15) ‘c. Model the tristate buffers with active ~ high output enable. (06 Marks) > a a t Fig3(c) 4 a, Design a 6-bit binary up-down counter using a 22V10 and a minimum number of ‘external gates. Write the VHDL code for the counter using PLA. (10 Marks) b, Design a keypad scanner for the following keypad layout. (10 Marks) ‘| | i 2ealas R 516 Ro a) Ri o | # Ro Contd...2Page No...2 EC64 a. Design a 4-bit serial adder with accumulator and generate the control state graph and table which defines the operation of a serial adder. (08 Marks) b. Write a VHDL module that describes one bit of a full adder with accumulator . The control i/p Ad = 1 add operation and Load = | load the i/p to the accumulator, (06 Marks) c, Write a VHDL code for 2 input Nor gate with Rise / Fall time modeling using generic statement, (06 Marks) a, Write a test-bench for the Dice game problem to test the game components. (10 Marks) b. ‘The functional equivalent of a static RAM ceil is as shown in figure. Write a VEDL code to realize the functionality (10 Marks) Dat G=1, Q follows D D G=0. data is latched Fig. 6(b) a. Give sequence of simulator commands that would test the divider for the case 93 divided by 17. (06 Marks) b, Write a VHDKL code for the resolution function for X 0 1 Z logic. (06 Marks) c. Realize the SM chart given using a PLA, counter and 4-1 Mux. (08 Marks) ° phi (2) —~ Fig.7(0) a. Show how to realize the following combinational function using two 3000 series logic cells. (10 Marks) EF =X ! Xp X31 Xo + Xo! Kg! KiXo! + Nyy! Ry! + XpNoXql Xo + Ka! NEKANSNG + Ky b. Write a VHDL code using One-hot assignment for the following specifications To : QOQ1Q2Q3=1000 ; TI=0100 ; T2=0010 ; T4=0001 Q3* = XI Q0+X2. QI + X3.Q2+X4Q3; Z1=X1Q0+X3Q2 ; Z2=X2Q1+X4Q3; (10 Marks)Page No...1 EC64 USN L] Sixth Semester B.E. Degree Examination, Dec. 06 / Jan. 07 EC/TE Digital System Design Using VHDL Time: 3 brs.] {Max. Marks:100 Note : Answer any FIVE full questions. 1a. Using a single bit subtractor, write a VHDL code for 4-bit subtractor. statement with respect to 4: 1 Mux. (08 Marks) a b. Differenciate between the conditional assignment statement and single assignment (06 Marks) ¢. What are the predefined unconstrained arrays? Explain each with an example, (06 Marks) 2 a. Bring out the differences between VHDL function and VHDL procedure with an example. (06 Marks) b. Draw the structure of a 8-bit counter using 74163. Write a VHDL description for a 8- bit counter using 74163 model. ©, Write a VHDL code for synthesis of a sequential CASE statement. Write a VHDL description that converts a S-bit bit_vector to an integer. Realize the following functions using PLA : £,(@,b,c,d ) = Ym (2,3,5,7,8,9,10,11,13,15) , oe (08 Marks) (06 Marks) (08 Marks) (06 Marks) f@bod) = Yim (2,3,5,6,7,10,11,14,15) and fy(a,b,¢,d) = Ym 6,7,8,9,13,14,15) ¢. Model the tristate buffers with active ~ high output enable. Fig3(c) (06 Marks) 4 a Design a 6-bit binary up-down counter using a 22V10 and a minimum number of extemal gates. Write the VHDL code for the counter using PLA. b. Design a keypad scanner for the following keypad layout, ‘ f 2.3 }>* RB 5] 6 +> R spo +> R 0 TE ++ RB (0 Marks) (10 Marks) Contd...2Page No...2 EC64 5 ay Design a 4-bit serial adder with accumulator and generate the control state graph and table which defines the operation of a serial adder. (08 Marks) b. Write a VHDL module that describes one bit of a full adder with accumulator . The control i/p Ad= I add operation and Load = 1 load the i/p to the accumulator. (06 Marks) ¢. Write a VHDL code for 2 input Nor gate with Rise / Fall time modeling using genetic statement. (06 Marks) 6 a. Write a test-bench for the Dice game problem to (est the game components. (10 Marks) b. The functional equivalent of a static RAM cell is as shown in figure. Write a VHDL code to realize the functionality (10 Marks) Data inte actrees G D G Q & Data out 1, Q follows D data is latched Sel! gq G eee) Fig. 6(b) 7a. Give sequence of simulator commands that would test the divider for the case 93 divided by 17. (06 Marks) b. Write a VIIDKL code for the resolution function for X 0 1 Z logic. (06 Marks) c. Realize the SM chart given using a PLA, counter and 4-1 Mux. (08 Marks) 8 a. Show how to realize the following combinational function using two 3000 series logic cells, (10 Marks) F = Xy!XaXs! Xo + Xp! Xg! XgXo! + XpXs! Ky! + XpXoX4! Xe + Xs! XEKINSX! + Ky b. Write a VHDL code using One-hot assignment for the following specifications To QO Qi Q2.Q3= 1000 ; TL=0100 ; T2=0010 ; T4=0001 QS =X1 QO+X2 QL + X3.Q2+X4.Q3; Z1=X1Q0+X3Q2 ; 22=X2Q+X4Q3: (0 Marks)Page No... Time: 1a b c. Qua b. « gta b. 4a b. 5a b. d EC64 ek fia ie ea | NEW SCHEME Sixth Semester B.E. Degree Examination, July.2007 EC/TE Digital System Design Using VHDL 3 brs.J [Max. Marks:100 Note: Answer any FIVE full questions, . Write down the VHDL-code to model the following : i) D-flip flop if) IK flip flop iii) 4:1 multiplexer (09 Marks) Starting from a single bit full adder as a component, write down the structural VHDL. description for a4 bit adder. (06 Marks) With the help of a block diagram, explain the stages of compilation, elaboration and simulation, (05 Marks) Develop the VHDL code for 8 bit counting using IC 74163 binary synchronous counters. Show the hardware diagram, (06 Marks) Explain with a set of statements, the sequential execution using process and if else statements. Assume suitable delays wherever necessary. (06 Marks) Implement a Mealy sequential network with ROM and D-flip flops for BCD to excess 3 code convertor, Draw the ROM truth table and ROM realization code. (08 Marks) Using CMOS-PLD 22CE V10, design a VHDL code for a sequential traffic light controller. Supply the necessary state graph and state table (10 Marks) For a keypad scanner (4 rows x 3 columns), develop a VHDL code incorporating key bouncing. Supply the stategrapa for scanner and truth table for decoder. (10 Marks) Draw the state graph for binary multiplier control and hence develop a behavioral VHDL model for binary multiplier. (10 Marks) Draw the block diagram for a signed divider (32 bits by 16 bits) with the associated control circuits. Supply the steps of procedure to camry out the division. Draw the state graph for control circuit (10 Maris) Describe the design of a serial adder with accumulator supplying the block diagram control state graph and state table. — (10 Marks) Derive an SM chart for the control of unsigned binary multiplier (4 bits x 4 bits), is SM chart into VHDL code, (10 Marks) Contd.... 2Page No... 7 a, b. 8 oa 2 EC64 . For the dice game based on the following rules, draw the SM chart and develop the behavioral VHDL code. i) After the first roll of the dice the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3 or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point and he or she must roll the dice again, ii) On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he or she loses if the sum is 7. Otherwise, the player must roll again until he or she finally wins or loses. (10 Marks) With Xilinx XC 3020, implement a parallel adder-subtractor with an accumulator. Show a typical logic design eell with inputs and outputs, and signal paths shown after programming. (10 Marks) . Assuming that configuration data is available in EPROM, outline the steps of procedure to design any digital system using FPGA. Give one example of design. (10 Marks) Explain IEFE-1164 standard logie system for use with VHDL taking one VHDL code example. (10 Marks) Develop a VHDL code for a RAM system with data register, memory control and MAR, giving block diagram and the corresponding SM obart (10 Marks) Write the separate SM charts for simplified 486 bus interface with CPU and for UART receiver. (10 Marks) Anan= (LOOT re Sixth Semester B.E. Degree Examination, Dec. 07 / Jan. 08 Digital System Design Using VHDL Time: 3 hrs Max. Marks:100 Note : Answer any FIVE full questions. 1a. Explain the following with declaration format and an example eae! i) Variable ii) Signal iti) Constant (06 Marks) b. Using a process statement write a VHDL source code for 410 1 multiplexes. (06 Mar) Bring out differences between a VHDL function and a VHDIL procedure with & suitable example, (08 Marks) 2a, The data stored in the ROM location are (9, A, 0,0, 1,0, 0,4, F, CCD, 7,4 67). Write a VHDL code for the ROM realization by using the binary values of the mumbers given above. (06 Maris) >. Find a minimum row PLA table to implement the following set of functions F(A.B,C,D) = EmB,4,6,9,1) f(A B,C, D) = Zm2,4,8101112) f,(4,B,C,D) = EmB6,710511) (09 Marks) ¢, A keypad has 4 rows and 3 columns as shown in figure Q2 (c) fy273) (4[5{6] 7(8{9 *fol# Fig. 2 ©) ‘Assume no more than two keys will be pressed at a time. Write the block diagram of keypad scanner and first 10 rows of the truth table for a keypad decoder. If 2 keys are pressed in the same column, the N output should indicate the key in the first of the 2 rows. (0S Maris) 3 a, With a neat block diagram and the function tables, explain the operation of a serial adder with accumulator. (06 Marks) b. The state graph for faster multiplex (4 x 4) is as shown in figare Q3 (6). Write @ behavioral model (VHDL source code) for 2's complement 4 * 4 binary multiplier. ‘cr Mark) ' sth ‘ Ge St] ood fom AY? 1 1A] cq Aah fads wich ' [ch fy wolndeh | Bash Ish mish Fig. 03 (6) 1of2EC6. c. Design a binary divider and draw the block diagram of the same. Show the procedure t divide 135 by 13 [convert it into binary and perform the operations). (07 Marte a. Derive the state machine (SM) chart for dice game and obtain the state graph for dice gam controller. (10 Marks b. Write a VHDL description of the state machine band on SM chart. (10 Marks Output 21 29 Tanne i orf 16] | So 00] 10 | 17 fo Sie S3 10} 10/11 fii Sy Si 00/10} ii | or $3 So 00 | 60 | OF OF a. Explain in brief with necessary SM charts, the linked state machines, (06 Marks b. Discuss the programmable interconnects between the CLB (Configurable Logic Blocks and /O blocks with respect to i) General purpose interconnects. ii) Direct interconnects, (08 Marks c. With a neat diagram explain the CLB as a Read / Write memory cell of Xilinx 4000 serie: FPGA. (06 Marks a, Design a floating point multiplier, explicitly showing the exponent adder, fractiot multiplier and control network. (10 Marks b. Explain operator over loading and write a source code for VHDL package with overloade: operation for bit-vectors. (06 Marks ¢. Write a VHDL code for the following tristate buffers with active — high output enabl (figure Q6 (¢)). (04 Marks’ b o a ¢ on Fig. Q6 (c) a. Write a VHDL source code to 4 bit adder using generate statement. (04 Maris) b, With a neat block diagram and truth table explain the 6116 static RAM. (07 Maris) c. Explain the simplified 486 bus model with a microprocessor bus interface and timing diagram of intel 486 basic 2 ~ 2 bus cycle. (09 Marks) Write short notes on: a. Compilation / Simulation. b. VHDL operators. c. Synthesis. d. Programmable Array Logic (PALS). (20 Marks) shaae 2of2USN on ne Sixth Semester B.E. Degree Examination, June/July 08 Digital System Design Using VHDL ‘Time: 3 brs. Max. Marks:100 Note : Answer any FIVE full questions. Declaring all the inputs of a 4 x 1 MUX as vectors write VHDL codes with same entity but different architecture using the following constructs of the language : i) with—select fi) if—then—else iii) when—else iv) case~clause (10 Marks) Model a priority encoder with inputs Ws, Wz, W) and Wo. Input Ws has the highest priority while Wo has the lowest priority. Encoder output is a two-bit code (Yi Yo). There is an extra output Z, which is set to zero when all inputs are equal to zero, Use standard logic type of VHDL objects in your code. (06 Marks) Bring out the differences between VHDL functions and procedures. (od Marks) Write a VHDL procedure Addrec, which will add two N-bit vectors and a carry and returns an N-bit sum and a carry. The procedure call is of the form ‘Addrec (A, B, Cin, Sum, Cout, N); (06 Marks) Write a VHDL program to detect the number of ones in an 8-bit vector. The output of the detector must be ‘0° for even number of ones, while ‘1? for odd number of ones. (06 Marks) Model behaviourally the following 2-digit BCD counter : tener v8 SITY Bop. Bepa. Fig.2(¢) (08 Marks) ‘An N-bit bi-directional shift register has N parallel deta inputs, N outputs, a Left Serial Input (LSI), a Right Serial Input (RSI) a clock input and the following control signals = Load : load the parallel data into the register (load overrides shift) Rh : Shift the register right (LSI goes into the left end) Lesh : Shift the register left (RSI goes into the right end) IF the register is implemented using PAL 22V10, what is the maximum value of N? (10 Marks) ‘A mealy sequential network with four output variables is realized using a 22V10. What is the maximum number of input variables it can have? The maximum number of states? Can any mealy network with these number of inputs and outputs be realized with a 22V10? Explain, (10 Marks) With the state graph of binary multiplier control, write the behavioral model for 4 x 4 binary multiplier (10 Marks) Write a VHDL module that describes one bit of a full adder with accumulator. The module should have two control inputs, Ag and L. If Ag= 1, the Y input (and carry input) are added to the accumulator. If L= 1, the Y input is loaded into the accumulator. Using this module write a VHDL description of a 4-bit subtractor with accumulator. Assume negative humbers are represented in 1’s complement. ‘The subtractor should have control signal inputs S, (subtract) and L¢ (load). (10 Marks) 1of2EC64 Construct an SM chart equivalent to following state table. Test only one variable in each decision box. Try to minimize the number of decision boxes. Present state ‘Next state Outputs ZZ Mix. =00] oF | 10 TT [X=] 00] o1 | wo] a So SIS [Si | 8 oo [10 [i [or Si Sof Si |S {Ss | [ao | io Fir iL & Ss] % |S |S 00 | 10 [| or Ss —_&] Ss |S | & oo [00 [or | or G0 Maris) Write a VHDL description of the state machine based on the SM chart of Q.No.5(a). (10 Marks) With the block diagram, explain the Configurable Logic Block (CLB) of Xilinx 3000 series logic cell in FPGA. (10 Marks) Explain the architecture of Altera 7000 series CPLD. (10 Marks) With sample waveforms explain transport and inertial delays in VHDL. (08 Marks) Explain the use of generics in VHDL. (06 Marks) Write the VHIDL code for the synthesis of a case statement. (05 Marks) Write a simple VHDL model for the memory that does not take timing considerations into account, (10 Marks) Write an SM chart for simplified 486 bus interface, (10 Marks) 20f2USN Time: 3 hrs, A002 ScmEanE CET TET] ae Sixth Semester B.E. Degree Examination, Dec.09-Jan.10 Digital Systems Design using VHDL Max. Marks:100 Note: 1. Answer any FIVE full questions. 2. Standard notations are used. Write VHDL code for a full subtracter using logic equations and using this module as a component, develop VHDL code for a 4-bit subtracter, (0 Marks) Develop a VHDL model for a simple heater thermostat using PROCESS, The model has two integer inputs, one that specifies the desired temperature and another that is connected to a thermometer, and one boolean output that turns a heater ON and OFF. The thermostat turns the heater ON if the measured temperature falls below two degrees less than the desired fomperature, and tums the heater OFF if the measured temperature rises above two degrees greater than the desired temperature. (0S Marks) With suitable examples, compare variables and signals in VHDL. (05 Marks) A Moore sequential machine with two inputs (x1 and x3) and one output (2) has the following state table | [x % Zz o fin i 2 I 0 | 2 2 L L Write VHDL code that describes the machine at the behavioral level. Assume that the state changes occur 10 ns after the rising edge of the clock and output changes occur {0 ns after the state changes. (08 Marks) Write a procedure for adding two N-bit vectors and a camry, and returns N-bit sum and catry. The procedure call should be of the form addvec(A,B,C in, Sum, Cont, N) (05 Marks) Write a behavioral level VHDL model for the 4-bit bidirectional shift register 74194. The description of 74194 is as follows : The CLRb input is asynchronous and active low and overrides all the other control inputs All other state changes occur following the rising edge of the clock. If the control inputs Si*SoI, the register is loaded in parallel. If Sj=1 and Sp=0, the register is shifted right and SDR (serial data right) is shifted into Qs. If Sy=0 and Sol, the register is shifted left and SDL (serial data right) is shifted into Qu. If S-Sy=0, no action oceurs. (07 Marks) PS [xe [x I an to ado lo The following state table is implemented using a ROM and two D flip flops (falling edge): Ge @ - x=0 x=I/|x=0 x=] or 10 0 1 1 oo 1 1 1 Oo O11 0 Draw the block diagram. Write VHDL code that describes the system. Assume. that the ROM has a delay of 10 ns, and each flip flop has a propogation delay of 15 ns. (08 Marks) Find a minimum row PLA table to implement the following set of functions : £,(A,B,C,D) =D m(4,5,10,1112) ; £,(A,B,C,D) = Dm(0,1,3,4,8,1) £,(A,B,C,D) = Xm(0,4,10,12,14) And draw the figure showing thé PLA realization of ‘equations fi, f) and fy. (07 Marks) lof2 0 a e@ 0 ool 0EC64 ‘With a neat block diagram, describe the operation of a parallel adder with accumulator. Discuss with related equations, how many bits of the parallel adder and accumulator can be fit into a PAL 22v10? (05 Marks) Draw the block diagram, state graph and write VHDL behavioral model for 4 x 4 binary multiplier. (08 Marks) . Draw the block diagram and state graph for signed divider. Write VHDL model of signed divider for 32-bit divider and 16-bit divider. (12 Marks) ‘The block diagram for multiplier control and state graph for add-shift control are shown in Fig.Q5(al) and Fig.Q5(a2) respectively, The counter counts the number of shifts and outputs KE=1 just before the last shift occurs. The add-shift control generates the required sequence of add and shift signals. Derive the state machine chart and write VHDL code for contro! of the binary multiplier. Dene. Fig.Q5(al) Fig.Q5(a2) (10 Marks) Derive the SM chart for the dice game and write VHDL behavioral model for the dice game using its SM chart. (10 Marks) Implement a 2-bit binary counter using one Xilinx series logic cell. Q is the least significant bit, and Q, is the most significant bit of the counter. The counter has an a synchronous reset (AR) and a synchronous load (Ld). The counter operates as follows : En=0 No change En=1,Ld=1 Load Qx and Q, with external inputs u and v on rising edge of clock. En=1,Ld=0 Increment counter on rising edge of clock. i) Give the next state equations for Qx and Qy. ii) Label the inputs on the FG mode diagram and show the connection path. (08 Marks) With a simplified block diagram, describe the Xilinx 4000 series CLB. Also, draw the diagram to show how a CLB can be configured as a 16 x 2-bit RAM. (12 Marks) With a neat block diagram, explain the operation of floating point multiplier which consists of an exponent adder and a fraction multiplier. (08 Maris) Differentiate inertial delay and transport delay, with an example. (04 Marks) Using GENERIC statement write VADL code for a three input nandgate. Consider Tis Tha and load in your model. Also, write a VHDL structural model that contains two instances of your nandgate, where in the first instance works with Tyse= 2 ns, Tian = 1 ns and load = 2, second instance uses default values specified. (08 Marks) Draw the block diagram and write VHDL code for static RAM model with truth table Q8(a). cs | OE | WE “Mode vO pins | [A [x |X [Notseiected high-Z | L | A | He | Outpurdisabted | high-Z L | L |] H {Read data out L x L_| Write data in Table Q8(@) (10 Marks) What is operator overloading? Write VHDL package with overtoaded operators for bit- vectors. sail (10 Marks) 2of2.