Pedagogical and Technological University of Colombia

Electronics Engineering School

Digital Electronics 1 Course
Laboratory Exercises
Laboratory Exercise 7
Numbering Systems

Introduction
Although most processors compute data in binary form, the input-output is generally done in some coded form.
Normally, we exchange information in decimal. Hence decimal numbers must be coded in terms of binary
representations. In the simplest form of binary code, each decimal digit is replaced by its binary equivalent. This
representation is called Binary Coded Decimal (BCD) or 8-4-2-1 (to indicate weight of each bit position). Because
there are only ten decimal digits, 1010 through 1111 are not valid BCD. Table below shows some of the widely used
binary codes for decimal digits. These codes are designed and used for communication reliability and error
detection.

TABLE I
MAIN BINARY CODES FOR DECIMAL DIGITS

Decimal Digits BCD (8-4-2-1) 6-3-1-1 Excess-3 2-out-of-5 Gray Code

0 0000 000 0011 00011 0000
1 0001 0001 0100 00101 0001
2 0010 0011 0101 00110 0011
3 0011 0100 0110 01001 0010
4 0100 0101 0111 01010 0110
5 0101 0111 1000 01100 1110
6 0110 1000 1001 10001 1010
7 0111 1001 1010 10010 1011
8 1000 1011 1011 10100 1001
9 1001 1100 1100 11000 1000

The BCD and 6-3-1-1 codes are weighted codes of 4 binary digits (bits) because each bit is assigned a weight. In the
case of BCD the weights are 8, 4, 2 and 1. For the code 6-3-1-1, as the name implies, the weights are 6, 3, 1 and 1.
Thus, given the binary code 0111 it is possible to know that it represents 7 in BCD (0 × 8 + 1 × 4 + 1 × 2 + 1 × 1 =
7), and 5 in code 6-3-1-1 (0 × 6 + 1 × 3 + 1 × 1 + 1 × 1 = 5).

The excess code 3 is obtained from BCD by adding 3 to each code. The code 2 of 5 has the property that in each
code only 2 of the 5 bits are 1. On the other hand, in the Gray code each consecutive code differs in a single bit.
These last two codes are unweighted. That is, the decimal value of a digit encoded in code 2 of 5 or in Gray code
cannot be obtained from a formula as in the case of weighted codes.

Part I
Model a binary code "2-out-of-5" and display the 4-bit binary decimal input number set by the SW3-0 switches on
five LEDs. Also display on the 7-segment display HEX0 the value of the switches. Use data flow modeling.

1. Create a new Quartus II project for your circuit.

2. Write a VHDL file that provides the necessary functionality. Include this file in your project and assign the
pins on the FPGA to connect to the switches, LEDs and 7-segment display.
3. Compile the project and download the compiled circuit into the FPGA chip.
4. Test the functionality of your design by toggling the switches and observing the LEDs and the display.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Part II
Design a circuit that converts a 4-bit binary number v into its 2-digit decimal equivalent z and m. Fig. 1b shows the
required output values. Fig. 1a shows a block diagram of the design, it includes a comparator that checks when the
value of v is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. Hint:
The m3 would be zero whenever v is greater than binary 1001.

d1
z
Comparator 0

5 1
7 6
Circuit B
m3 4 2 v[3:0] z m[3:0]
v3 0
0 1 3
0000 0 0000
0001 0 0001
0010 0 0010
d0 0011 0 0011
v2 0 m2 0 0100 0 0100
1
5 1
0101 0 0101
7-segment 7 6 0110 0 0110
decoder 0111 0 0111
4 2
1000 0 1000
v1 0 m1
3 1001 0 1001
1
1010 1 0000
1011 1 0001
1100 1 0010
v0 0 m0 1101 1 0011
1 1110 1 0100
1111 1 0101

Circuit A

(a) (b)
Fig. 1 a) Design of binary-to-decimal conversion circuit; b) Output values of the conversion

The intent of this exercise is to use simple VHDL assignment statements to specify the required logic functions
using Boolean expressions. Your VHDL code should not include any IF-ELSE, CASE, or similar statements.
Perform the following steps:

1. Make a Quartus II project for your VHDL entity

2. Create and add the VHDL module with v[3:0] input, and z and m[3:0] output, include the comparator, the
circuit A and the 2-to-1 multiplexers, connect them as necessary.
3. Compile the circuit and use functional simulation to verify the correct operation of your comparator,
multiplexers, and circuit A watching the outputs z and m[3:0].
4. Extend the design to have the BCD to 7-segment decoder and the circuit B, use switches SW3−0 on the DE1
board to represent the binary number v, and the displays HEX1 and HEX0 to show the values of decimal
digits d1 and d0. Make sure to include in your project the required pin assignments for the DE1 board.
5. Recompile the project, and then download the circuit into the FPGA chip.
6. Test your circuit by trying all possible values of v and observing the output displays.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Part III
When two one-bit numbers are added, they may produce two bits output. For example, 1 + 1 = 10 (all in binary).
When you add three one- bit numbers the result will still be two bits, e.g. 1 + 1 + 1 = 11. This simple operation can
be viewed as adding two bits with carry in from the lower significant operation, resulting into sum and carry out.
The Fig. 2b and Fig. 2c show a circuit symbol and truth table for the full adder, which produces the two-bit binary
sum. Fig. 2d shows how four instances of this full adder entity can be used to design a circuit that adds two four-bit
numbers. Since the carry is rippled from least significant bit position (cin) to the most significant position (cout), such
adder is called ripple carry adder.

b a ci co s
ci
0 0 0 0 0
a s 0 0 1 0 1
ci
b s 0 1 0 0 1
a FA 0 1 1 1 0
co 1 0 0 0 1
0 b
co 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1
(a) (b) (c)

b3 a3 c3 b2 a2 c2 b1 a1 c1 b0 a0 cin

FA FA FA FA

cout s3 s2 s1 s0
(d)
Fig. 2 a) Full adder circuit; b) Full adder symbol; c) Truth table of full adder; d) Ripple carry adder circuit

Write VHDL code that implements a 4-bit adder. Perform the following steps:

1. Create a new Quartus II project for the adder circuit. Write a VHDL entity for the full adder sub circuit and
write a top-level VHDL entity that instantiates four instances of this full adder.
2. Use switches SW7−4 and SW3−0 to represent the inputs a and b, respectively. Use SW8 for the carry-in (cin) of
the adder. Connect the SW8-0 switches to their corresponding red lights LEDR8-0, and connect the outputs of
the adder, cout and s, to the green lights LEDG4-0.
3. Include the necessary pin assignments for the DE1 board, compile the circuit, and download it into the
FPGA chip.
4. Test your circuit by trying different values for numbers a, b, and cin.
 Pedagogical and Technological University of Colombia
Electronics Engineering School
Digital Electronics 1 Course
Laboratory Exercises
Part IV
Design a circuit that adds two BCD digits A and B with a drag, generating the result in two-digit BCD S1 and S0.
Reuse the models developed in parts II and III as necessary. Use data flow modeling. Note that the largest sum that
this circuit must handle is 9 + 9 + 1 = 19.

Perform the following steps:

1. Create a new Quartus II project for your BCD adder.

2. Modify the circuit of parts II and III as necessary to produce the sum of two digits BCD A and B generating
the result S1 and S0.
3. Use switches SW7-0 to enter two 4-bit BCD inputs and SW8 for the drag bit, also connect the inputs SW8-0 to
the red LEDs LEDR8-0 correspondent and the four-bit sum with their carryout produced by the operation A
+ B to the green LEDs LEDG4-0. Display the BCD values of A and B on the 7-segment displays HEX3 and
HEX2, and display the result S1 and S0 on HEX1 and HEX0.
4. Check for the cases when the input A or B is greater than nine, indicate an error by turning on the green
LED LEDG8.
5. Include the necessary pin assignments for the DE1 board, compile the circuit, and download it into the
FPGA chip.
6. Test your circuit by trying different values for numbers A, B, and Cin.

Part V
Design a circuit that can add two 2-digit BCD numbers, A1 A0 and B1 B0 to produce the three-digit BCD sum S2 S1
S0. Use two instances of your circuit from part IV to build this two-digit BCD adder. Perform the following steps:

1. Use switches into the GPIO connector extension to represent 2-digit BCD numbers A1 A0 and B1 B0,
respectively. Display the BCD sum S2 S1 S0 on the 7-segment displays HEX2, HEX1 and HEX0.
2. Make the necessary pin assignments and compile the circuit.
3. Download the circuit into the FPGA chip, and test its operation.

Part VI
Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the
BCD form. Use switches SW5−0 to input the binary number and 7-segment displays HEX1 and HEX0 to display the
decimal number. Implement your circuit on the DE1 board and demonstrate its functionality.