SRM VALLIAMMAI ENGINEERING COLLEGE

(An Autonomous Institution)

SRM Nagar, Kattankulathur – 603 203

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK

VI SEMESTER

EC 8095 – VLSI Design

Regulation – 2017

Academic Year 2019 – 20

Prepared by

Mr.A.Anbarasan, Assistant Professor/ECE

Mr.A.Pandian, Assistant Professor/ECE
Mr. S.Senthil Murugan, Assistant Professor/ECE
 SRM VALLIAMMAI ENGINEERING COLLEGE
(An Autonomous Institution)
SRM Nagar, Kattankulathur – 603 203.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

QUESTION BANK
SUBJECT : EC8095 VLSI Design
SEM / YEAR: VI / III

UNIT I - INTRODUCTION TO MOS TRANSISTOR

MOS Transistor, CMOS logic, Inverter, Pass Transistor, Transmission gate, Layout Design
Rules, Gate Layouts, Stick Diagrams, Long-Channel I-V Charters tics, C-V Charters tics, Non
ideal I-V Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay
Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.
PART - A
Q. No Questions BTL Competence
1. Write the functions of gate terminal. BTL 1 Remembering
2. Compare nMOS and pMOS transistor. BTL 4 Analyzing
3. What is gate-to-body capacitance? BTL 1 Remembering
4. Summarize the flow of current between the source and drain. BTL 2 Understanding
Draw the 3-input NOR gate using CMOS Logic with truth BTL 3 Applying
5.
table.
6. Evaluate the structure of MOS. BTL 5 Evaluating
7. Illustrate the transmission gate or pass gate with neat sketch. BTL 3 Applying
Point out the set of design rules for layouts with two metal BTL 4 Analyzing
8.
layers.
What is stick diagram? Sketch the stick diagram for 3 input BTL 3 Applying
9.
NAND gate.
Name the different operating modes of transistor and its BTL 1 Remembering
10.
current?
Explain the equation for describing the channel length BTL 2 Understanding
11.
modulation effect in nMOS transistor.
12. Mention the Non ideal I-V effects of MOS transistor. BTL 1 Remembering
Discuss the relationships between voltages for the three BTL 2 Understanding
13.
regions of operation of a CMOS inverter.
14. Why pMOS transistors are wider than nMOS transistors. BTL 1 Remembering
Design a RC ladder for Elmore delay with its propagation BTL 6 Creating
15. delay time, tpd.
Define body effect and write the threshold equation including BTL 1 Remembering
16.
the body effect.
17. Describe the Logical effort of a gate. BTL 2 Understanding
18. Analyze Parasitic delay of a gate. BTL 4 Analyzing
19. Compare constant field scaling and constant voltage scaling. BTL 5 Evaluating
Formulate the various critical parameters of Transistor BTL 6 Creating
20.
scaling.
PART – B
Explain the structure and working of nMOS and pMOS BTL 4 Analyzing
1.
transistor. (13)
Summarize the following using CMOS logic:
2. (i) Inverter with truth table, (6) BTL 2 Understanding
(ii) NAND Gate with truth table. (7)
Illustrate with necessary diagrams
3. BTL 3 Applying
(i) Ideal I-V characteristics of MOS transistors, (6)
(ii) C-V characteristics of MOS transistors. (7)
Analyze the characteristics and working of the following with
neat diagram, BTL 4 Analyzing
4.
(i) Pass transistors, (6)
(ii) Transmission gate. (7)
(i) Describe in detail about Layout design rules. (7)
5. (ii) Draw the stick diagram and layout diagram for the CMOS BTL 1 Remembering
gate computing. Y  ( A  B  C )  D . (6)
Discuss in detail about the velocity saturation and channel
6. length modulation. (13) BTL 2 Understanding

Write short notes on:

(i) Body Effect, (4) BTL 1 Remembering
7.
(ii) Subthreshold Condition, (4)
(iii) Junction Leakage. (5)
Interpret the DC transfer characteristics of CMOS inverter. BTL 3 Applying
8.
(13)
Describe the following with necessary equations.
9. (i) Detailed MOS gate capacitance model, (7) BTL 2 Understanding
(ii) Detailed MOS diffusion capacitance model. (6)
Demonstrate the RC Delay model and Elmore delay model. BTL 3 Applying
10.
(13)
(i) State logical effort and draw the logic gates for different
transistor widths. (6) BTL 1 Remembering
11.
(ii) Define parasitic delay and compare the parasitic delay of
common gates for various inputs. (7)
Write short notes on:
12. (i) Transistor scaling, (7) BTL 1 Remembering
(ii) Interconnect scaling. (6)
Design a CMOS inverter and formulate the beta ratio effects BTL 6 Creating
13.
and noise margin. (13)
Evaluate Multistage Logic Networks with delay and formulate BTL 5 Evaluating
14.
the expression with an example. (13)
PART – C
 1. Explain the Non ideal I-V effects of MOS transistors. (15) BTL 5 Evaluating
Evaluate the DC transfer characteristics of CMOS inverter.
2. BTL 5 Evaluating
(15)
Design a CMOS compound gate computing and sketch a stick
3. diagram. F  ( A  B)  (C  D) and write the layout procedure. BTL 6 Creating
(15)
Generalize the following delay models:
(i) RC delay model, (5) BTL 6 Creating
4. (ii) Linear delay model, (5)
(iii) Parasitic delay. (5)

UNIT II – COMBINATIONAL LOGIC CIRCUITS

Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic
Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail Domino, CPL,
DCVSPG, DPL, Circuit Pitfalls.
Power: Dynamic Power, Static Power, Low Power Architecture.
PART – A
Q. No Questions BTL Competence
1. Write about static CMOS circuits. BTL 1 Remembering
2. What is meant by bubble pushing? BTL 1 Remembering
Generalize the skewed gates and calculate the logical effort BTL 3 Applying
3.
for HI-skew inverter.
4. Summarize the Multiple threshold voltages for CMOS. BTL 2 Understanding
5. Analyse the pseudo-nMOS logic gates. BTL 4 Analyzing
6. Construct the symmetric 2-input NOR gate with its truth table. BTL 6 Creating
7. Illustrate the Source follower Pull-up logic. BTL 4 Analyzing
Describe the precharge and evaluation modes of dynamic
8. BTL 1 Remembering
gates with its timing diagram.
9. Draw the footed and unfooted Inverter, NAND2 and NOR2. BTL 1 Remembering
Compare the static CMOS, Pseudo-nMOS and dynamic
10. BTL 4 Analyzing
inverters.
11. Evaluate the Multiple Output Domino Logic (MODL). BTL 5 Evaluating
Design a circuit to compute F=AB+CD using NANDs and BTL 6 Creating
12.
NORs.
13. Define Keeper circuit. BTL 1 Remembering
14. Discuss the Dual-rail Domino Logic. BTL 2 Understanding
15. Show that CMOS gates are very power-efficient. BTL 3 Applying
16. Estimate the power dissipation in CMOS circuits. BTL 2 Understanding
17. Explain static dissipation in CMOS inverter. BTL 2 Understanding
18. Mention the methods used for dynamic power reduction. BTL 1 Remembering
19. Interpret the average dynamic power dissipation. BTL 3 Applying
20. Justify that CPL is an improvement of CVSL. BTL 5 Evaluating
 PART – B
Analyse the following static CMOS logic.
(i) Bubble pushing, (4)
1. BTL 4 Analyzing
(ii) Compound gates, (4)
(iii) Skewed gates. (5)
Illustrate the following circuits in detail.
2. (i) Pseudo-nMOS, (8) BTL 2 Understanding
(ii) Ganged CMOS. (5)
(i) Explain in detail about Cascode voltage switch logic. (8)
3. BTL 4 Analyzing
(ii) Infer the modes of operation in dynamic circuits. (5)
Write short notes on
4. (i) Domino logic, (7) BTL 1 Remembering
(ii) Dual-rail Domino Logic. (6)
Draw the 2-input multiplexers using the following circuit
techniques.
(i) static CMOS, (3)
5. BTL 1 Remembering
(ii) Pseudo-nMOS, (3)
(iii) CVSL, (3)
(iv) Dual-rail Domino. (4)
Summarize the following.
6. (i) Pass transistor logic, (7) BTL 2 Understanding
(ii) Complementary pass transistor logic. (6)
Evaluate the design of Differential Cascode Voltage Switch
7. BTL 5 Evaluating
with Pass Gate (DCVSPG). (13)
Describe in detail about the following.
(i) Keepers, (5)
8. BTL 1 Remembering
(ii) Multiple-Output Domino Logic (MODL), (4)
(iii) NP and Zipper Domino. (4)
Illustrate the Cascode Voltage Switch Logic with neat
9. BTL 3 Applying
diagram. (13)
Classify the types of power dissipation and manipulate each in
10. BTL 3 Applying
detail. (13)
(i) Define Multiple Threshold voltages. (3) BTL 1 Remembering
11.
(ii) Examine the P/N Ratios for logic gates. (10)
Manipulate the various Ratioed circuits for CMOS circuits.
12. BTL 3 Applying
(13)
Discuss the structure and working of CMOS with
13. BTL 2 Understanding
transmission gates. (13)
14. Construct the various low-power reduction techniques. (13) BTL 6 Creating
PART – C
Summarize the following.
(i) Input ordering delay effect, (5)
1. BTL 5 Evaluating
(ii) Asymmetric gates, (5)
(iii) P/N ratios. (5)
 Evaluate the following Dynamic circuits.
(i) Domino logic, (5)
2. BTL 5 Evaluating
(ii) Dual-rail Domino logic, (5)
(iii) Keepers. (5)
Design the Ratioed circuits and its types with neat diagram. BTL 6 Creating
3.
(15)
Formulate the following power dissipation in CMOS circuits.
4. (i) Static dissipation, (7) BTL 6 Creating
(ii) Dynamic dissipation. (8)

UNIT III - SEQUENTIAL CIRCUIT DESIGN

Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier
Based Register, Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential
Circuits.
Timing Issues: Timing Classification Of Digital System, Synchronous Design.
PART - A
Q. No Questions BTL Competence
1. Define bistability principle. BTL 1 Remembering
2. Name the approaches used to accomplish the bistable circuit. BTL 1 Remembering
3. Show the mode of operation of low voltage static latches. BTL 3 Applying
4. Summarize the timing properties of Master-slave registers. BTL 2 Understanding
Analyse the working of dynamic positive edge-triggered
5. BTL 4 Analyzing
register when clk=0.
6. Draw the Multiplexer-based nMOS latch. BTL 1 Remembering
7. Describe the operation of C2MOS register. BTL 2 Understanding
8. Evaluate the True Single-Phase Clocked Register (TSPCR). BTL 5 Evaluating
What is the role of transistor sizing in TSPC Edge-Triggered
9. BTL 1 Remembering
Register?
10. Mention the advantages of pipelined operation. BTL 1 Remembering
11. Discuss the sense-amplifier based registers. BTL 2 Understanding
Sketch the circuit of latch-based pipeline using C2MOS
12. BTL 4 Analyzing
latches.
13. Explain the operation modes for NORA logic style. BTL 4 Analyzing
14. List out the timing parameters of the sequential circuit in
BTL 1 Remembering
synchronous design.
15. Deduce the properties of Schmitt trigger. BTL 5 Evaluating
16. Design a voltage-controlled oscillator based on current- BTL 6 Creating
starved inverters.
17. Examine the uses of Schmitt trigger. BTL 3 Applying
18. Estimate the use of address transition detection (ATD) circuit. BTL 2 Understanding
14. Develop the positive and negative clock skew scenarios. BTL 6 Creating
20. Classify the transition of signals at predetermined periods. BTL 3 Applying
PART-B
State and explain the Bistability principle and its two different
1. BTL 1 Remembering
approaches. (13)
 Discuss in detail:
(i) Master-Slave Edge-Triggered Register, (7)
2. BTL 2 Understanding
(ii) Timing properties of Multiplexer-Based Master-Slave
registers. (6)
Write short notes on:
3. (i) Multiplexer-Based Latches, (7) BTL 1 Remembering
(ii) Low-Voltage Static Latches. (6)
2 Analyzing
4. Explain the C MOS Register with CLK- CLK clocking BTL 4
approach. (13)
Evaluate the True Single-Phase Clocked Register (TSPCR)
5. BTL 5 Evaluating
and TSPC Edge-Triggered register. (13)
Illustrative the following Alternative Register styles.
6. (i) Pulse Registers, (7) BTL 3 Applying
(ii) Sense-Amplifier-Based Registers. (6)
Classify the various Pipeling techniques and explain in detail.
7. BTL 3 Applying
(13)
Summarize the following.
8. (i) Latch versus Register based pipeline, (6) BTL 2 Understanding
(ii) NORA-CMOS logic style for pipelined structures. (7)
(i) Define Schmitt trigger and its properties. (4)
9. (ii) Describe Schmitt trigger and its CMOS implementation BTL 1 Remembering
with neat diagram. (9)
Construct the clock-distribution techniques dealing with clock
10. BTL 6 Creating
skew and jitter. (13)
Describe in detail:
(i) Synchronous interconnect, (3)
11. (ii) Mesochronous interconnect, (3) BTL 1 Remembering
(iii) Plesiochronous interconnect, (3)
(iv) Asynchronous interconnect. (4)
Examine the Monostable Sequential circuits and Astable
12. BTL 2 Understanding
circuits with neat an example. (13)
Analyze the basics of synchronous timing, clock skew, clock BTL 4
13. Analyzing
jitter and combined impact of skew and jitter. (13)
14. Manipulate the various sources of skew and jitter. (13) BTL 3 Applying
PART-C
Evaluate the Master-Slave Edge-Triggered register with its
1. BTL5 Evaluating
timing properties and Non-ideal clock signals. (15)
Summarize the following:
(i) Dynamic transmission-gate edge-triggered registers, (5)
2. BTL5 Evaluating
(ii) C2MOS-A clock-skew insensitive approach, (5)
(iii) True single-phase clocked register. (5)
Formulate the following Nonbistable sequential circuits
(i)) The Schmitt Trigger, (5) BTL 6 Creating
3.
(ii) Monostable Sequential Circuits, (5)
(iii) Astable Circuits. (5)
Design the clock distribution strategies for three generations BTL 6 Creating
4.
of the digital alpha microprocessors. (15)

UNIT IV - DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power and speed
tradeoffs, Case Study: Design as a tradeoff.
Designing Memory and Array structures: Memory Architectures and Building Blocks, Memory
Core, Memory Peripheral Circuitry.
PART-A
Q. No Questions BTL Competence
Obtain the critical path delay of 4 bit ripple carry adder and
1. BTL 6 Creating
draw the circuit.
Summarize about carry propagation delay. Mention its effect
2. BTL 2 Understanding
in circuits.
3. List out the components of Data path. BTL 1 Remembering
Why is barrel Shifters very useful in the designing of
4. BTL 2 Understanding
arithmetic circuits?
Interpret a partial product selection table using modified 3-bit
5. BTL 5 Evaluating
booth’s recoding multiplication.
6. What is one time programmable memories? BTL 1 Remembering
7. Draw the structure of 6- transistor SRAM cell. BTL 3 Applying
List the advantages and disadvantages of full adder design
8. BTL 1 Remembering
using static CMOS.
Analyze the concept of Dynamic voltage scaling and list its BTL 4
9. Analyzing
advantages.
10. Define Clock gating. BTL 1 Remembering
Create a schematic for Sleep transistors used on both supply
11. BTL 6 Creating
and ground.
12. Examine the need of VTCMOS. BTL 4 Analyzing
13. Give the applications of CAM. BTL 2 Understanding
14. Explain the inverting property of full adder. BTL 4 Analyzing
How to design a column multiplexer with separate decoder
15. BTL 3 Applying
circuit?
Write the full adders output in terms of propagate and
16. BTL 1 Remembering
generate.
Classify Power optimization techniques for latency and BTL 3
17. Applying
throughput constrained design.
18. Write the charge-share equation for DRAM. BTL1 Remembering
19. Sketch a sense amplifiers CMOS circuit. BTL2 Understanding
20. Elaborate the Concept of large SRAMs. BTL 5 Evaluating
PART-B
(i) Describe ripple carry adder and derive the expression for
1. worst case delay. (10) BTL 1 Remembering
(ii) Write a note on Carry Bypass adders. (3)
Examine the concept of carry look ahead adder and discuss its BTL 4
2. Analyzing
types. (13)
Outline the operation of a basic 4 bit adder. Describe the
3. BTL 1 Remembering
different approaches of improving the speed of the adder. (13)
Illustrate the concepts of faster decoder and sum-addressed BTL 3
4. Applying
decoder circuit. (13)
Define SRAM memory cell operation and summarize short
5. note on BTL 1 Remembering
(i) Read operation, (7)
 (ii) Write operation. (6)
Demonstrate the bitline conditioning circuitry with necessary
6.
circuit diagram. (13) BTL3 Applying
Design a multiplier for 5 bit by 3 bit. Explain its operation and
7. summarize the number of adders. Discuss it over Wallace
BTL 6 Creating
multiplier. (13)
Summarize the Multi-ported SRAM and Register file CMOS
8. BTL2 Understanding
logic circuit. (13)
Evaluate the architecture of large memory array with subarray
9. BTL5 Evaluating
memory Circuitry. (13)
10. Give a note on linear carry select adder. (13) BTL 2 Understanding
Examine the operation of :
11. (i) Static CMOS adders. (7)
BTL 4 Analyzing
(ii) Mirror adder (6)
Analyse the operation of booth multiplication with suitable
12. examples. Justify how booth algorithms speed up the BTL 4
Analyzing
multiplication process. (13)
13. Discuss the data paths in digital processor architectures. (13) BTL 2 Understanding
14. Write detailed note about any two multiplier circuit. (13) BTL 1 Remembering
PART-C
(i) Construct 4 X 4 array type multiplier and find its critical
path delay. (8)
1. BTL5 Evaluating
(ii) Implement a 4 input and 4 output barrel shift adder using
NMOS logic. (7)
Design a multiplier for 5 bit by 3 bit. Explain its operation and
2. summarize the number of adders. Discuss it over Wallace BTL6 Creating
multiplier. (15)
Explain a Modified Booth algorithm with a suitable example.
3. BTL5 Evaluating
(15)
Discuss detail about the DRAM sub array and open bitlines
4. BTL6 Creating
architecture. (15)

UNIT V - IMPLEMENTATION STRATEGIES AND TESTING

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design for
Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Design for Manufacturability,
Boundary Scan.
PART-A
BT Competence
Q. No Questions
Level
1. What is fault model? BTL 1 Remembering
2. Point out the common techniques of ad hoc testing. BTL 4 Analyzing
3. List out the different approaches of Design for testability. BTL 1 Remembering
4. Narrate about stuck-at faults and state their uses. BTL 3 Remembering
5. Classify the types of stuck-at faults. BTL 3 Applying
6. Give a note on short circuit and open circuit faults. BTL 2 Understanding
7. State the features of boundary scan method. BTL 1 Remembering
8. Differentiate between observability and controllability. BTL 4 Analyzing
9. Describe about ATPG design scan? BTL 1 Remembering
10. Define Fuse based FPGA. BTL 1 Remembering
11. Name the two different types of routing in FPGA. BTL 2 Understanding
12. Develop a PRSG logic circuit for BIST test. BTL 6 Creating
13. Draw the block diagram of test data register.. BTL 6 Creating
14. Compare serial and parallel scan in ad hoc testing. BTL 4 Analyzing
Summarize the functions of Programmable Interconnect
15. BTL 5 Evaluating
Points in FPGA.
16. Give an example circuit for delay fault CMOS logic circuit. BTL 2 Understanding
Determine the power supply of CMOS logic circuit using
17. BTL 5 Evaluating
IDDQ fault test.
18. Illustrate the Test Access Port connection details. BTL 3 Applying
19. Outline the steps for CMOS circuit IDDQ test. BTL 2 Understanding
20. Write the various ways of routing procedure. BTL 1 Remembering
PART-B
(i) Explain the manufacturing test principle with an example
1. of digital logic circuits. (8) BTL1 Remembering
(ii) Give a short note on stuck-at faults model. (5)
Describe the various types of ad hoc testing techniques with
2. BTL 2 Understanding
neat diagram. (13)
(i) List out the common testing technique for ad hoc test. (8)
3. (ii) Outline the need of Observability for integrated circuits.
BTL 1 Remembering
(5)
Illustrate the concepts of short circuit and open circuit fault.
4. BTL 3 Applying
(13)
5. Explain the architecture of parallel scan testing method. (13) BTL 4 Analyzing
Examine the boundary scan architectures and explain how to
6. BTL 4 Analyzing
test the circuit board level and system level. (13)
Identify and Explain the BIST block structure along its
7. BTL 1 Remembering
components. (13)
(i) Discuss the types of FPGA routing techniques. (7)
8. (ii) Demonstrate the basic types of programmable elements of BTL 2 Understanding
FPGA. (6)
Elaborate the small finite state machine of TAP architecture.
9. BTL 6 Creating
(13)
(i) Compare two types of Ad hoc scanning methods. (10) BTL 4 Analyzing
10.
(ii) Point out the Test access port signals. (3)
11. Draw and explain the building blocks of FPGA. (13) BTL 2 Understanding
12. Draw the block diagram of BILBO\BIST and explain each
BTL 3 Applying
unit operation. (13)
13. Summarize the steps involved in design for manufacturability
BTL 5 Evaluating
to increase the yield of optimized circuit. (13)
Write short notes on
14.
(i) TAP controller (6) BTL 1 Remembering
(ii) Instruction register (7)
PART-C
With neat sketch explain the CLB, IOB and programmable
1. BTL 5 Evaluating
interconnects of an FPGA device. (15)
Draw and explain the building blocks of FPGA with different
2. BTL 6 Creating
fusing technologies. (15)
 (i) Explain about building block architecture of TAP. (10)
3. (ii) Write short notes on routing procedures involved in FPGA BTL 5 Evaluating
interconnect. (5)
Discuss in detail about different types of scan design method
4. BTL 6 Creating
and explain with neat diagram. (15)