Tempus

Introduction

● Why Tempus ?
● What we can do in Tempus ?

2
Timing Analysis

● Why is timing analysis important when designing a chip ?

● What are the types of timing analysis?
○ STA
○ DTA
● Why do we normally do STA rather than DTA
● What are the Timing violations we come across ?
●

3
Design Import
● Input Requirements
○ Timing Libraries (Liberty dotlib files)
○ Verilog Netlist
○ SDC Constraints
○ Parasitic Data (SPEF)
● Design Import Flow
○ Read all the inputs
○ Link design
○ Update timing
○ Generate reports
● Performing Sanity Checks
○ check_design
○ check_timing
●
4
Types of analysis

What is Mode?

What is Corner?

What is view?

Types are:

● Single mode analysis

● MMMC (Multi mode Multi Corner)
○ C-MMMC
○ D-MMMC
●

5
run.tcl

6
7
8
Reports.tcl

9
Command: report_constraints -all_violators -early

10
Command: report_constraints -all_violators -drv_violation_type max_transition

11
Related Commands
● To display DRV violations
○ report_constraints -all_violators -drv_violation_type max_capacitance
○ report_constraints -all_violators -drv_violation_type min_transition
○ report_constraints -all_violators -drv_violation_type min_capacitance
○ report_constraints -all_violators -drv_violation_type max_fanout
○ report_constraints -all_violators -drv_violation_type min_fanout
● To display setup violations
○ report_timing -check_type setup
○ report_timing -late
○ report_constraints -all_violators -late
● To display hold violations
○ report_timing -check_type hold
○ report_timing -early
○ report_constraints -all_violators -early
● 12
Fixing Techniques
Setup : Take all violated paths and analyse the cell delays on data path.

● Upsize
● Vt swapping (HVT to LVT)
● Adding a buffer

Hold : Take all hold violated endpoints and add delay buffer with respect to negative slack if slack is
more then we add more delay buffers .

● Downsize
● Vt swapping (LVT to HVT)

Tran : If there is more load on particular net, then we need better transition to drive the net. So we
take the net driver and add one appropriate buffer on driver input side to improve transition.

Cap : If particular net having more fanout cells than the available load that impacts a cap violations
in other words charging and discharging takes more time . So we can split the load to perform a
cloning or add buffer at the driver output side. 13
Fixing of violations through ECO Opt
The only command to fix eco timing db is write_eco_opt_db. By using this design it
automatically create ecoTimingDB.

Script to fix hold violations

● set_eco_opt_mode -verbose true
● set_eco_opt_mode -load_eco_opt_db ecoTimingDB
● eco_opt_design -hold
Script to fix DRC violations
● set_eco_opt_mode -verbose true
● set_eco_opt_mode -load_eco_opt_db ecoTimingDB
● set_eco_opt_mode -along_route_buffering true
● eco_opt_design -drv

We can observe two files are created

● eco_innovus.tcl -> Given to PNR team
● eco_tempus.tcl
●
14
Fixing of DRVs manually

more balatran8_7_19 | grep "/D" | awk '{ print “add_repeater -term ”$1 “ -cell BUF_X16”}' 15
This is the file we need to source in our design for fixing of DRCs (max_tran) manually.

16
Multi-Mode Multi Corner

17
18
19
20
21
● For fixing of Timing violations, need to set view analysis mode to one view.

Commands:

tempus 1 > all_analysis_views

scan_fast_RCMIN func_slow_RCMAX scan_fast_RCMAX func_fast_RCMIN scan_slow_RCMIN
func_fast_RCMAX scan_slow_RCMAX func_slow_RCMIN
tempus 2> set_analysis_view -setup func_slow_RCMAX -hold func_slow_RCMIN
tempus 3> all_setup_analysis_views
func_slow_RCMAX
tempus 4> all_hold_analysis_views
func_slow_RCMIN
tempus 5> report_constraint -all_violators -view func_slow_RCMIN -early
tempus 6> report_timing -view func_slow_RCMIN -early

22
● The script below shows all violators based on all views

● Here all the violators are fixed through ECO optimization techniques.

23
 Initial Summary
Hold Analysis :

Views WNS TNS VP Worst End-Point

func_slow_RCMAX -2.159 -58.348 35 TDSP_CORE_INST/PROG_BUS_MACH_IN

ST/data_out_reg[10]/D

func_fast_RCMAX -1.300 -24.323 33 TDSP_CORE_INST/PROG_BUS_MACH_IN

ST/data_out_reg[10]/D

func_fast_RCMIN -1.070 -17.029 27 TDSP_CORE_INST/PROG_BUS_MACH_IN

ST/data_out_reg[2]/D

func_slow_RCMIN -1.885 -47.266 35 TDSP_CORE_INST/PROG_BUS_MACH_IN

ST/data_out_reg[2]/D

scan_slow_RCMAX -1.675 -25.134 19 TDSP_CORE_INST/DATA_BUS_MACH_INS

T/data_out_reg[3]/SI

scan_fast_RCMAX -0.632 -4.727 17 TDSP_CORE_INST/DATA_BUS_MACH_INS

T/data_out_reg[3]/SI

scan_slow_RCMIN -1.334 -17.783 19 TDSP_CORE_INST/DATA_BUS_MACH_INS

T/data_out_reg[3]/SI

scan_fast_RCMIN -0.395 -0.603 11 TDSP_CORE_INST/DATA_BUS_MACH_INS

T/data_out_reg[3]/SI
Setup Analysis :

Views WS TNS VP Worst End-Point

func_slow_RCMAX 1.031 0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

func_fast_RCMAX 4.452 .0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

func_fast_RCMIN 5.942 0.000 0 RESULTS_CONV_INST/r852_reg[11]/D

func_slow_RCMIN 3.488 0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

scan_slow_RCMAX 1.031 0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

scan_fast_RCMAX 4.452 0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

scan_slow_RCMIN 3.488 0.000 0 RESULTS_CONV_INST/r1477_reg[10]/D

scan_fast_RCMIN 5.942 0.000 0 RESULTS_CONV_INST/r852_reg[11]/D

25
 Initial Summary: Final Summary:

Setup Hold Setup Hold

Worst Slack 1.031 -2.159 Worst Slack 1.031 0.000

Total Slack 0.000 -58.348 Total Slack 0.000 0.000

Violating paths 0 35 Violating paths 0 0

This is the script for fixing hold violations automatically based on endpoints with respect to slack
27
SI Analysis
Tempus performs the following signal integrity analysis operations:

● SI Delay Analysis
● SI Glitch Analysis

SI Delay Analysis :

● SI can increase or decrease signal delay, which can, in turn cause setup or hold failures.
● Consider that attacker A1 switches in the opposite direction to the victim, as shown in the figure below, then
there can be a potential increase in the victim delay.
● SI can also decrease the delay and cause hold time failures. If both the attacker and victim are switching in the
same direction, as shown in the figure below, then there is a decrease in the victim net delay. If this occurs on a
critical minimum delay path, it can lead to hold violations.

28
SI Delay increases SI Delay decreases

29
SI enabling switches
● set_si_mode –individual_attacker_threshold 0.015
(Set the individual attacker threshold)

● set_si_mode –num_si_iteration 3 (Perform 3 SI iterations)

● set_si_mode -separate_delta_delay_on_data true -enable_delay_report true

(Separate delta delay on data)

● set_delay_cal_mode –siAware true (Enable SI-aware delay calculation)

● report_timing (for report the timing violations)

● report_delay_calculation –si –from inst1/A –to inst1/Y

(Report details of SI delay calculation for an arc)

● report_noise –delay {min | max} (report delay uncertainty due to SI)

30
SI enabling switches
● set_delay_cal_mode –siAware true
(Enable signal integrity (SI) analysis)

● set_si_mode –enable_glitch_report true

(Perform glitch analysis and enable the glitch reports to be generated)

● set_si_mode -enable_glitch_propagation true

(enable glitch propagation)

● update_glitch (perform glitch analysis)

● report_noise -txtfile glitch.txt (generate SI glitch report)

31
Fixing of SI glitch through ECOs
● The below example shows fixing Si glitch violations only:

set_eco_opt_mode –fix_max_cap false –fix_max_tran false –fix_glitch true

● The below example shows fixing of SI glitch violations using DRV fixing in addition to regular
max_tran/max_cap violations:

set_eco_opt_mode -fix_glitch true

eco_opt_design -drv

32
ECO generated glitch files

33
This is the file generated for innovus team (PNR)

34
Functional ECO

Ibias pin

read_spi

dma spi

35
Adding a functional cell in between modules

read_
spi
newnet
dma spi

ibias( net)

Ibias
pin

36
Commands to add Functional ECO
● detach_net read_spi SPI_INST/p214748365A/B1
● add_inst ecoAND FreePDK45_lib_v1.0/AND2_X1
● add_net balanet
● attach_net balanet ecoAND/A1
● attach_net balanet SPI_INST/p214748365A/B1
● attach_net read_spi ecoAND/ZN
● attach_net ibias ecoAND/A2

By using above commands we can add a cell in between modules. This we called it as
Functional ECO

37
Conclusion

38