3977

Data Sheet
26184.22B
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
The A3977xED and A3977xLP are complete microstepping motor
A3977xED
drivers with built-in translator. They are designed to operate bipolar
(PLCC)
stepper motors in full-, half-, quarter-, and eighth-step modes, with
SUPPLY1

ENABLE
SENSE1

output drive capability of 35 V and ±2.5 A. The A3977 includes a

SLEEP
OUT1A

OUT1B
HOME

LOAD
GND

GND

GND
DIR

fixed off-time current regulator that has the ability to operate in slow-,
41

40
44

43

42
2

1
4

3
5
6

VBB1

NC 7 39 NC fast-, or mixed-decay modes. This current-decay control scheme

CHARGE PUMP

NC 8 38 CP2
results in reduced audible motor noise, increased step accuracy, and
TIMER
PWM

PFD 9 37 CP1

RC1 10 VCP
reduced power dissipation.
36

The translator is the key to the easy implementation of the A3977.

& CONTROL LOGIC

GND 11 GND
TRANSLATOR

35

GND 12 34 GND
By simply inputting one pulse on the STEP input the motor will take
GND 13 GND

REG
33
one step (full, half, quarter, or eighth depending on two logic inputs).
REF 14 ÷8 32 VREG

RC2 15 31 STEP
There are no phase-sequence tables, high-frequency control lines, or
LOGIC
SUPPLY 16 VDD 30 NC complex interfaces to program. The A3977 interface is an ideal fit for
NC 17 29 NC applications where a complex µP is unavailable or over-burdened.
VBB2
Internal synchronous-rectification control circuitry is provided to
SENSE2 21
OUT2A 18

MS1 20

GND 22

GND 23

SUPPLY2 25
GND 24

SR 26
MS2 19

OUT2B 28
RESET 27
LOAD

improve power dissipation during PWM operation.

Dwg. PP-075-1

Internal circuit protection includes thermal shutdown with hyster-

esis, under-voltage lockout (UVLO) and crossover-current protection.
ABSOLUTE MAXIMUM RATINGS Special power-up sequencing is not required.
The A3977 is supplied in a choice of two power packages, a 44-
Load Supply Voltage, VBB ............. 35 V lead plastic PLCC with copper batwing tabs (suffix ED), and a thin
Output Current, IOUT .................. ±2.5 A*
(<1.2 mm), 28-lead TSSOP with an exposed thermal pad (suffix LP).
Logic Supply Voltage, VDD ........... 7.0 V
Logic Input Voltage Range, VIN
FEATURES
(tw >30 ns) .... -0.3 V to VDD + 0.3 V
(tw <30 ns) .......... -1 V to VDD + 1 V ■ ±2.5 A, 35 V Output Rating
Sense Voltage, VSENSE ................ 0.5 V ■ Low rDS(on) Outputs, 0.45 Ω Source, 0.36 Ω Sink Typical
Reference Voltage, VREF ................. VDD ■ Automatic Current Decay Mode Detection/Selection
Package Power Dissipation,
■ 3.0 V to 5.5 V Logic Supply Voltage Range
PD ................................ See page 3
Operating Temperature Range, TA ■ Mixed, Fast, and Slow Current Decay Modes
(A3977Kx) ............ -40°C to +125°C ■ Home Output
(A3977Sx) .............. -20°C to +85°C ■ Synchronous Rectification for Low Power Dissipation
Junction Temperature, TJ ......... +150°C
Storage Temperature Range, ■ Internal UVLO and Thermal Shutdown Circuitry
TS ......................... -55°C to +150°C ■ Crossover-Current Protection
* Output current rating may be limited by
duty cycle, ambient temperature, and heat
sinking. Under any set of conditions, do not Always order by complete part number: the prefix ‘A’ + the basic part number
exceed the specified current rating or a (3977) + a suffix letter to indicate operating temperature range + a two-letter
junction temperature of 150°C.
suffix to indicate package style, e.g., A3977SLP .
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

FUNCTIONAL BLOCK DIAGRAM

LOGIC VREG CP2 CP1

LOAD
SUPPLY
2V VCP SUPPLY
VDD UVLO REGULATOR CHARGE
AND PUMP
FAULT BANDGAP
REF. VBB1
SUPPLY
REF DMOS H BRIDGE
DAC SENSE1 VCP
+ -

RC1 OUT1A
PWM LATCH
BLANKING OUT1B
MIXED DECAY

4 PWM TIMER

STEP
SENSE1
DIR
TRANSLATOR

RESET
GATE DRIVE
CONTROL LOGIC

MS1
DMOS H BRIDGE
MS2 VBB2
HOME
SLEEP OUT2A
VPFD SR
OUT2B
ENABLE

PWM TIMER
PFD
4 PWM LATCH
BLANKING
MIXED DECAY

RC2
+ -
SENSE2
DAC

Dwg. FP-050-2

115 Northeast Cutoff, Box 15036

2 Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2002, 2003 Allegro MicroSystems, Inc.
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

A3977xLP
(TSSOP)

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

5.0

LOAD
SENSE1 1 VBB1 28 SUPPLY1
SUFFIX '–LP', RθJA = 28°C/W*
HOME 2 27 SLEEP 4.0
DIR 3 26 ENABLE

OUT1A 4 25 OUT1B
SUFFIX '–ED', RθJA = 32°C/W†
3.0
TIMER

CHARGE PUMP
PWM

PFD 5 24 CP2

RC1 6 23 CP1
SUFFIX '–LP',
& CONTROL LOGIC

RθJA = 33°C/W†
TRANSLATOR

AGND 7 22 VCP
2.0
REF 8 ÷8 21 PGND

RC2 9 REG 20 VREG

LOGIC 1.0
10 VDD 19 STEP
SUPPLY SUFFIX 'S–'
OUT2A 11 18 OUT2B
SUFFIX 'K–'
MS2 12 17 RESET
0
MS1 13 16 SR 25 50 75 100 125 150
SENSE2 14 15
LOAD AMBIENT TEMPERATURE IN °C
VBB2
SUPPLY2
Dwg. GP-018-2A
Dwg. PP-075
Package Thermal Resistance, RθJA
A3977xLP ......................... 28°C/W*
A3977xED ........................ 32°C/W†
A3977xLP ......................... 33°C/W†
* Measured on JEDEC standard “High-K” four-layer board.
† Measured on typical two-sided PCB with three square inches
(1935 mm2) copper ground area.

Table 1. Microstep Resolution Truth Table

MS1 MS2 Resolution

L L Full step (2 phase)
H L Half step
L H Quarter step
H H Eighth step

www.allegromicro.com 3
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise

noted)
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range VBB Operating 8.0 – 35 V
During sleep mode 0 – 35 V
Output Leakage Current IDSS VOUT = VBB – <1.0 20 µA
VOUT = 0 V – <1.0 -20 µA
Output On Resistance rDS(on) Source driver, IOUT = -2.5 A – 0.45 0.57 Ω
Sink driver, IOUT = 2.5 A – 0.36 0.43 Ω
Body Diode Forward Voltage VF Source diode, IF = -2.5 A – – 1.4 V
Sink diode, IF = 2.5 A – – 1.4 V
Motor Supply Current IBB fPWM < 50 kHz – – 8.0 mA
Operating, outputs disabled – – 6.0 mA
Sleep mode – – 20 µA
Control Logic
Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V
Logic Input Voltage VIN(1) 0.7VDD – – V
VIN(0) – – 0.3VDD V
Logic Input Current IIN(1) VIN = 0.7VDD -20 <1.0 20 µA
IIN(0) VIN = 0.3VDD -20 <1.0 20 µA
Maximum STEP Frequency fSTEP 500* – – kHz
HOME Output Voltage VOH IOH = -200 µA 0.7VDD – – V
VOL IOL = 200 µA – – 0.3VDD V
Blank Time tBLANK Rt = 56 kΩ, Ct = 680 pF 700 950 1200 ns
Fixed Off Time toff Rt = 56 kΩ, Ct = 680 pF 30 38 46 µs
continued next page …

115 Northeast Cutoff, Box 15036

4 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR

ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 35 V, VDD = 3.0 V to 5.5V (unless otherwise

noted)
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Control Logic (cont’d)
Mixed Decay Trip Point PFDH – 0.6VDD – V
PFDL – 0.21VDD – V
Ref. Input Voltage Range VREF Operating 0 – VDD V
Reference Input Current IREF – 0 ±3.0 µA
Gain (Gm) Error EG VREF = 2 V, Phase Current = 38.27% – – ±10 %
(note 3) VREF = 2 V, Phase Current = 70.71% – – ±5.0 %
VREF = 2 V, Phase Current = 100.00% – – ±5.0 %
Crossover Dead Time tDT SR enabled 100 475 800 ns
Thermal Shutdown Temp. TJ – 165 – °C
Thermal Shutdown Hysteresis ∆TJ – 15 – °C
UVLO Enable Threshold VUVLO Increasing VDD 2.45 2.7 2.95 V
UVLO Hysteresis ∆VUVLO 0.05 0.10 – V
Logic Supply Current IDD fPWM < 50 kHz – – 12 mA
Outputs off – – 10 mA
Sleep mode – – 20 µA
* Operation at a step frequency greater than the specified minimum value is possible but not warranteed.
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = ([VREF/8] – VSENSE)/(VREF/8)

www.allegromicro.com 5
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MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Functional Description
Device Operation. The A3977 is a complete Step Input (STEP). A low-to-high transition on the
microstepping motor driver with built in translator for STEP input sequences the translator and advances the
easy operation with minimal control lines. It is designed motor one increment. The translator controls the input to
to operate bipolar stepper motors in full-, half-, quarter- the DACs and the direction of current flow in each wind-
and eighth-step modes. The current in each of the two ing. The size of the increment is determined by the state
output H-bridges, all n-channel DMOS, is regulated with of inputs MS1 and MS2 (see table 1).
fixed off time pulse-width modulated (PWM) control
Microstep Select (MS1 and MS2). Input terminals
circuitry. The H-bridge current at each step is set by the
MS1 and MS2 select the microstepping format per
value of an external current sense resistor (RS), a reference
table 1. Changes to these inputs do not take effect until
voltage (VREF), and the DAC’s output voltage controlled
the STEP command (see figure).
by the output of the translator.
Direction Input (DIR). The state of the DIRECTION
At power up, or reset, the translator sets the DACs and
input will determine the direction of rotation of the motor.
phase current polarity to initial home state (see figures for
home-state conditions), and sets the current regulator for Internal PWM Current Control. Each H-bridge is
both phases to mixed-decay mode. When a step command controlled by a fixed off time PWM current-control circuit
signal occurs on the STEP input the translator automati- that limits the load current to a desired value (ITRIP).
cally sequences the DACs to the next level (see table 2 for Initially, a diagonal pair of source and sink DMOS outputs
the current level sequence and current polarity). The are enabled and current flows through the motor winding
microstep resolution is set by inputs MS1 and MS2 as and RS. When the voltage across the current-sense resistor
shown in table 1. If the new DAC output level is lower equals the DAC output voltage, the current-sense com-
than the previous level the decay mode for that H-bridge parator resets the PWM latch, which turns off the source
will be set by the PFD input (fast, slow or mixed decay). driver (slow-decay mode) or the sink and source drivers
If the new DAC level is higher or equal to the previous (fast- or mixed-decay modes).
level then the decay mode for that H-bridge will be slow
The maximum value of current limiting is set by the
decay. This automatic current-decay selection will
selection of RS and the voltage at the VREF input with a
improve microstepping performance by reducing the
transconductance function approximated by:
distortion of the current waveform due to the motor
BEMF. ITRIPmax = VREF/8RS
Reset Input (RESET). The RESET input (active low) The DAC output reduces the VREF output to the
sets the translator to a predefined home state (see figures current-sense comparator in precise steps (see table 2 for
for home state conditions) and turns off all of the DMOS % ITRIPmax at each step).
outputs. The HOME output goes low and all STEP inputs ITRIP = (% ITRIPmax/100) x ITRIPmax
are ignored until the RESET input goes high.
It is critical to ensure that the maximum rating (0.5 V)
Home Output (HOME). The HOME output is a logic on the SENSE terminal is not exceeded. For full-step
output indicator of the initial state of the translator. At mode, VREF can be applied up to the maximum rating of
power up the translator is reset to the home state (see VDD, because the peak sense value is 0.707 x VREF/8. In
figures for home state conditions). all other modes VREF should not exceed 4 V.

115 Northeast Cutoff, Box 15036

6 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Functional Description (cont’d)

Fixed Off-Time. The internal PWM current-control Shutdown. In the event of a fault (excessive junction
circuitry uses a one shot to control the time the driver(s) temperature, or low voltage on VCP) the outputs of the
remain(s) off. The one shot off-time, toff, is determined by device are disabled until the fault condition is removed.
the selection of an external resistor (RT) and capacitor At power up, and in the event of low VDD, the under-
(CT) connected from the RC timing terminal to ground. voltage lockout (UVLO) circuit disables the drivers and
The off time, over a range of values of CT = 470 pF to resets the translator to the HOME state.
1500 pF and RT = 12 kΩ to 100 kΩ is approximated by: Sleep Mode (SLEEP). An active-low control input
toff = RTCT used to minimize power consumption when not in use.
This disables much of the internal circuitry including the
RC Blanking. In addition to the fixed off time of the
output DMOS, regulator, and charge pump. A logic high
PWM control circuit, the CT component sets the compara-
allows normal operation and startup of the device in the
tor blanking time. This function blanks the output of the
home position. When coming out of sleep mode, wait
current-sense comparator when the outputs are switched
1 ms before issuing a STEP command to allow the charge
by the internal current-control circuitry. The comparator
pump (gate drive) to stabilize.
output is blanked to prevent false over-current detection
due to reverse recovery currents of the clamp diodes, and/ Percent Fast Decay Input (PFD). When a STEP
or switching transients related to the capacitance of the input signal commands a lower output current from the
load. The blank time tBLANK can be approximated by: previous step, it switches the output current decay to either
slow-, fast-, or mixed-decay depending on the voltage
tBLANK = 1400CT
level at the PFD input. If the voltage at the PFD input is
Charge Pump. (CP1 and CP2). The charge pump is greater than 0.6VDD then slow-decay mode is selected. If
used to generate a gate supply greater than VBB to drive the voltage on the PFD input is less than 0.21VDD then
the source-side DMOS gates. A 0.22 µF ceramic capaci- fast-decay mode is selected. Mixed decay is between
tor should be connected between CP1 and CP2 for pump- these two levels. This terminal should be decoupled with
ing purposes. A 0.22 µF ceramic capacitor is required a 0.1 µF capacitor.
between VCP and VBB to act as a reservoir to operate the
Mixed Decay Operation. If the voltage on the PFD
high-side DMOS devices.
input is between 0.6VDD and 0.21VDD, the bridge will
VREG. This internally generated voltage is used to operate operate in mixed-decay mode depending on the step
the sink-side DMOS outputs. The VREG terminal should sequence (see figures). As the trip point is reached, the
be decoupled with a 0.22 µF capacitor to ground. VREG is device will go into fast-decay mode until the voltage on
internally monitored and in the case of a fault condition, the RC terminal decays to the voltage applied to the PFD
the outputs of the device are disabled. terminal. The time that the device operates in fast decay is
approximated by:
Enable Input (ENABLE). This active-low input
enables all of the DMOS outputs. When logic high the tFD = RTCTIn (0.6VDD/VPFD)
outputs are disabled. Inputs to the translator (STEP,
After this fast decay portion, tFD, the device will
DIRECTION, MS1, MS2) are all active independent of the
switch to slow-decay mode for the remainder of the fixed
ENABLE input state.
off-time period.

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MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Functional Description (cont’d)

Synchronous Rectification. When a PWM off cycle Active Mode. When the SR input is logic low, active
is triggered by an internal fixed off-time cycle, load mode is enabled and synchronous rectification will occur.
current will recirculate according to the decay mode This mode prevents reversal of the load current by turning
selected by the control logic. The A3977 synchronous off synchronous rectification when a zero current level is
rectification feature will turn on the appropriate detected. This prevents the motor winding from conduct-
MOSFETs during the current decay and effectively short ing in the reverse direction.
out the body diodes with the low rDS(on) driver. This will
Disabled Mode. When the SR input is logic high,
reduce power dissipation significantly and eliminate the
synchronous rectification is disabled. This mode is
need for external Schottky diodes for most applications.
typically used when external diodes are required to
The synchronous rectification can be set in either transfer power dissipation from the A3977 package to the
active mode or disabled mode. external diodes.

Timing Requirements
(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)

STEP 50%

C D

A B

MS1/MS2/
DIR/RESET

SLEEP

Dwg. WP-042

A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns
B. Minimum Command Active Time
After Step Pulse (Data Hold Time) ............ 200 ns
C. Minimum STEP Pulse Width ...................... 1.0 µs
D. Minimum STEP Low Time ......................... 1.0 µs
E. Maximum Wake-Up Time ......................... 1.0 ms

115 Northeast Cutoff, Box 15036

8 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Applications Information
Layout. Current Sensing. To minimize inaccuracies caused by
The printed wiring board should use a heavy ground ground-trace IR drops in sensing the output current level,
plane. the current-sense resistor (RS) should have an independent
ground return to the star ground of the device. This path
For optimum electrical and thermal performance, the
should be as short as possible. For low-value sense
driver should be soldered directly onto the board.
resistors the IR drops in the printed wiring board sense
The load supply terminal, VBB, should be decoupled resistor’s traces can be significant and should be taken
with an electrolytic capacitor (>47 µF is recommended) into account. The use of sockets should be avoided as
placed as close to the device as possible. they can introduce variation in RS due to their contact
resistance.
To avoid problems due to capacitive coupling of the
high dv/dt switching transients, route the bridge-output Allegro MicroSystems recommends a value of RS
traces away from the sensitive logic-input traces. Always given by
drive the logic inputs with a low source impedance to
RS = 0.5/ITRIPmax
increase noise immunity.
Thermal Protection. Circuitry turns off all drivers
Grounding. A star ground system located close to the
when the junction temperature reaches 165°C, typically.
driver is recommended.
It is intended only to protect the device from failures due
The 44-lead PLCC has the analog ground and the to excessive junction temperatures and should not imply
power ground internally bonded to the power tabs of the that output short circuits are permitted. Thermal shut-
package (leads 44, 1, 2, 11 – 13, 22 – 24, and 33 – 35). down has a hysteresis of approximately 15°C.
On the 28-lead TSSOP package, the analog ground
(lead 7) and the power ground (lead 21) must be con-
nected together externally. The copper ground plane
located under the exposed thermal pad is typically used as
the star ground.

www.allegromicro.com 9
 3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR

Table 2. Step Sequencing

Home State = 45º Step Angle, DIR = H

Phase 1 Current Phase 2 Current

Step Angle
Full Step Half Step ¼ Step ⅛ Step (%Itripmax) (%Itripmax)
(º)
(%) (%)
1 1 1 100.00 0.00 0.0
2 98.08 19.51 11.3
2 3 92.39 38.27 22.5
4 83.15 55.56 33.8
1 2 3 5 70.71 70.71 45.0
6 55.56 83.15 56.3
4 7 38.27 92.39 67.5
8 19.51 98.08 78.8
3 5 9 0.00 100.00 90.0
10 –19.51 98.08 101.3
6 11 –38.27 92.39 112.5
12 –55.56 83.15 123.8
2 4 7 13 –70.71 70.71 135.0
14 –83.15 55.56 146.3
8 15 –92.39 38.27 157.5
16 –98.08 19.51 168.8
5 9 17 –100.00 0.00 180.0
18 –98.08 –19.51 191.3
10 19 –92.39 –38.27 202.5
20 –83.15 –55.56 213.8
3 6 11 21 –70.71 –70.71 225.0
22 –55.56 –83.15 236.3
12 23 –38.27 –92.39 247.5
24 –19.51 –98.08 258.8
7 13 25 0.00 –100.00 270.0
26 19.51 –98.08 281.3
14 27 38.27 –92.39 292.5
28 55.56 –83.15 303.8
4 8 15 29 70.71 –70.71 315.0
30 83.15 –55.56 326.3
16 31 92.39 –38.27 337.5
32 98.08 –19.51 348.8

115 Northeast Cutoff, Box 15036

10 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Full-Step Operation
MS1 = MS2 = L, DIR = H

STEP
INPUT

HOME
OUTPUT

SLOW
DECAY
70.7%

PHASE 1
CURRENT

–70.7%

SLOW
DECAY
70.7%

PHASE 2
CURRENT

–70.7%
Dwg. WK-004-15

The vector addition of the output currents at any step is

100%.

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Half-Step Operation
MS1 = H, MS2 = L, DIR = H

STEP
INPUT

HOME
OUTPUT

DECAY

DECAY
DECAY

DECAY
DECAY

DECAY
DECAY

DECAY
MIXED

MIXED
MIXED

MIXED
SLOW

SLOW
SLOW

SLOW
100%
70.7%

PHASE 1
CURRENT

–70.7%
–100%
DECAY
DECAY

DECAY
DECAY

DECAY

DECAY
DECAY

DECAY
MIXED

SLOW
MIXED

SLOW

MIXED

MIXED
SLOW

SLOW
100%
70.7%

PHASE 2
CURRENT

–70.7%
–100%
Dwg. WK-004-14

The mixed-decay mode is controlled by the percent fast

decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.

115 Northeast Cutoff, Box 15036

12 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Quarter-Step Operation
MS1 = L, MS2 = H, DIR = H

STEP
INPUT

HOME
OUTPUT

SLOW MIXED SLOW MIXED

DECAY DECAY DECAY DECAY
100%
70.7%
38.3%
PHASE 1
CURRENT
–38.3%
–70.7%
–100%

MIXED SLOW MIXED SLOW

DECAY DECAY DECAY DECAY
100%
70.7%
38.3%
PHASE 2
CURRENT
–38.3%
–70.7%
–100%
Dwg. WK-004-13

The mixed-decay mode is controlled by the percent fast

decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.

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8 Microstep/Step Operation
MS1 = MS2 = H, DIR = H
STEP
INPUT

HOME
OUTPUT

SLOW MIXED SLOW MIXED

DECAY DECAY DECAY DECAY
100%
70.7%
38.3%
PHASE 1
CURRENT
–38.3%
–70.7%
–100%

MIXED SLOW MIXED SLOW

DECAY DECAY DECAY DECAY
100%
70.7%
38.3%
PHASE 2
CURRENT
–38.3%
–70.7%
–100%
Dwg. WK-004-12

The mixed-decay mode is controlled by the percent fast

decay voltage (VPFD). If the voltage at the PFD input is
greater than 0.6VDD then slow-decay mode is selected. If
the voltage on the PFD input is less than 0.21VDD then
fast-decay mode is selected. Mixed decay is between
these two levels.

115 Northeast Cutoff, Box 15036

14 Worcester, Massachusetts 01615-0036 (508) 853-5000
 3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR

Terminal List

Terminal A3977xLP A3977xED

Name Terminal Description (TSSOP) (PLCC)
GND Analog and power ground – 44, 1, 2
SENSE1 Sense resistor for bridge 1 1 3
HOME Logic output 2 4
DIR Logic Input 3 5
OUT1A DMOS H bridge 1 output A 4 6
NC No (internal) connection – 7, 8
PFD Mixed decay setting 5 9
RC1 Analog Input for fixed offtime – bridge 1 6 10
GND Analog and power ground – 11, 12, 13
AGND Analog ground 7* –
REF Gm reference input 8 14
RC2 Analog input for fixed offtime – bridge 2 9 15
LOGIC SUPPLY VDD, the logic supply voltage 10 16
NC No (internal) connection – 17
OUT2A DMOS H bridge 2 output A 11 18
MS2 Logic input 12 19
MS1 Logic input 13 20
SENSE2 Sense resistor for bridge 2 14 21
GND Analog and power ground – 22, 23, 24
LOAD SUPPLY2 VBB2, the load supply for bridge 2 15 25
SR Logic input 16 26
RESET Logic input 17 27
OUT2B DMOS H bridge 2 output B 18 28
NC No (internal) connection – 29, 30
STEP Logic input 19 31
VREG Regulator decoupling 20 32
PGND Power ground 21* –
GND Analog and power ground – 33, 34, 35
VCP Reservoir capacitor 22 36
CP1 Charge pump capacitor 23 37
CP2 Charge pump capacitor 24 38
NC No (internal) connection – 39
OUT1B DMOS H bridge 1 output B 25 40
ENABLE Logic input 26 41
SLEEP Logic input 27 42
LOAD SUPPLY1 VBB1, the load supply for bridge 1 28 43

* AGND and PGND on the TSSOP package must be connected together externally.

www.allegromicro.com 15
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A3977xED
28 18

29 17
0.032
0.319 0.026
0.291

0.021 0.695
0.013 0.685
Dimensions in Inches
0.656 (controlling dimensions)
0.650
INDEX AREA
0.319
0.291
0.050
BSC
39 7

40 44 1 2 6

0.020 0.656
MIN 0.650
0.180 0.695
0.165 0.685
Dwg. MA-005-44A in

28 18

29 17
0.812
8.10 0.661
7.39

0.533 17.65
0.331 17.40
Dimensions in Millimeters
16.662 (for reference only)
16.510
INDEX AREA
8.10
7.39
1.27
BSC
39 7

40 44 1 2 6

0.51 16.662
MIN 16.510
4.57 17.65
4.20 17.40
Dwg. MA-005-44A mm

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Webbed lead frame. Terminals 1, 2, 11, 12, 13, 22, 23, 24, 33, 34, 35, and 44 are internally one piece.
4. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.

115 Northeast Cutoff, Box 15036

16 Worcester, Massachusetts 01615-0036 (508) 853-5000
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A3977xLP
0.197
28 15

0.0394
REF

0.177 0.118
0.169 0.0098
BSC
INDEX GAUGE PLANE
AREA
SEATING PLANE

0° TO 8° 0.030
0.012 1 2 3 0.026 0.018
0.0075 0.386 BSC Dimensions in Inches
0.378 (for reference only)

0.260
0.244

0.0472 0.0079
MAX 0.0035

0.0059 EXPOSED
0.00 THERMAL PAD
Dwg. MA-008-30A in

5.0
28 15

1.00
REF

4.50 3.0
4.30 0.25
BSC
INDEX GAUGE PLANE
AREA
SEATING PLANE

0° TO 8° 0.75
0.30 1 2 3 0.65 0.45
0.19 9.80 BSC
9.60
Dimensions in Millimeters
(controlling dimensions)
6.60
6.20

0.20
1.20 0.09
MAX

0.15 EXPOSED
0.00 THERMAL PAD
Dwg. MA-008-30A mm

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.

www.allegromicro.com 17
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The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

115 Northeast Cutoff, Box 15036

18 Worcester, Massachusetts 01615-0036 (508) 853-5000
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.