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    Lab Manual NBA

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    SHAMINDRA SEN
    The document describes experiments to design and simulate basic logic gates using Xilinx and VHDL/Verilog. It includes experiments on an XOR gate, half adder, and 4:1 multiplexer. The objective is to design each circuit using VHDL, simulate using Verilog, and verify the output waveform matches the theoretical behavior. VHDL and Verilog code are provided for each circuit along with conclusions about using VHDL/Verilog for synthesis.

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    Lab Manual NBA

    Uploaded by

    SHAMINDRA SEN
    66 views14 pages
    The document describes experiments to design and simulate basic logic gates using Xilinx and VHDL/Verilog. It includes experiments on an XOR gate, half adder, and 4:1 multiplexer. The objective is to design each circuit using VHDL, simulate using Verilog, and verify the output waveform matches the theoretical behavior. VHDL and Verilog code are provided for each circuit along with conclusions about using VHDL/Verilog for synthesis.

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    The document describes experiments to design and simulate basic logic gates using Xilinx and VHDL/Verilog. It includes experiments on an XOR gate, half adder, and 4:1 multiplexer. The objective is to design each circuit using VHDL, simulate using Verilog, and verify the output waveform matches the theoretical behavior. VHDL and Verilog code are provided for each circuit along with conclusions about using VHDL/Verilog for synthesis.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    66 views14 pages

    Lab Manual NBA

    Uploaded by

    SHAMINDRA SEN
    The document describes experiments to design and simulate basic logic gates using Xilinx and VHDL/Verilog. It includes experiments on an XOR gate, half adder, and 4:1 multiplexer. The objective is to design each circuit using VHDL, simulate using Verilog, and verify the output waveform matches the theoretical behavior. VHDL and Verilog code are provided for each circuit along with conclusions about using VHDL/Verilog for synthesis.

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    © All Rights Reserved
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    of 14

    EXPERIMENT NO-

    AIM: Design and simulation of XOR gate using Xilink.

    OBJECTIVE: To design XOR gate and simulate its operation using Xilink
    Software and VHDL in dataflow model.

    THEORY:
    XOR gates have two inputs and one output and they implement the
    special boolean logic of inequality detection. The EXOR gate gives a high
    output every time it detects an inequality in the inputs. Its equation is as
    follows Y (A xor B) = AB’ + A’B

    This can be implemented using VHDL codes and can be simulated using a
    verilog program.It is verified by matching the output waveform with
    theoritical knowledge.

    VHDL PROGRAM:
    entity XOR1 is
    port(a: in STD_LOGIC;b: in STD_LOGIC;c: out STD_LOGIC;);
    end XOR1;
    architecture dataflow of XOR1 is
    begin
    c<=a XOR b;
    end dataflow;

    VERILOG PROGRAM:
    Module XOR1
    Reg a;
    Reg b;
    wire c;
    XOR1 uut (a(a);b(b);c(c););
    Initial begin
    a=0;
    b=0;
    #100;
    a=0;
    b=1;
    #100
    a=1;
    b=0;
    #100
    a=1;
    b=1;
    #100
    End;
    End module;
    OUTPUT WAVEFORM:

    CONCLUSION:
    Many VHDL constructs although useful for simulation and other
    Stages in the design process are not relevant for synthesis.A subset of
    VHDL can only be used for synthesis.
    Verilog is much more easier to use and learn and is most widely used in
    synthesis and simulation.It is also used in ASIC design.
    EXPERIMENT NO-

    AIM: Design and simulation of Half Adder using Xilink.

    OBJECTIVE: To design Half Adder and simulate its operation using Xilink
    Software and VHDL in dataflow model.

    THEORY:

    S=A XOR B;
    C=A AND B;
    This can be implemented using VHDL codes and can be simulated using a
    verilog program.It is verified by matching the output waveform with
    theoritical knowledge.

    VHDL PROGRAM:
    entity HA is
    port(a: in STD_LOGIC;b: in STD_LOGIC;S: out STD_LOGIC;
    C: out STD_LOGIC;);
    end HA;
    architecture dataflow of XOR1 is
    Begin
    S<=a XOR b;
    C<=a AND b;
    end dataflow;

    VERILOG PROGRAM:
    Module HA
    Reg a;
    Reg b;
    Wire s;
    Wire c;
    XOR1 uut (.a(a);.b(b);.C(C);.S(S));
    Initial begin
    a=0;
    b=0;
    #100;
    a=0;
    b=1;
    #100
    a=1;
    b=0;
    #100
    a=1;
    b=1;
    #100
    End;
    End module;

    OUTPUT WAVEFORM:
    CONCLUSION:
    Many VHDL constructs although useful for simulation and other
    Stages in the design process are not relevant for synthesis.A subset of
    VHDL can only be used for synthesis.
    Verilog is much more easier to use and learn and is most widely used in
    synthesis and simulation.It is also used in ASIC design.
    EXPERIMENT NO-

    AIM: Design and simulation of 4:1 MUX using Xilink.

    OBJECTIVE: To design 4:1 MUX and simulate its operation using Xilink
    Software and VHDL in behavioral model.

    THEORY:
    A multiplexer is a data selector. It has multiple inputs, out of which it
    selects one and connects that one to the output. This selection is done
    on the basis of the values of the select inputs. In this program, we will
    write the VHDL code for a 4:1 Mux. A 4:1 mux will have two select inputs.
    Since we are using behavioral architecture, it is necessary to understand
    and implement the logic circuit’s truth table.

    I0 I1 I2 I3 S0 S1 Y

    I0 x x x 0 0 I0

    x I1 x x 0 1 I1
    x x I2 x 1 0 I2

    x x x I3 1 1 I3

    Truth table of a 4:1 Mux:


    VHDL PROGRAM:
    entity MUX_SOURCE is
    Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
    I : in STD_LOGIC_VECTOR (3 downto 0);
    Y : out STD_LOGIC);
    end MUX_SOURCE;
    architecture Behavioral of MUX_SOURCE is
    begin
    process (S,I)
    begin
    if (S <= "00") then
    Y <= I(0);
    elsif (S <= "01") then
    Y <= I(1);
    elsif (S <= "10") then
    Y <= I(2);
    else
    Y <= I(3);
    end if;
    end process;
    end Behavioral;

    VERILOG PROGRAM:
    module MUX_SOURCE;
    reg [3:0] a;
    reg [3:0] b;
    reg [3:0] c;
    reg [3:0] d;
    wire [3:0] out;
    reg [1:0] sel;
    integer i;
    MUX_SOURCE mux0 ( .a (a),
    .b (b),
    .c (c),
    .d (d),
    .sel (sel),
    .out (out));

    initial begin
    // Launch a monitor in background to display values to log whenever
    a/b/c/d/sel/out changes//
    $monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h
    out=0x%0h", $time, sel, a, b, c, d, out);

    // 1. At time 0, drive random values to a/b/c/d and keep sel = 0


    sel <= 0;
    a <= $random;
    b <= $random;
    c <= $random;
    d <= $random;
    // 2. Change the value of sel after every 5ns
    for (i = 1; i < 4; i=i+1) begin
    #5 sel <= i;
    end

    // 3. After Step2 is over, wait for 5ns and finish simulation


    #5 $finish;
    end
    endmodule
    OUTPUT WAVEFORM:

    CONCLUSION:
    Many VHDL constructs although useful for simulation and other
    Stages in the design process are not relevant for synthesis.A subset of
    VHDL can only be used for synthesis.
    Verilog is much more easier to use and learn and is most widely used in
    synthesis and simulation.It is also used in ASIC design.

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