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Lab 1

The document provides instructions for students in a VLSI Design Lab course to simulate multiplexers using Verilog, including writing code for a 2-to-1 and 4-to-1 multiplexer, developing testbenches, and using the Incisive Enterprise Simulator tool to compile, elaborate, simulate, and verify that the multiplexers are functioning correctly as designed. Students are then tasked with writing behavioral models and testbenches for an 8-to-1 multiplexer.

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Masud Sarker
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96 views

Lab 1

The document provides instructions for students in a VLSI Design Lab course to simulate multiplexers using Verilog, including writing code for a 2-to-1 and 4-to-1 multiplexer, developing testbenches, and using the Incisive Enterprise Simulator tool to compile, elaborate, simulate, and verify that the multiplexers are functioning correctly as designed. Students are then tasked with writing behavioral models and testbenches for an 8-to-1 multiplexer.

Uploaded by

Masud Sarker
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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United International University (UIU)

Dept. of Electrical and Electronic Engineering (EEE)


Course: VLSI Design Lab (EEE 442)

Experiment 1: Simulation of Multiplexers using Verilog

Introduction:

1. Collect the login ID and password from the lab instructor, log into your account and familiarize
yourself with the Linux Operating system. Practice the Linux commands provided in the
attached document.

2. Copy the cshrc file to your home directory as .cshrc file


 cd -- moves you to your home directory
 cp ~sahmed/cshrc .cshrc

3. Switch to csh, this will setup your cadence tools environment variables
 csh

4. Create a lab directory and a simulation sub-directory under your work area:
 mkdir lab1
 cd lab1
 mkdir simulation
 cd simulation

5. Use an editor (vi, nedit, gedit etc.) to write the Verilog code for a 2-to-1 multiplexer (MUX)
 nedit mux21.v &

6. Use an editor to write a test bench Verilog code for your 2-to-1 MUX
 nedit mux21_test.v &

7. We will use Incisive Enterprise Simulator (IES) to verify that the MUX is working properly.
Invoke the tool by typing ‘nclaunch –new’ in the terminal
 nclaunch –new
8. NCLaunch window will appear. Click on the ‘Multiple Step’

9. ‘nclaunch: Open Design Directory’ window will appear. Click on the ‘Create cds.lib File’
10. ‘create a cds.lib file’ window will appear. Click on ‘Save’

11. ‘New cds.lib File’ window will appear. Select the third option since we are using Verilog. Click
on ‘OK’

12. Click ‘OK’ in the ‘nclaunch: Open Design Directory’ window.


13. In the NCLaunch window we will see the design (mux21.v) and the testbench (mux21_tb.v) that
we created in the simulation directory.

Command Entry Window

14. Now we will COMPILE the code to check their syntax and semantics. Select both the design
(mux21.v) and the testbench (mux21_test.v) and click on the ncvlog for Verilog designers.

15. Any error in the code will be reported in the ‘Command Entry Window’ (at the bottom of the
NCLaunch). Clean all the errors in the design and/or the testbench.
ELABORATION – constructs design hierarchy and connects signals

16. Open the ‘worklib’ directory on the right side of the window and select the test bench as it is the
top module (which contains the design module). Click on the ‘launch elaborator (ncelab)’

SIMULATION – executes simulation code

17. Open the ‘snapshots’ directory on the right side of the window and select the worklib of the test
bench. Click on ‘launch simulator’

18. ‘Console – SimVision’ window will appear. This is used to perform simulation in command
mode. Minimize this window since we will be using GUI mode for simulation.
19. ‘Design Browser – SimVision’ window also appears. There are many options in the ‘Design
Brwoser’ to analyze the design and debugging. Select the test bench module on the left side of
the window. Click on the ‘waveform’
20. ‘Wavefor – SimVision’ window will appear. In the waveform window we will see the ports of the
design. Click on the ‘run simulation’ to start the simulation. Use the ‘pause’ button to interrupt
or to stop simulation. Use different options like zoom in, zoom out etc. to analyze the plot.
There are many options in the ‘Waveform’ window to analyze the design and debugging.

run simulation

21. After verifying the design, close the tools.

22. Write Verilog code for a 4-to-1 MUX (mux41.v) using the 2-to-1 MUX you have just tested.
23. Write the test bench (Stimulus Module) for the above 4-to-1 MUX (mux41_test.v). The test
bench code must be according to the following information:
MUX Inputs: i0, i1, i2, i3
Selector inputs: s0, s1
The outputs: out = i0; for s0 = 0 and s1 = 0
out = i1; for s0 = 1 and s1 = 0
out = i2; for s0 = 0 and s1 = 1
out = i3; for s0 = 1 and s1 = 1
Choose the input values (clocks) as given below:
i0 = > Low = 05, High = 05
i1 = > Low = 10, High = 10
i2 = > Low = 20, High = 20
i3 = > Low = 40, High = 40
s0 = > Low = 80, High = 80
s1 = > Low = 160, High = 160
24. Use Incisive Enterprise Simulator (IES) to verify that the MUX is working properly. Invoke the
tool by typing ‘nclaunch’ without the ‘– new’ option since we will use the previously created
worklib.
 nclaunch

25. Follow the same steps described before to test the 4-to-1 MUX.

26. Write behavioral model of an 8-to-1 MUX. Must utilize vector notations for inputs/selectors.
Provide appropriate stimulus to run simulation.

27. Use Incisive Enterprise Simulator (IES) to verify that the 8-to-1 MUX is working properly. Follow
the same steps described before.

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