Design of high performance Booth Multiplier

Using Multiplexer
V Soma Sandeep K Bala Sindhuri N Udaya Kumar K Rajesh
PG Student Department of ECE Department of ECE PG Student
SRKR Engineering SRKR Engineering SRKR Engineering SRKR Engineering
College College College College
Bhimavaram Bhimavaram Bhimavaram Bhimavaram
[email protected] k.b.s [email protected] [email protected] [email protected]

Abstract— The demand for the improvement of digital signal In Booth multiplication, partial product generation depends
processing is highly increasing in present days. For this, more upon the recoding scheme e.g. Radix-2 encoding.
technological developments are required in computer and Multiplication using normal Booths recoding algorithm
microprocessor applications for meeting high speed and power technique based on the partial product can be generated for a
efficiency. Multiplier plays a crucial role in signal processing that group of consecutive 0‘s and 1‘s which is called Booths
will decide overall device speed, and power consumption. In recoding. This recoding algorithm is used to generate an
order to accomplish better performance, multiplexer based 8*8- efficient partial product. This increase in the width of partial
bit booth multiplier is designed and coding is done in Verilog. product usually depends upon the radix scheme used for
Simulation and synthesis are carried on Xilinx 14.5 software. The recoding [5].
proposed design reduces the area, power, and delay when
compared to the existing multipliers. The booth algorithm is an effective technique for 2s
complement multiplication. The booth algorithm reduces the
Keywords— Adder/subtractor, Area efficient, Booth multiplier, number of partial products by shifting over a string of zeros.
Multiplexer based adder/subtractor, Radix 4 Booth multiplier. The increase in speed is proportional to the number of zeroes
in the recoded version of the multiplier. In this radix2
I. INTRODUCTION algorithm, the main disadvantage is no. of partial products
increases when one of the inputs is alternatively 1‘s and 0‘s
Now a day‘s in the field of Digital Signal Processing and
i.e.,01010101 [6]-[8].
graphics applications, multiplication is an important and
computationally intensive operation [1]. It is certainly present This paper is structured as follows. Section II deals with
in many parts of a digital system or digital computer, most the conventional booth multiplier. Section III deals with the
notably in signal processing, graphics, and scientific proposed booth multiplier in detail such as Multiplexer based
computation. The efficiency of the multiplier has always been adder, 1-Bit adder/ subtractor and 9-Bit adder/subtractor.
a critical issue. An efficient multiplier should have following Section IV deals with the simulation, synthesis results and
characteristics like Accuracy, Speed, Area, and Power. comparison with the other booth multiplier designs. Finally,
Accuracy: - A good multiplier should give the correct result. Section V concludes the work done.
Speed: - Multiplier should perform the operation at high
speed. Area: -A multiplier should occupy a smaller number of II. CONVENTIONAL BOOTH MUTLIPLIER
LUTs. Power: -Multiplier should consume less power [2]. The
multiplier has intensive computations such as it generates In this conventional booth multiplier, n/2 stages and n/2
partial products then it reduces to one row of final sums and partial products exist, here n is input data length. Each stage
carries. Finally, the result was generated by adding final sums consists three blocks such as 9-Bit multiplexer, 9-Bit
and carries [3]. adder/subtractor and code. Only in stage 1 in place of 9-Bit
adder/subtractor block two more blocks namely 9-Bit mux
The sequential add-shift method, it treats positive and binary to 2‘s compliment and 9-Bit mux 2:1 are placed. This
negative numbers uniformly. In the sequential add-shift conventional booth multiplier structure is shown in Fig.1.From
method, each multiplier bit generates a rendering of the the literature it is found that this multiplier is consuming more
multiplicand that is added to the partial product. For large power and occupying more space [9]-[12].
operands, the delay to obtain the product can be substantial
[4].
 III. PROPOSED BOOTH MULTIPLIER
In order to address the disadvantages of conventional
booth multiplier it is decided to propose a new booth
multiplier. This proposed booth multiplier has blocks like
Multiplexer based adder, 1-Bit adder/ subtractor and 9-Bit
adder/subtractor. Each block is explained below.

A. Multiplexer based adder:

Multiplexer based full adder consists of NOT gate and two
4:1 multiplexers as shown in Fig.2. Here inputs are ‗c‘ and
inverted ‗c‘ for a multiplexer that gives sum as the output and
‗0‘,‗c‘ and ‗1‘ for the other multiplexer that gives carry as
output and the selection lines are ‗a‘ and ‗b‘ for the 4:1
multiplexers. Sum and carry are the outputs of the two 4:1
multiplexers.

Fig. 2. Full adder using multiplexers

B. 1-Bit adder/ subtractor:

1-Bit adder/subtractor is designed by using a multiplexer-
based adder and xor gate. Conventional full adder has three
inputs and two outputs such as a, b and cin are respective
inputs and sum, carry are respective outputs same way 1-bit
adder /subtractor exists but the main difference is xor gate is
used to select either adder or subtractor. Here b and cin are
inputs for xor gate and output is taken as one of the inputs for
1-bit adder/subtractor. Here cin is taken as the same as
previous stage carry for a 1-bit adder/subtractor. If input cin is
‗0‘ then adder operation is performed otherwise subtraction is
done as shown in Fig. 3.

Fig. 1. Conventional booth multiplier Fig. 3. 1-Bit Adder/subtractor using multiplexer

C. 9-Bit adder/subtractor: TABLE I. FUNCTIONALITY OF 9-BIT MUX BLOCK.

This 9-Bit adder/subtractor is designed by using nine 1-bit

adder/subtractor blocks cascaded with each other. Here 9-bit Enable Selection
adder/subtractor has three inputs and two outputs such as S.NO
Yi+1 Yi Yi-1
Output
a[8:0], b[8:0], cin are inputs and s[8:0], cout are outputs
respectively. Each 1-bit adder/subtractor output carry/borrow 1 0 0 0 0
is taken as the previous stage carry to the next 1-bit 2 0 0 1 X
adder/subtractor, this process continues up to last 9th block. 3 0 1 0 X
Based on 1st block‘s ‗cin‘ input a 9-bit adder or subtractor is 4 0 1 1 2X
selected as shown in Fig. 4.
5 1 0 0 2X
6 1 0 1 1X
7 1 1 0 1X
8 1 1 1 0

The proposed booth multiplier design looks similar to the

conventional one but the main difference is 9-Bit
adder/subtractor and coders are designed using multiplexers.
Due to this power consumption, area and delay time are
reduced as shown in Fig. 6.
If X=0 then X+Y output is Y and X-Y output is –Y i.e,2‘s
compliment of Y. To achieve this functionality 9-Bit binary to
2‘s complement block is used. Other stages have three blocks
Fig. 4. 9-Bit Adder/subtractor using multiplexer they are the coder, 9-Bit mux block and 9-Bit adder/subtractor,
here 9-Bit adder/subtractor is replaced on 9-Bit 2:1 mux and
D. 9-Bit Mux Block: the coder has three inputs i.e, Yi+1 ,Yi, Yi-1 and two outputs
In this 9-Bit mux block is designed by using two 4:1 i.e.,A0 and A1. WhereA0 is used as selection and enable line
multiplexers with enable line. Here 0, X and 2X are inputs for for 9-Bit 4:1 mux block and other outputA1 as to select
4:1 multiplexers where X is one of the 8-Bit input operand and adder/subtractor. TABLE II. represent the functionality of
2X is obtained by shifting X by one bit left. Yi and Yi-1 are code block using mux. 9-Bit 4:1 mux has four inputs and one
selection lines and Yi+1 is enable line for 4:1 multiplexers as output. Here 0,1*X,1*X and 2*X are inputs where X is 8-bit
shown in Fig.5. These selection lines and enable line are input data and output is selected based on coder output A0.
obtained from code using mux block in proposed model. Every stage has 9-Bit output in that two LSB bits are taken as
Based on enable line either 4:1 multiplexer 1 or 2 is enabled actual product output remaining bits are taken as input for next
and corresponding output is observed by using selection lines stage 9-bit adder/subtractor.
as shown in TABLE I.
TABLE II. FUNCTIONALITY OF CODE BLOCK USING MUX

Outputs
Inputs
A0 A1
S.NO
Yi+1 Yi Yi-1 Enable Selection Adder/subtractor

1 0 0 0 0 0 0 0

2 0 0 1 0 0 1 0

3 0 1 0 0 1 0 0

4 0 1 1 0 1 1 0

5 1 0 0 1 0 0 1

6 1 0 1 1 0 1 1

7 1 1 0 1 1 0 1

8 1 1 1 1 1 1 0

Fig. 5. 9-Bit Mux Block

 9-Bit mux block output is taken as one of the inputs for 9-
Bit adder/subtractor and other input for 9-Bit adder/subtractor
is taken as previous stage output but for initial stage there is
modified due to one of the input data is zero so 9-Bit binary to
2‘s compliment and 9-Bit 2:1 mux is used without 9-Bit
adder/subtractor. Final stage (i.e., n/2 stage) 9-Bit
adder/subtractor output is taken as actual multiplier 9-Bit
MSB output and remaining bits already observed at previous
stages.

IV. RESULTS
The proposed methodology is simulated and synthesized
on Vivado 2017.2 software. The simulated result for 8*8 booth
multiplier using multiplexer is shown in Fig. 7.

Fig. 7. Simulation result for 8*8-Bit booth multiplier using multiplexer

Inputs for 8*8 booth multiplier using multiplexer are

a[7:0], b[7:0] taken as ―00010000‖, ― 00000010‖ respectively
and so obtained output p[15:0] is ―0000000000100000‖.
The proposed booth multiplier and conventional booth
multiplier with and without incrementer are coded in Verilog
and the synthesis is carried out using Xilinx. The synthesis file
consists of the number of LUT‘s, delay and power
consumption of respective designs are mentioned in TABLE
III. The proposed booth multiplier using multiplexer has
significant less delay, area and power consumption compared
to booth multiplier designs are also shown in TABLE III.
TABLE III. RADIX4 BOOTH MULTIPLIERS COMPARISON IN LUT‘S,
DELAY AND POWER

Multiplier No.
S.No Power (Watts) Delay (ns)
Name of
LUT
’s
Booth
Multiplier
1 58 13.698 12.120
conventional

Booth
Multiplier
2 58 12.797 10.266
Proposed
with
multiplexer

Fig. 6. Proposed 8*8-Bit booth multiplier using multiplexer

 A comparison is made between proposed booth multiplier REFERENCES
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with incrementer and the remaining three multipliers listed as Encoded Multi-Modulus Multipliers‖, IEEE Trans on Circuits And System, vol.
S.No 1 to 3 in TABLE III. The comparison results are 60(11), Nov 2013.
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incrementer design offers saving of 3.57% of LUT‘s ,1.44% of and Multiplier-Accumulator Unit‖, International Journal of Emerging
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1 CONVENTIOANL 3.57 0.73 1.04

BOOTH MULTIPLIER
2 PROPOSED 3.57 1.44 2.22

V. CONCLUSION
Design of high performance and power potent booth
multiplier using multiplexer is carried out in this paper.
From the results it can be concluded that the proposed
booth multiplier shows better results when compared to
conventional booth multiplier. In this proposed design, the
novelty is that a new design is incorporated for the 9-Bit
Mux Block, code Block and adder/subtractor Block.
Because of this new design it can be concluded that the
proposed booth multiplier is power efficient and fast
enough. Thus, the proposed booth multiplier is appropriate
for high speed Digital Signal Processing and graphics
applications.