Chapter 3

Top Level View of Computer Function and

Interconnection
 Contemporary computer designs are based on
concepts developed by John von Neumann at the
Institute for Advanced Studies, Princeton.
 Such a design is referred to as the Neumann
architecture and is based on three key concepts:
◦ Data and instructions are stored in a single read–write
memory.
◦ The contents of this memory are addressable by
location, without regard to the type of data contained
there.
◦ Execution occurs in a sequential fashion (unless
explicitly modified) from one instruction to the next.
 Hardwired systems are inflexible
 General purpose hardware can do different
tasks, given correct control signals
 Instead of re-wiring, supply a new set of
control signals
 Several other components are needed to yield
a functioning computer.
 Data and instructions must be put into the
system. For this we need some sort of input
module.
 This module contains basic components for
accepting data and instructions in some form
and converting them into an internal form of
signals usable by the system.
 A program is not always executed
sequentially; it may jump around.
 Similarly, operations on data may require
access to more than just one element at a
time in a predetermined sequence.
 Thus, there must be a place to store
temporarily both instructions and data.
 A sequence of steps
 For each step, an arithmetic or logical
operation is done
 For each operation, a different set of control
signals is needed
 For each operation a unique code is provided
◦ e.g. ADD, MOVE
 A hardware segment accepts the code and
issues the control signals
convenient to organize memory
using 16-bit words.
The instruction format provides
4 bits for the opcode, so that there
can be as many as 2^4 =16
different opcodes,
up to 2^12 =4096 (4K) words of
memory can be directly addressed
 Two steps:
◦ Fetch
◦ Execute
 Program Counter (PC) holds address of next
instruction to fetch
 Processor fetches instruction from memory
location pointed to by PC
 Increment PC
◦ Unless told otherwise
 Instruction loaded into Instruction Register
(IR)
 Processor interprets instruction and performs
required actions
 Processor-memory
◦ data transfer between CPU and main memory
 Processor I/O
◦ Data transfer between CPU and I/O module
 Data processing
◦ Some arithmetic or logical operation on data
 Control
◦ Alteration of sequence of operations
◦ e.g. jump
 Combination of above
 ADD B,A, that stores the sum of the contents of
memory locations B and A into memory location A.

 A single instruction cycle with the following steps

occurs:
◦ • Fetch the ADD instruction.
◦ • Read the contents of memory location A into the
processor.
◦ • Read the contents of memory location B into the
processor. In order that the contents of A are not lost, the
processor must have at least two registers for storing
memory values, rather than a single accumulator.
◦ • Add the two values.
◦ • Write the result from the processor to memory location A.
 Mechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processing
 Program
◦ e.g. overflow, division by zero
 Timer
◦ Generated by internal processor timer
◦ Used in pre-emptive multi-tasking
 I/O
◦ from I/O controller
 Hardware failure
◦ e.g. memory parity error
 Added to instruction cycle
 Processor checks for interrupt
◦ Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
◦ Suspend execution of current program
◦ Save context
◦ Set PC to start address of interrupt handler routine
◦ Process interrupt
◦ Restore context and continue interrupted program
 Disable interrupts
◦ Processor will ignore further interrupts whilst
processing one interrupt
◦ Interrupts remain pending and are checked after
first interrupt has been processed
◦ Interrupts handled in sequence as they occur
 Define priorities
◦ Low priority interrupts can be interrupted by higher
priority interrupts
◦ When higher priority interrupt has been processed,
processor returns to previous interrupt
 All the units must be connected
 Different type of connection for different type
of unit
◦ Memory
◦ Input/Output
◦ CPU
 Receives and sends data
 Receives addresses (of locations)
 Receives control signals
◦ Read
◦ Write
◦ Time
 Similar to memory from computer’s viewpoint
 Output
◦ Receive data from computer
◦ Send data to peripheral
 Input
◦ Receive data from peripheral
◦ Send data to computer
 Receive control signals from computer
 Send control signals to peripherals
◦ e.g. spin disk
 Receive addresses from computer
◦ e.g. port number to identify peripheral
 Send interrupt signals (control)
 Reads instruction and data
 Writes out data (after processing)
 Sends control signals to other units
 Receives (& acts on) interrupts
 There are a number of possible
interconnection systems
 Single and multiple BUS structures are most
common
 e.g. Control/Address/Data bus (PC)
 e.g. Unibus (DEC-PDP)
 A communication pathway connecting two or
more devices
 Usually broadcast
 Often grouped
◦ A number of channels in one bus
◦ e.g. 32 bit data bus is 32 separate single bit
channels
 Power lines may not be shown
 Carries data
◦ Remember that there is no difference between
“data” and “instruction” at this level
 Width is a key determinant of performance
◦ 8, 16, 32, 64 bit
 Identify the source or destination of data
 e.g. CPU needs to read an instruction (data)
from a given location in memory
 Bus width determines maximum memory
capacity of system
◦ e.g. 8080 has 16 bit address bus giving 64k
address space
 Control and timing information
◦ Memory read/write signal
◦ Interrupt request
◦ Clock signals
 Dedicated
◦ Separate data & address lines
 Multiplexed
◦ Shared lines
◦ Address valid or data valid control line
 time multiplexing
◦ Advantage - fewer lines
◦ Disadvantages
 More complex control
 Ultimate performance
 Lots of devices on one bus leads to:
◦ Propagation delays
 Long data paths mean that coordination of bus use can
adversely affect performance
 If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to overcome
these problems
 More than one module controlling the bus
◦ e.g. CPU and IO controller
 Only one module may control bus at one time
 Arbitration may be centralised or distributed
 Centralised
◦ Single hardware device controlling bus access
 Bus Controller
 Arbiter
◦ May be part of CPU or separate
 Distributed
◦ Each module may claim the bus
◦ Control logic on all modules
◦ Master and slave
 Co-ordination of events on bus
 Synchronous
◦ Events determined by clock signals
◦ Control Bus includes clock line
◦ A single 1-0 is a bus cycle
◦ All devices can read clock line
◦ Usually sync on leading edge
◦ Usually a single cycle for an event
 Peripheral Component Interconnection
 Introduced by Intel in 1992
 Revised twice into version 2.1 which is the 64-bit
standard that it is today.
 Great feature of PCI Bus was that it was invented as
an industry standard
 The current standard allows the use of up to 64 data
lines at 66 MHz, for a raw transfer rate of 528
MByte/s, or 1.224 Gbps.
◦ But it is not just a high speed that makes PCI attractive.
◦ PCI is specifically designed to meet economically the I/O
requirements of modern systems; it requires very few chips
to implement and supports other buses attached to the PCI
bus.
 PCI provides direct access to system
memory for the devices that are connected
to the bus which is then connected through
a bridge that connects to the front side bus.
 This configuration allowed for higher
performance without slowing down the
processor

52
•The PCI Bus was
originally 33Mhz and
then changed to
66Mhz.
•PCI Bus became big
with the release of
Windows 95 with
“Plug and Play”
technology
•“Plug and Play”
utilized the PCI bus
concept.
53
 Bus Bus Speed MB/sec Advantages Disadvantages
Bus Type Width

ISA 16 bits 8MHz 16 MBps low cost, low speed, Jumpers

compatibility, & DIP switches.
widely used becoming obsolete

PCI 64 bits 133 MHz 1 GBps very high speed, incompatible with
Plug & Play, older systems,
dominant board- can cost more
level bus
CompactPCI 64 bits 33MHz 132 MBps designed for lower speed than
industrial use, hot PCI, need adapter for
swapping/Plug & PC use, incompatible
Play, ideal for with older systems
embedded
systems

Table 1: How PCI compares to other buses (Tyson, 2004a; Quatech, 2004c)
56
 Requirements for  Tasks it
full automates:
implementation: ◦ Interrupt Requests
(IRQ)
◦ Plug and Play BIOS
◦ Direct Memory
◦ Extended System Access (DMA)
Configuration Data ◦ Memory Addresses
(ESCD) ◦ Input/Output (I/O)
◦ Plug and Play Configuration
operating system
(Tyson, 2004b)

57
 In a typical system, the firmware (or operating
system) queries all PCI buses at startup time (via
PCI Configuration Space) to find out what devices
are present and what system resources (memory
space, I/O space, interrupt lines, etc.) each
needs.
 It then allocates the resources and tells each
device what its allocation is.
 The PCI configuration space also contains a small
amount of device type information, which helps
an operating system choose device drivers for it,
or at least to have a dialogue with a user about
the system configuration.
 Systems lines
◦ Including clock and reset
 Address & Data
◦ 32 time mux lines for address/data
◦ Interrupt & validate lines
 Interface Control
 Arbitration
◦ Not shared
◦ Direct connection to PCI bus arbiter
 Error lines
 Interrupt lines
◦ Not shared
 Cache support
 64-bit Bus Extension
◦ Additional 32 lines
◦ Time multiplexed
◦ 2 lines to enable devices to agree to use 64-bit
transfer
 JTAG/Boundary Scan
◦ For testing procedures These signal lines support
testing procedures defined in IEEE Standard 1149.1.
 Transaction between initiator (master) and
target
 Master claims bus
 Determine type of transaction
◦ e.g. I/O read/write
 Address phase
 One or more data phases
 Stallings, chapter 3 (all of it)
 www.pcguide.com/ref/mbsys/buses/

 In fact, read the whole site!

 www.pcguide.com/