1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev,

& Flow Dev, Verification services. Turnkey Projects

(http://www.signo semi.com/)
a

LEF, DEF & LIB

by signo -scribe (http://www.signo semi.com/author/signo -scribe/) | Nov 2,
2017 | Random-Blogs (http://www.signo semi.com/category/random-blogs-2/) | 4
comments (http://www.signo semi.com/lef-def-lib/#respond)

 Blog Views: 38,574

Author: Ashish Kumar Sharma (https://www.linkedin.com/in/ashish-kumar-sharma-
341a786b/), Physical Design Engineer, Signo Semiconductors
(http://www.signo semi.com/)

Library Exchange Format (LEF)

The LEF le is the abstract view of cells. It only gives the idea about PR boundary,
pin position and metal layer information of a cell. To get the complete information
about the cell, DEF (Design Exchange Format) le is required. In this 3 sections are
de ned, i.e. technology, site, macros. In the technology part layers, design rules, via
de nitions and metal capacitance are de ned. In the site, site extension is de ned
and in the macros the information about cell description, dimension, layout of pins
and blockages and capacitance are de ned.

For every technology the layer and the via statements are di erent. So for the layer
and via, the type of the layer (layer may be routing type, master slice or overlap),
width/pitch and spacing, direction, resistance, capacitance, and antenna factor are
de ned.

Unit De nition 
UNITS

DATABASE MICRONS 1000 ;

END UNITS

www.signoffsemi.com/lef-def-lib/ 1/9
1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects

Values de ned in le will be multiplied with UNITS. For example, if spacing is

de ned as 0.6, then the actual value will be 600bd (0.6 * 1000).

Manufacturing grid

MANUFACTURING GRID 0.1 ;

This is de ned for the geometry alignment, once it is speci ed, then the cells are
placed in location which is aligned to the manufacturing grid.

Implant Layer de nition

This syntax de nes the Implant layer in the design. For each layer, name, space and
width are de ned. Space and width are the factors that a ect the legal cell
placement.

Masterslice or Overlap Layer de nition

LAYER layerName

TYPE{MASTERSLICE| OVERLAP} ;

This de nes the masterslice (non routing) or overlap layers in the design. Master
slice layers are basically polysilicon layers.Whenever the pins of MACROS are
present on Polysilicon these layers are used.

VIA

for signal routers the VIA statement de nes via’s. By default via is using three
layers

1. cut layers.

2. Routing

3. Masterslice.

The routing and the master slice layers touch the cut layers.

Via Rule Generator

In order to generate the via arrays, via rule generator de nes the formulas.VIARULE
GENERATE statement can be used to de ne the special wiring which is explicitly
not de ned in VIARULE statement.

Same-Net Spacing

This rule determines the minimum spacing between geometries in the same net, it
is only de ned if the same-net spacing is less than the di erent net spacing.

SITE

www.signoffsemi.com/lef-def-lib/ 2/9
1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects

Site speci es the region of the block like PAD and CORE, under this syntax,
symmetry is also de ned w.r.t. X, Y or R90 (Rotate by 90°).

Macro (Attributes of Macros are de ned)

This syntax de nes the detail about Macros like name, PAD detail, class size,
location of endcap cells (like topright, bottom etc.) symmetry, site name,
obstruction detail.

Macro Pin Statement

De nes the pins for the Macros. For each macro, Pin statements are required (all
I/O pins, VDD , VSS).

Following list of pins are required

Power and ground pins

Input and Output Pins, inout and netlist pins.
Must Join pins

MustJoin pin

This speci es the name of the pins to be connected together.

Macro Obstruction statement

The OBS de nes the group of obstruction on macros, normally this blocks the
routing but in case of obstruction on pin it allows the routing.

DEF (Design Exchange Format)

The DEF le basically contains the placement information of macros , standard

cells, I/O pins and other physical entities. The logical design data to place and route
tool and takes the physical design data from place and route tool in form of DEF.
The logical design data contains the internal connectivity, grouping information,
and physical constraints and the physical design data contains routing geometry
data, placement location and orientation. DEF is used as an input for various
stages.Floorplan DEF is given at the import design stage to provide information
about macro location, IO ports and block shape, SCANDEF is given at the import
design stage for scan chain reordering which contains the connectivity information
of scan ops and it is also an input of scan tracing stage, DEF generated by PnR is
used in Star RC extraction.

In detail it contains:

Die Area
Tracks
Components (macros)
www.signoffsemi.com/lef-def-lib/ 3/9
1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects

I/O Pins
Nets
Blockages
Halo
Scan Chain
Vias
Slots
Fills
Region
Row
Metal layers

Liberty Timing File (LIB)

.lib is basically a timing model contains cell delays, transition, setup and hold time
requirements. CCS and NLDM techniques are used to generate .lib les. In CCS
(composite current source) current source is used for driver modeling, CCS has 20
variables to account input slew and output load data where as, NLDM uses the
voltage source for driver modeling and it has only 2 variables which are not
su cient for modeling the nonlinearity of any circuit. So CCS is more accurate than
NLDM. Because of the di erence in number of variables used in both the models,
size of CCS le is 10X times larger than the NLDM le. Also the run time for CCS is
more when compared to NLDM.

The design needs to be tested for certain PVT (process voltage and temperature)
corners. But for every PVT corner, the timing of the cells are di erent. Hence there
is a .lib le for every PVT corner.

In .lib le following unit attributes are present

Time unit
Voltage unit
Current unit
Leakage power unit
Capacitive load unit
Slew rate : Lower and upper limit values are de ned in terms of percentage for
both rise and fall time
Input threshold at rise and fall time
Output threshold for rise and fall time

Look Up table templates are de ned for di erent parameters like delay, hold,
passive energy, recovery, removal, setup, with di erent matrix.

For each cell (AND, NAND, Or etc..) following attributes are de ned:

www.signoffsemi.com/lef-def-lib/ 4/9
1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects

Area of cell
Leakage power
Capacitance
Rise and fall capacitance
Properties such as capacitance, direction of the pin etc. for each pin (input and
output) will be de ned. Further di erent values are characterised in matrix form,
as shown in the below example.

fall_transition(delay_template_5x5) {

index_1 (“0.015, 0.04, 0.08, 0.2, 0.4”);

index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“0.0606, 0.0624, 0.0744, 0.0768, 0.09”, \

“0.1146, 0.1152, 0.1164, 0.1212, 0.1314”, \

“0.201, 0.2004, 0.2052, 0.2058, 0.2148”, \

“0.48, 0.4806, 0.4812, 0.4824, 0.4866”, \

“0.9504, 0.9504, 0.9504, 0.951, 0.9534”);

Output fall transition is characterized based on output capacitance and input

transition. Index_1 represents output capacitance and index_2 represents input
transition . In the above example, 5 values are speci ed in each indexes, if a given
value is not there in the list then we calculate fall transition by intrapolation or
extrapolation. If the value is in between the given values of an index we go for
intrapolation or else we go for extrapolation.

Like “fall transition” other parameter also calculated which are as follows:

Rise transition
Internal Power
Fall power
Rise power
Cell fall
Cell rise

Below an another example of D ip op characterization table is given, which

shows the hold falling, and setup falling is also de ned in addition to the above
attributes. Index_1 is corresponds to related pin transition and index_2 corresponds
to constrained pin transition.

timing_type : hold_falling;

www.signoffsemi.com/lef-def-lib/ 5/9
1/29/2020 LEF, DEF & LIB - Physical design, STA & Synthesis, DFT, Automation & Flow Dev, Verification services. Turnkey Projects

rise_constraint(hold_template_3x5) {

index_1 (“0.06, 0.3, 0.6”);

index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“-0.09375, -0.0875, -0.075, -0.1125, -0.175”, \

“-0.2, -0.19375, -0.18125, -0.21875, -0.1875”, \

“-0.16875, -0.25625, -0.24375, -0.28125, -0.25”);

timing_type : setup_falling;

rise_constraint(setup_template_3x5) {

index_1 (“0.06, 0.3, 0.6”);

index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“0.28125, 0.275, 0.2625, 0.3, 0.3625”, \

“0.29375, 0.2875, 0.36875, 0.3125, 0.375”, \

“0.35625, 0.35, 0.3375, 0.375, 0.4375”);

4 Comments
SARAVANAKUMAR A on April 13, 2018 at 11:12 AM
Good explanation, i cannot anywhere in other website

Reply

Signo -Scribe
(http://www.signo semi.com/user/signo -scribe/)
on April 13, 2018 at 11:55 AM

Thanks.

Reply
www.signoffsemi.com/lef-def-lib/ 6/9