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TMS320F28379S, TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C – AUGUST 2014 – REVISED MAY 2016
TMS320F2837xS Delfino™ Microcontrollers

1 Device Overview
1.1
1
Features
• TMS320C28x 32-Bit CPU – Four Serial Communications Interfaces
– 200 MHz (SCI/UART) (Pin-Bootable)
– IEEE 754 Single-Precision Floating-Point Unit – Two I2C Interfaces (Pin-Bootable)
(FPU) • Analog Subsystem
– Trigonometric Math Unit (TMU) – Up to Four Analog-to-Digital Converters (ADCs)
– Viterbi/Complex Math Unit (VCU-II) • 16-Bit Mode
• Programmable Control Law Accelerator (CLA) – 1.1 MSPS Each (up to 4.4-MSPS System
– 200 MHz Throughput)
– IEEE 754 Single-Precision Floating-Point – Differential Inputs
Instructions – Up to 12 External Channels
– Executes Code Independently of Main CPU • 12-Bit Mode
• On-Chip Memory – 3.5 MSPS Each (up to 14-MSPS System
– 512KB (256KW) or 1MB (512KW) of Flash Throughput)
(ECC-Protected) – Single-Ended Inputs
– 132KB (66KW) or 164KB (82KW) of RAM – Up to 24 External Channels
(ECC-Protected or Parity-Protected) • Single Sample-and-Hold (S/H) on Each ADC
– Dual-Zone Security Supporting Third-Party • Hardware-Integrated Post-Processing of
Development ADC Conversions
• Clock and System Control – Saturating Offset Calibration
– Two Internal Zero-Pin 10-MHz Oscillators – Error From Setpoint Calculation
– On-Chip Crystal Oscillator – High, Low, and Zero-Crossing Compare,
– Windowed Watchdog Timer Module With Interrupt Capability
– Missing Clock Detection Circuitry – Trigger-to-Sample Delay Capture
• 1.2-V Core, 3.3-V I/O Design – Eight Windowed Comparators With 12-Bit
• System Peripherals Digital-to-Analog Converter (DAC) References
– Two External Memory Interfaces (EMIFs) With – Three 12-Bit Buffered DAC Outputs
ASRAM and SDRAM Support • Enhanced Control Peripherals
– 6-Channel Direct Memory Access (DMA) – 24 PWM Channels With Enhanced Features
Controller – 16 High-Resolution Pulse Width Modulator
– Up to 169 Individually Programmable, (HRPWM) Channels
Multiplexed General-Purpose Input/Output • High Resolution on Both A and B Channels
(GPIO) Pins With Input Filtering of 8 PWM Modules
– Expanded Peripheral Interrupt Controller (ePIE) • Dead-Band Support (on Both Standard and
– Multiple Low-Power Mode (LPM) Support With High Resolution)
External Wakeup – Six Enhanced Capture (eCAP) Modules
• Communications Peripherals – Three Enhanced Quadrature Encoder Pulse
– USB 2.0 (MAC + PHY) (eQEP) Modules
– Support for 12-Pin 3.3 V-Compatible Universal – Eight Sigma-Delta Filter Module (SDFM) Input
Parallel Port (uPP) Interface Channels, 2 Parallel Filters per Channel
– Two Controller Area Network (CAN) Modules • Standard SDFM Data Filtering
(Pin-Bootable) • Comparator Filter for Fast Action for Out of
– Three High-Speed (up to 50-MHz) SPI Ports Range
(Pin-Bootable)
– Two Multichannel Buffered Serial Ports
(McBSPs)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28379S, TMS320F28377S
SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com
• Package Options: • Temperature Options:

– Lead-Free, Green Packaging – T: –40ºC to 105ºC Junction
– 337-Ball New Fine Pitch Ball Grid Array – S: –40ºC to 125ºC Junction
(nFBGA) [ZWT Suffix] – Q: –40ºC to 125ºC Free-Air
– 176-Pin PowerPAD™ Thermally Enhanced Low- (Q100 Qualification for Automotive Applications)
Profile Quad Flatpack (HLQFP)
[PTP Suffix]
– 100-Pin PowerPAD Thermally Enhanced Thin
Quad Flatpack (HTQFP) [PZP Suffix]
1.2 Applications
• Industrial Drives • Smart Metering
• Solar Micro Inverters and Converters • Automotive Transportation
• Radar • Power Line Communications
• Digital Power
1.3 Description
The Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for
advanced closed-loop control applications such as industrial drives and servo motor control; solar
inverters and converters; digital power; transportation; and power line communications. Complete
development packages for digital power and industrial drives are available as part of the powerSUITE and
DesignDRIVE initiatives.
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz
of signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which
enables fast execution of algorithms with trigonometric operations common in transforms and torque loop
calculations; and the VCU accelerator, which reduces the time for complex math operations common in
encoded applications.
The F2837xS microcontroller family features a CLA real-time control co-processor. The CLA is an
independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA
responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel
processing capability can effectively double the computational performance of a real-time control system.
By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such
as communications and diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code
(ECC) and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for
code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable
system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple
analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM)
works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The
Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when
current limit conditions are exceeded or not met. Other analog and control peripherals include DACs,
PWMs, eCAPs, eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO11898-1/CAN 2.0B-compliant), and a new uPP interface
extend the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs and
supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly,
a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their
application.
2 Device Overview Copyright © 2014–2016, Texas Instruments Incorporated

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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
TMS320F28379S, TMS320F28377S
www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016
Device Information (1)

PART NUMBER PACKAGE BODY SIZE
TMS320F28379SZWT nFBGA (337) 16.0 mm × 16.0 mm
TMS320F28379SPTP HLQFP (176) 24.0 mm × 24.0 mm
TMS320F28379SPZP HTQFP (100) 14.0 mm × 14.0 mm
(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable
Information.
Copyright © 2014–2016, Texas Instruments Incorporated Device Overview 3

TMS320F28379S, TMS320F28377S
1.4 Functional Block Diagram

Figure 1-1 shows the CPU system and associated peripherals.
MEMCPU1
CPU1.CLA1 to CPU1 Low-Power

CPU1.CLA1 C28 CPU-1 User-Configurable Mode Control
GPIO MUX
128x16 MSG RAM
CPU1 to CPU1.CLA1 DCSM
FPU PSWD
OTP
128x16 MSG RAM VCU-II Dual 1K x 16
TMU Code
Security (F28377S, F23875S only)
Module Flash Bank 0 Flash Bank 1
Watchdog INTOSC1
CPU1 Local Shared + 256K x 16
256K x 16
6x 2Kx16 Emulation Secure
Secure Memories Code
Secure
LS0-LS5 RAMs
shown in Red Security PUMP
Logic
CPU1.D0 RAM 2Kx16 (ECSL)
(F28377S, F28375S only)
Flash Wrapper for Main PLL INTOSC2
CPU1.D1 RAM 2Kx16 WD Timer Flash Wrapper for
Bank 0
NMI-WDT Bank 1
CPU Timer 0 External Crystal or

CPU1.M0 RAM 1Kx16 Oscillator
CPU Timer 1
A5:0 16-/12-bit ADC CPU Timer 2
A CPU1.M1 RAM 1Kx16
x4 Aux PLL
B5:0 B ePIE Global Shared AUXCLKIN
C (up to 192 16x 4Kx16
ADC
C5:2 Analog D Result
Secure-ROM 32Kx16 interrupts) GS0-GS15 RAMs
Secure TRST
MUX Config Regs
Boot-ROM 32Kx16
CPU1.CLA1 Bus
D5:0 Nonsecure TCK
JTAG TDI
ADCIN14
Data Bus TMS
ADCIN15 Bridge CPU1.CLA1 Data ROM CPU1.DMA
(4Kx16) TDO
Comparator
DAC CPU1 Buses
Subsystem
(CMPSS) x3
Data Bus Data Bus Data Bus Data Bus Data Bus
Peripheral Frame 1 Data Bus Bridge Bridge Bridge Peripheral Frame 2 Bridge Bridge Bridge
ePWM-1/../12 SCI- USB CAN- SPI- RAM

eCAP- I2C-A/B
1/../6
eQEP-1/2/3 SDFM-1/2 A/B/C/D Ctrl / A/B A/B/C McBSP-A/B uPP EMIF1 EMIF2 GPIO
(16L FIFO)
HRPWM-1/../8 (16L FIFO) PHY (32-MBOX) (16L FIFO)
EXTSYNCOUT
UPPAD[7:0]
EPWMxB
EPWMxA
SCITXDx
CANTXx
SPISIMOx
SPISOMIx
UPPACLK
EM1CTLx
EM2CTLx
SPICLKx
MCLKRx
SPISTEx
MCLKXx
UPPAWT
EQEPxS
UPPAEN
EXTSYNCIN
UPPAST
USBDM
SDx_Dy
SDx_Cy
EQEPxI
MDXx
USBDP
MFSRx
SCIRXDx
MFSXx
EM1Dx
EM1Ax
EM2Dx
EM2Ax
CANRXx
GPIOn
EQEPxB
ECAPx
EQEPxA
TZ1-TZ6
MRXx
SDAx
SCLx
GPIO MUX, Input X-BAR, Output X-BAR
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram
4 Device Overview Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
Table of Contents
1 Device Overview ......................................... 1 6.3 Memory ............................................ 178
1.1 Features .............................................. 1 6.4 Identification........................................ 186
1.2 Applications ........................................... 2 6.5 Bus Architecture – Peripheral Connectivity ........ 187
1.3 Description ............................................ 2 6.6 C28x Processor .................................... 188
1.4 Functional Block Diagram ........................... 4 6.7 Control Law Accelerator ........................... 190
2 Revision History ......................................... 6 6.8 Direct Memory Access ............................. 191
3 Device Comparison ..................................... 7 6.9 Boot ROM and Peripheral Booting................. 193
3.1 Related Products ..................................... 9 6.10 Dual Code Security Module ....................... 196
4 Terminal Configuration and Functions ............ 10 6.11 Timers .............................................. 196
4.1 Pin Diagrams ........................................ 10 6.12 Nonmaskable Interrupt With Watchdog Timer
4.2 Signal Descriptions .................................. 16 (NMIWD) ........................................... 196
4.3 Pins With Internal Pullup and Pulldown ............. 38 6.13 Watchdog.......................................... 197
4.4 Connections for Unused Pins ....................... 39 6.14 Configurable Logic Block (CLB) ................... 197
4.5 Pin Multiplexing...................................... 40 7 Applications, Implementation, and Layout ...... 198
5 Specifications ........................................... 47 7.1 TI Design or Reference Design .................... 198
5.1 Absolute Maximum Ratings ........................ 47 8 Device and Documentation Support .............. 199
8.1 Device and Development Support Tool
5.2 ESD Ratings ........................................ 47
Nomenclature ...................................... 199
5.3 Recommended Operating Conditions ............... 48
8.2 Tools and Software ................................ 200
5.4 Power Consumption Summary ...................... 49
8.3 Documentation Support ............................ 202
5.5 Electrical Characteristics ............................ 53
8.4 Related Links ...................................... 203
5.6 Thermal Resistance Characteristics ................ 54
8.5 Community Resources............................. 203
5.7 System .............................................. 56
8.6 Trademarks ........................................ 203
5.8 Analog Peripherals .................................. 92
8.7 Electrostatic Discharge Caution ................... 203
5.9 Control Peripherals ................................ 117
8.8 Glossary............................................ 203
5.10 Communications Peripherals ...................... 134
9 Mechanical Packaging and Orderable
6 Detailed Description.................................. 176 Information ............................................. 204
6.1 Overview ........................................... 176 9.1 Packaging Information ............................. 204
6.2 Functional Block Diagram ......................... 176
Copyright © 2014–2016, Texas Instruments Incorporated Table of Contents 5

TMS320F28379S, TMS320F28377S
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from October 22, 2015 to May 6, 2016 (from B Revision (October 2015) to C Revision) Page
• Global: Restructured document. ................................................................................................... 1

• Section 1.3 (Description): Removed paragraph about Configurable Logic Block (CLB). ................................... 2
• Table 3-1 (Device Comparison): TMS320F28375SPZP is available in the Q temperature range. ....................... 7
• Section 3.1 (Related Products): Added section. ................................................................................. 9
• Table 4-1 (Signal Descriptions): Updated DESCRIPTION of VREFHIA, VREFHIB, VREFHIC, VREFHID, and VDDA. ............ 16
• Figure 5-7 (Clocking System): Changed figure title from "Device Clocking" to "Clocking System." ..................... 60
• Table 5-19 (Flash Wait States): Changed title from "Minimum Required Flash Wait States at Different
Frequencies" to "Flash Wait States." Updated table. ........................................................................... 66
• Section 5.7.5.1 (JTAG Electrical Data and Timing): Added section. ........................................................ 70
• Table 5-39 (EMIF Asynchronous Memory Timing Requirements): Parameter 14 [tsu(EMOEL-EMWAIT)]: Changed MIN
value from 4E to 4E+20............................................................................................................. 85
• Table 5-39: Parameter 28 [tsu(EMWEL-EMWAIT)]: Changed MIN value from 4E to 4E+20. ..................................... 85
• Table 5-40 (EMIF Asynchronous Memory Switching Characteristics): Parameter 11 [td(EMWAITH-EMOEH)]: Changed
MIN value from 3E+8 to 4E+10. Changed MAX value from 4E+10 to 5E+15. .............................................. 85
• Table 5-40: Parameter 25 [td(EMWAITH-EMWEH)]: Changed MIN value from 3E+8 to 4E+10. Changed MAX value
from 4E+10 to 5E+15. .............................................................................................................. 85
• Section 5.9.4 (High-Resolution Pulse Width Modulator (HRPWM)): Removed NOTE about dual-edge high-
resolution being enabled. ........................................................................................................ 129
• Figure 5-67 (SPI CPU Interface): Changed figure title from "SPI" to "SPI CPU Interface." ............................. 151
• Table 5-80 (SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3): Parameter 2
[tw(SPCH)M, clock polarity = 0]: Updated MIN value and MAX value. ......................................................... 154
• Table 5-80: Parameter 3 [tw(SPCL)M, clock polarity = 0]: Updated MIN value and MAX value. ........................... 154
• Table 5-82 (SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3): Parameter 2
[tw(SPCL)M, clock polarity = 1]: Updated MIN value and MAX value. ......................................................... 157
• Table 5-82: Parameter 3 [tw(SPCH)M, clock polarity = 1]: Updated MIN value and MAX value. .......................... 157
• Table 5-86 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3):
Parameter 2 [tw(SPCH)M, clock polarity = 0]: Updated MIN value and MAX value. ......................................... 162
• Table 5-86: Parameter 3 [tw(SPCL)M, clock polarity = 0]: Updated MIN value and MAX value. ........................... 162
• Table 5-88 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3):
Parameter 2 [tw(SPCL)M, clock polarity = 1]: Updated MIN value and MAX value. ......................................... 165
• Table 5-88: Parameter 3 [tw(SPCH)M, clock polarity = 1]: Updated MIN value and MAX value. .......................... 165
• Section 6.1 (Overview): Removed paragraph about Configurable Logic Block (CLB). .................................. 176
• Table 6-5 (Peripheral Registers Memory Map): Added PROTECTED column and associated footnote. ............. 181
• Table 6-8 (Device Identification Registers): Added UID_UNIQUE. ........................................................ 186
• Section 6.14 (Configurable Logic Block (CLB)): Updated section. ......................................................... 197
• Section 7.1 (TI Design or Reference Design): Added section. .............................................................. 198
• Section 8 (Device and Documentation Support): Updated and restructured section. ................................... 199
• Section 8.2 (Tools and Software): Added section. ........................................................................... 200
• Section 8.3 (Documentation Support): Updated section. .................................................................... 202
• Section 9.1 (Packaging Information): Updated section. ...................................................................... 204
6 Revision History Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
3 Device Comparison
Table 3-1 lists the features of each 2837xS device.
Table 3-1. Device Comparison
FEATURE(1) 28379S 28377S 28376S 28375S 28374S
Package Type
337- 176- 100- 337- 176- 100- 337- 176- 100- 337- 176- 100- 337- 176- 100-
(ZWT is an nFBGA package.
Ball Pin Pin Ball Pin Pin Ball Pin Pin Ball Pin Pin Ball Pin Pin
PTP is an HLQFP package.
ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP
PZP is an HTQFP package.)
Processor and Accelerators
Number 1
Frequency (MHz) 200
C28x Floating-Point Unit (FPU) Yes
VCU-II Yes
TMU – Type 0 Yes
Number 1
CLA – Type 1
Frequency (MHz) 200
6-Channel DMA – Type 0 1
Memory
Flash (16-bit words) 1MB (512KW) 1MB (512KW) 512KB (256KW) 1MB (512KW) 512KB (256KW)
Dedicated and Local
36KB (18KW)
Shared RAM
RAM
(16-bit words) Global Shared RAM 128KB (64KW) 128KB (64KW) 96KB (48KW) 128KB (64KW) 96KB (48KW)
Total RAM 164KB (82KW) 164KB (82KW) 132KB (66KW) 164KB (82KW) 132KB (66KW)
Code security for on-chip flash, RAM, and
Yes
OTP blocks
Boot ROM Yes
System
Configurable Logic Block (CLB) Yes No
32-bit CPU timers 3
Watchdog timers 1
Nonmaskable Interrupt Watchdog (NMIWD)
1
timers
Crystal oscillator/External clock input 1
0-pin internal oscillator 2
I/O pins (shared) GPIO 169 97 41 169 97 41 169 97 41 169 97 41 169 97 41
External interrupts 5
EMIF1 (16-bit or 32-bit) 1 – 1 – 1 – 1 – 1 –
EMIF
EMIF2 (16-bit) 1 – – 1 – – 1 – – 1 – – 1 – –
Analog Peripherals
MSPS 1.1 –
Conversion Time (ns)(2) 915 –

ADC 16-bit mode
Input pins 24 20 14 24 20 14 24 20 14 –
Channels (differential) 12 9 7 12 9 7 12 9 7 –
MSPS 3.5
Conversion Time (ns)(2) 290

ADC 12-bit mode
Input pins 24 20 14 24 20 14 24 20 14 24 20 14 24 20 14
Channels
24 20 14 24 20 14 24 20 14 24 20 14 24 20 14
(single-ended)
Number of 16-bit or 12-bit ADCs 4 2 4 2 4 2 –
Number of 12-bit only ADCs – 4 2 4 2
Temperature sensor 1
CMPSS (each CMPSS has two comparators
8 4 8 4 8 4 8 4 8 4
and two internal DACs)
Buffered DAC 3
Copyright © 2014–2016, Texas Instruments Incorporated Device Comparison 7

TMS320F28379S, TMS320F28377S
Table 3-1. Device Comparison (continued)

FEATURE(1) 28379S 28377S 28376S 28375S 28374S
Package Type
337- 176- 100- 337- 176- 100- 337- 176- 100- 337- 176- 100- 337- 176- 100-
(ZWT is an nFBGA package.
Ball Pin Pin Ball Pin Pin Ball Pin Pin Ball Pin Pin Ball Pin Pin
PTP is an HLQFP package.
ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP ZWT PTP PZP
PZP is an HTQFP package.)
Control Peripherals(3)
eCAP inputs – Type 0 6
Enhanced Pulse Width Modulator (ePWM)
24 15 24 15 24 15 24 15 24 15
channels – Type 4
eQEP modules – Type 0 3 2 3 2 3 2 3 2 3 2
High-resolution ePWM channels – Type 4 16 9 16 9 16 9 16 9 16 9
SDFM channels – Type 0 8 6 8 6 8 6 8 6 8 6
(3)
Communication Peripherals
Controller Area Network (CAN) – Type 0(4) 2
Inter-Integrated Circuit (I2C) – Type 0 2
Multichannel Buffered Serial Port (McBSP) –

2
Type 1
Serial Communications Interface (SCI) –
4 3 4 3 4 3 4 3 4 3
Type 0
Serial Peripheral Interface (SPI) – Type 2 3
Universal Serial Bus (USB) – Type 0 1
uPP – Type 0 1
Temperature and Qualification
T: –40°C to 105°C Yes
Junction S: –40°C to 125°C Yes
Temperature (TJ)
Q: –40°C to 150°C(5) No Yes No No Yes No
Free-Air (5) No Yes No No Yes No

Temperature (TA) Q: –40°C to 125°C
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number. See Section 4 to identify which peripheral instances are accessible on pins in the
smaller package.
(4) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this
peripheral.
(5) The letter Q refers to Q100 qualification for automotive applications.
8 Device Comparison Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
3.1 Related Products

For information about other devices in this family of products, see the following links:
TMS320F2837xD Dual-Core Delfino™ Microcontrollers
The Delfino™ TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for
DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, the
F2837xD supports a new dual-core C28x architecture that significantly boosts system performance. The
integrated analog and control peripherals also let designers consolidate control architectures and eliminate
multiprocessor use in high-end systems.
TMS320F2807x Piccolo™ Microcontrollers
The TMS320F2807x microcontroller platform is part of the Piccolo™ family and is suited for advanced
closed-loop control applications such as industrial drives and servo motor control; solar inverters and
converters; digital power; transportation; and power line communications. Complete development
packages for digital power and industrial drives are available as part of the powerSUITE and
TMS320F2833x Digital Signal Controllers (DSCs)
The TMS320F28335, TMS320F28334, and TMS320F28332 devices, members of the TMS320C28x/
Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding control
applications.
TMS320F2823x Digital Signal Controllers (DSCs)
The TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x/
Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding control
applications.
TMS320C2834x Delfino Microcontrollers
The TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI's existing F2833x
high-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point
performance, and has up to 516KB of on-chip RAM. Designed for real-time control applications, the
C2834x is based on the C28x core, making it code-compatible with all C28x microcontrollers. The on-chip
peripherals and low-latency core make the C2834x an excellent solution for performance-hungry real-time
control applications.
Copyright © 2014–2016, Texas Instruments Incorporated Device Comparison 9

TMS320F28379S, TMS320F28377S
4 Terminal Configuration and Functions

4.1 Pin Diagrams
Figure 4-1 to Figure 4-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid
Array. Each figure shows a quadrant of the terminal assignments. Figure 4-5 shows the pin assignments
on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 4-6 shows the pin
assignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.
1 2 3 4 5 6 7 8 9 10
W VSSA ADCINB1 ADCINB3 ADCINB5 VREFHIB VREFLOD VSS VDDIO GPIO128 GPIO116 W
V VREFHIA ADCINB0 ADCINB2 ADCINB4 VREFHID VREFLOB VSSA GPIO124 GPIO127 GPIO131 V
U ADCINA0 ADCINA2 ADCINA4 ADCIN15 ADCIND1 ADCIND3 ADCIND5 GPIO123 GPIO126 GPIO130 U
T ADCINA1 ADCINA3 ADCINA5 ADCIN14 ADCIND0 ADCIND2 ADCIND4 GPIO122 GPIO125 GPIO129 T
R VREFHIC VREFLOA ADCINC2 ADCINC4 VSSA VDDA VSS VSS VDDIO VDD R
P VSSA VREFLOC ADCINC3 ADCINC5 VSSA VDDA VSS VSS VDDIO VDD P
7 8 9 10
N VSS GPIO109 GPIO114 GPIO113 VSS VSS N
M VDDIO GPIO110 GPIO112 GPIO111 VDDIO VDDIO M VSS VSS VSS M
L GPIO27 GPIO106 GPIO107 GPIO108 VSS VSS L VSS VSS VSS L
K GPIO26 GPIO25 GPIO24 GPIO23 VDD VDD K VSS VSS VSS K
1 2 3 4 5 6 8 9 10
A. Only the GPIO function is shown on GPIO terminals. See Table 4-1 for the complete, muxed signal name.
Figure 4-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]
10 Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
11 12 13 14 15 16 17 18 19
W GPIO29 FLT1 TDI TMS TDO GPIO121 GPIO39 GPIO132 VSS W
V GPIO28 GPIO115 FLT2 TRST TCK GPIO36 GPIO40 GPIO134 VDDIO V
U GPIO31 GPIO117 GPIO32 GPIO34 GPIO120 GPIO37 GPIO41 GPIO135 ERRORSTS U
T GPIO30 GPIO118 GPIO33 GPIO35 GPIO119 GPIO38 GPIO136 GPIO137 GPIO138 T
R VDD3VFL VDD3VFL VDD VSS VSS GPIO48 GPIO49 GPIO50 GPIO51 R
P VSS VSS VDD VSS VSS GPIO52 GPIO53 GPIO54 GPIO55 P
11 12 13
N VDDIO VDDIO GPIO56 GPIO58 GPIO57 GPIO139 N
M VSS VSS M VSS VSS GPIO59 GPIO60 GPIO141 GPIO140 M
L VSS VSS L VDDIO VDDIO GPIO61 GPIO64 VSS GPIO142 L
K VSS VSS K VSS VSS GPIO65 GPIO66 GPIO44 GPIO45 K
11 12 14 15 16 17 18 19
Figure 4-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]
Copyright © 2014–2016, Texas Instruments Incorporated Terminal Configuration and Functions 11

TMS320F28379S, TMS320F28377S
11 12 14 15 16 17 18 19
J VSS VSS J VDD VDD GPIO63 GPIO62 VREGENZ X2 J
H VSS VSS H VSS VSS VDDOSC VDDOSC VSSOSC VSSOSC H
G VDD VDD VSS VSS GPIO133 X1 G

11 12 13
F VDD VSS VDDIO VSS VSS VDDIO GPIO144 GPIO143 XRS F
E VDD VSS VDDIO VSS VSS VDDIO GPIO145 GPIO47 GPIO46 E
D GPIO87 GPIO156 GPIO152 GPIO148 GPIO80 GPIO75 GPIO147 GPIO146 GPIO42 D
C GPIO86 GPIO155 GPIO151 GPIO83 GPIO79 GPIO76 GPIO74 GPIO68 GPIO43 C
B GPIO85 GPIO154 GPIO150 GPIO82 GPIO78 GPIO72 GPIO71 GPIO69 GPIO67 B
A GPIO84 GPIO153 GPIO149 GPIO81 GPIO77 GPIO73 GPIO70 VDDIO VSS A
11 12 13 14 15 16 17 18 19
Figure 4-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]

TMS320F28379S, TMS320F28377S
1 2 3 4 5 6 8 9 10
J GPIO103 GPIO104 GPIO105 GPIO22 VSS VSS J VSS VSS VSS J
H GPIO100 GPIO101 GPIO102 NC VDDIO VDDIO H VSS VSS VSS H
G GPIO99 GPIO8 GPIO9 VDDIO VDDIO VDDIO G

7 8 9 10
F GPIO98 GPIO20 GPIO21 VDDIO VSS VSS VDDIO VSS VDD VDDIO F
E GPIO16 GPIO17 GPIO18 GPIO19 VSS VSS VDDIO VSS VDD VDDIO E
D GPIO13 GPIO14 GPIO15 GPIO168 GPIO166 GPIO89 GPIO5 GPIO1 GPIO162 GPIO159 D
C GPIO11 GPIO12 GPIO96 GPIO167 GPIO165 GPIO88 GPIO4 GPIO0 GPIO161 GPIO158 C
B VDDIO GPIO10 GPIO95 GPIO93 GPIO91 GPIO7 GPIO3 GPIO164 GPIO160 GPIO157 B
A VSS GPIO97 GPIO94 GPIO92 GPIO90 GPIO6 GPIO2 GPIO163 VDDIO VSS A
1 2 3 4 5 6 7 8 9 10
Figure 4-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]

TMS320F28379S, TMS320F28377S
ERRORSTS
VREGENZ
GPIO133
VDDOSC
VDDOSC
VSSOSC
GPIO67
GPIO43
GPIO42
GPIO47
GPIO46
GPIO45
GPIO44
GPIO66
GPIO65
GPIO64
GPIO63
GPIO62
GPIO61
GPIO60
GPIO59
GPIO58
GPIO57
GPIO56
GPIO55
GPIO54
GPIO53
GPIO52
GPIO51
GPIO50
GPIO49
GPIO48
GPIO41
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
XRS
VDD
VDD
X1
X2
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
GPIO68 133 88 VDDIO
GPIO69 134 87 GPIO40
VDD 137 84 GPIO37
VDDIO 138 83 GPIO36
GPIO72 139 82 VDDIO
GPIO73 140 81 TCK
GPIO74 141 80 TMS
GPIO75 142 79 TRST
GPIO76 143 78 TDO
GPIO77 144 77 TDI
GPIO78 145 76 VDD
GPIO79 146 75 VDDIO
VDDIO 147 74 FLT2
GPIO80 148 73 FLT1
GPIO81 149 72 VDD3VFL
VDDIO 152 69 GPIO33
VDD 153 68 VDDIO
VDD 158 63 GPIO30
VDDIO 159 62 VDDIO
GPIO0 160 61 VDD
GPIO1 161 60 ADCIND4
GPIO6 166 55 VREFHID
GPIO7 167 54 VDDA
VDDIO 168 53 VREFHIB
VDD 169 52 VSSA
GPIO88 170 51 VREFLOD
GPIO89 171 50 VREFLOB
GPIO90 172 49 ADCINB3
GPIO94 176 45 ADCIN15
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
11
1
2
3
4
5
6
7
8
9
GPIO11
GPIO21
ADCINA1
GPIO12
GPIO22
ADCINC2
ADCINA2
GPIO10
GPIO14
GPIO20
VDD
VDD
GPIO24
ADCINC4
ADCINA4
ADCINA0
ADCIN14
GPIO13
GPIO16
GPIO17
GPIO23
GPIO26
GPIO27
GPIO18
GPIO19
GPIO99
GPIO8
GPIO9
ADCINC3
ADCINA3
VDDIO
GPIO15
VDDIO
VDDIO
VDDIO
GPIO25
VDDIO
ADCINA5
VREFLOC
VREFHIC
VREFLOA
VSSA
VDDA
VREFHIA
A. Only the GPIO function is shown on GPIO pins. See Table 4-1 for the complete, muxed signal name.
Figure 4-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)

TMS320F28379S, TMS320F28377S
VREGENZ
GPIO69
GPIO43
GPIO42
GPIO66
GPIO65
GPIO64
GPIO63
GPIO62
GPIO61
GPIO60
GPIO59
GPIO58
GPIO41
VDDOSC
VDDOSC
VSSOSC
VDDIO
VDDIO
VDDIO
XRS
VDD
VDD
X1
X2
71
61
51
72
62
52
74
70
64
73
66
60
54
69
68
67
63
56
53
59
58
57
75
65
55
GPIO70 76 50 TCK
GPIO71 77 49 TMS
VDD 78 48 TRST
VDDIO 79 47 TDO
GPIO72 80 46 TDI
GPIO73 81 45 VDD
GPIO78 82 44 VDDIO
VDDIO 83 43 FLT2
VDD 84 42 FLT1
GPIO84 85 41 VDD3VFL
GPIO85 86 40 VDDIO
GPIO86 87 39 VDD
GPIO87 88 38 VDDA
VDD 89 37 VREFHIB
VDDIO 90 36 VSSA
GPIO2 91 35 VSSA
GPIO3 92 34 VREFLOB
GPIO4 93 33 ADCINB5
VDDIO 94 32 ADCINB4
VDD 95 31 ADCINB3
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
GPIO11
GPIO21
ADCINA1
GPIO12
ADCINA2
GPIO14
GPIO20
ADCINA4
ADCINA0
GPIO13
GPIO16
GPIO17
GPIO18
GPIO19
GPIO99
ADCINA3
VDD
GPIO15
ADCINA5
VDDIO
VDDIO
VDDIO
VSSA/VREFLOA
VDDA
VREFHIA
A. Only the GPIO function is shown on GPIO pins. See Table 4-1 for the complete, muxed signal name.
Figure 4-6. 100-Pin PZP PowerPAD HTQFP (Top View)
NOTE
PCB footprints and schematic symbols are available for download in a vendor-neutral format,
which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE
Symbols section in the product folder for each device, under the Packaging section. These
footprints and symbols can also be searched for at http://webench.ti.com/cad/.

TMS320F28379S, TMS320F28377S
4.2 Signal Descriptions

Table 4-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned.
The peripheral signals that are listed under them are alternate functions. Some peripheral functions may
not be available in all devices. See Table 3-1 for details. All GPIO pins are I/O/Z and have an internal
pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the
GPIO pins. The pullups are not enabled at reset.
Table 4-1. Signal Descriptions

TERMINAL
ZWT PTP PZP I/O/Z(1) DESCRIPTION
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
ADC, DAC, AND COMPARATOR SIGNALS
ADC-A high reference. Place at least a 1-µF capacitor
on this pin for the 12-bit mode, or at least a 22-µF
capacitor for the 16-bit mode. This capacitor should be
VREFHIA V1 37 19 I
placed as close to the device as possible between the
VREFHIA and VREFLOA pins.
NOTE: Do not load this pin externally.
ADC-B high reference. Place at least a 1-µF capacitor
VREFHIB W5 53 37 I
VREFHIB and VREFLOB pins.
ADC-C high reference. Place at least a 1-µF capacitor
VREFHIC R1 35 – I
VREFHIC and VREFLOC pins.
ADC-D high reference. Place at least a 1-µF capacitor
VREFHID V5 55 – I
VREFHID and VREFLOD pins.
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA
VREFLOA R2 33 17 I
and VREFLOA. On the PZP package, pin 17 must be
connected to VSSA on the system board.
VREFLOB V6 50 34 I ADC-B low reference
VREFLOC P2 32 – I ADC-C low reference
VREFLOD W6 51 – I ADC-D low reference
ADCIN14 I Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all
T4 44 26 ADCs together (either single-ended or differential) from
an external reference.
CMPIN4P I Comparator 4 positive input
ADCIN15 I Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all
U4 45 27 ADCs together (either single-ended or differential) from
an external reference.
CMPIN4N I Comparator 4 negative input
ADCINA0 I ADC-A input 0. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode which
U1 43 25 cannot be disabled.
DACOUTA O DAC-A output

TMS320F28379S, TMS320F28377S
Table 4-1. Signal Descriptions (continued)

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
ADCINA1 I ADC-A input 1. There is a 50-kΩ internal pulldown on
T1 42 24 cannot be disabled.
DACOUTB O DAC-B output
ADCINA2 I ADC-A input 2
U2 41 23
T2 40 22
U3 39 21
T3 38 20
ADCINB0 I ADC-B input 0. There is a 100-pF capacitor to VSSA on
this pin in both ADC input or DAC reference mode which
cannot be disabled. If this pin is being used as a
reference for the on-chip DACs, place at least a 1-µF
capacitor on this pin.
VDAC V2 46 28 I Optional external reference voltage for on-chip DACs.
There is a 100-pF capacitor to VSSA on this pin in both
ADC input or DAC reference mode which cannot be
disabled. If this pin is being used as a reference for the
on-chip DACs, place at least a 1-µF capacitor on this
pin.
ADCINB1 I ADC-B input 1. There is a 50-kΩ internal pulldown on
W2 47 29 cannot be disabled.
DACOUTC O DAC-C output
ADCINB2 I ADC-B input 2
V3 48 30
ADCINB3 I ADC-B input 3
W3 49 31
ADCINB4 V4 – 32 I ADC-B input 4
ADCINB5 W4 – 33 I ADC-B input 5
ADCINC2 I ADC-C input 2
R3 31 –
P3 30 –
R4 29 –
P4 – –
ADCIND0 I ADC-D input 0
T5 56 –
U5 57 –
T6 58 –
U6 59 –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
ADCIND4 T7 60 – I ADC-D input 4
ADCIND5 U7 – – I ADC-D input 5
GPIO AND PERIPHERAL SIGNALS
GPIO0 0, 4, 8, 12 I/O General-purpose input/output 0
EPWM1A 1 C8 160 – O Enhanced PWM1 output A (HRPWM-capable)
SDAA 6 I/OD I2C-A data open-drain bidirectional port
EPWM1B 1 O Enhanced PWM1 output B (HRPWM-capable)
D8 161 –
MFSRB 3 I/O McBSP-B receive frame synch
SCLA 6 I/OD I2C-A clock open-drain bidirectional port
EPWM2A 1 O Enhanced PWM2 output A (HRPWM-capable)
A7 162 91
OUTPUTXBAR1 5 O Output 1 of the output XBAR
SDAB 6 I/OD I2C-B data open-drain bidirectional port
B7 163 92
MCLKRB 3 I/O McBSP-B receive clock
SCLB 6 I/OD I2C-B clock open-drain bidirectional port
C7 164 93
CANTXA 6 O CAN-A transmit
MFSRA 2 D7 165 – I/O McBSP-A receive frame synch
CANRXA 6 I CAN-A receive
A6 166 –
EXTSYNCOUT 3 O External ePWM synch pulse output
EQEP3A 5 I Enhanced QEP3 input A
CANTXB 6 O CAN-B transmit
MCLKRA 2 I/O McBSP-A receive clock
B6 167 –
EQEP3B 5 I Enhanced QEP3 input B
CANRXB 6 I CAN-B receive

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
G2 18 –
ADCSOCAO 3 O ADC start-of-conversion A output for external ADC
EQEP3S 5 I/O Enhanced QEP3 strobe
SCITXDA 6 O SCI-A transmit data
SCITXDB 2 O SCI-B transmit data
G3 19 –
EQEP3I 5 I/O Enhanced QEP3 index
SCIRXDA 6 I SCI-A receive data
ADCSOCBO 3 O ADC start-of-conversion B output for external ADC
B2 1 100
UPP-WAIT 15 I/O Universal parallel port wait. Receiver asserts to request
a pause in transfer.
SCIRXDB 2, 6 I SCI-B receive data
OUTPUTXBAR7 3 C1 2 1 O Output 7 of the output XBAR
UPP-START 15 I/O Universal parallel port start. Transmitter asserts at start
of DMA line.
MDXB 3 O McBSP-B transmit serial data
C2 4 3
SCITXDC 6 O SCI-C transmit data
UPP-ENA 15 I/O Universal parallel port enable. Transmitter asserts while
data bus is active.
MDRB 3 D1 5 4 I McBSP-B receive serial data
SCIRXDC 6 I SCI-C receive data
UPP-D7 15 I/O Universal parallel port data line 7

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
D2 6 5
MCLKXB 3 I/O McBSP-B transmit clock
SCIRXDB 2 I SCI-B receive data
D3 7 6
MFSXB 3 I/O McBSP-B transmit frame synch
SPISIMOA 1 I/O SPI-A slave in, master out
OUTPUTXBAR7 3 E1 8 7 O Output 7 of the output XBAR
EPWM9A 5 O Enhanced PWM9 output A
SD1_D1 7 I Sigma-Delta 1 channel 1 data input
SPISOMIA 1 I/O SPI-A slave out, master in
OUTPUTXBAR8 3 E2 9 8 O Output 8 of the output XBAR
EPWM9B 5 O Enhanced PWM9 output B
SD1_C1 7 I Sigma-Delta 1 channel 1 clock input
SPICLKA 1 I/O SPI-A clock
CANRXA 3 E3 10 9 I CAN-A receive
SPISTEA 1 I/O SPI-A slave transmit enable
CANTXA 3 E4 12 11 O CAN-A transmit

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
MDXA 2 O McBSP-A transmit serial data
CANTXB 3 F2 13 12 O CAN-B transmit
MDRA 2 I McBSP-A receive serial data
CANRXB 3 F3 14 13 I CAN-B receive
UPP-CLK 15 I/O Universal parallel port transmit clock
MCLKXA 2 I/O McBSP-A transmit clock
SCITXDB 3 J4 22 – O SCI-B transmit data
SPICLKB 6 I/O SPI-B clock
MFSXA 2 I/O McBSP-A transmit frame synch
SCIRXDB 3 K4 23 – I SCI-B receive data
SPISTEB 6 I/O SPI-B slave transmit enable
K3 24 –
SPISIMOB 6 I/O SPI-B slave in, master out
K2 25 –
MDRB 3 I McBSP-B receive serial data
SPISOMIB 6 I/O SPI-B slave out, master in

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
MCLKXB 3 K1 27 – I/O McBSP-B transmit clock
MFSXB 3 L1 28 – I/O McBSP-B transmit frame synch
EM1CS4 2 O External memory interface 1 chip select 4
V11 64 –
EM1SDCKE 2 O External memory interface 1 SDRAM clock enable
W11 65 –
EM1CLK 2 O External memory interface 1 clock
T11 63 –
EM1WE 2 O External memory interface 1 write enable
U11 66 –
SDAA 1 U13 67 – I/OD I2C-A data open-drain bidirectional port
SCLA 1 T13 69 – I/OD I2C-A clock open-drain bidirectional port
EM1RNW 2 O External memory interface 1 read not write

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
U14 70 –
T14 71 –
V16 83 –
EM1WAIT 2 I External memory interface 1 Asynchronous SRAM WAIT
U16 84 –
EM1OE 2 O External memory interface 1 output enable
EM1A0 2 O External memory interface 1 address line 0
T16 85 –
W17 86 –
EM1A2 2 V17 87 – O External memory interface 1 address line 2
GPIO41 0, 4, 8, 12 I/O General-purpose input/output 41. For applications using
the Hibernate low-power mode, this pin serves as the
GPIOHIBWAKE signal. For details, see the Low Power
Modes section of the System Control chapter in the
U17 89 51 TMS320F2837xS Delfino Microcontrollers Technical
Reference Manual.
D19 130 73
USB0DM Analog I/O USB PHY differential data
C19 131 74
USB0DP Analog I/O USB PHY differential data
K18 113 –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
K19 115 –
EM1A6 2 E19 128 – O External memory interface 1 address line 6
SCIRXDD 6 I SCI-D receive data
EM1A7 2 E18 129 – O External memory interface 1 address line 7
SCITXDD 6 O SCI-D transmit data
EM1A8 2 R16 90 – O External memory interface 1 address line 8
SPISIMOC 6 I/O SPI-C slave in, master out
SPISOMIC 6 I/O SPI-C slave out, master in
EM1A12 2 P16 96 – O External memory interface 1 address line 12
SPICLKC 6 I/O SPI-C clock
EM1D31 2 I/O External memory interface 1 data line 31
P17 97 –
SPISTEC 6 I/O SPI-C slave transmit enable

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
SPISIMOA 1 I/O SPI-A slave in, master out
EM2D14 3 P18 98 – I/O External memory interface 2 data line 14
SPISOMIA 1 I/O SPI-A slave out, master in
EM2D13 3 P19 100 – I/O External memory interface 2 data line 13
SPICLKA 1 I/O SPI-A clock
EM2D12 3 N16 101 – I/O External memory interface 2 data line 12
SPISTEA 1 I/O SPI-A slave transmit enable
EM2D11 3 N18 102 – I/O External memory interface 2 data line 11
MCLKRA 1 I/O McBSP-A receive clock
N17 103 52
SPISIMOA 15 I/O SPI-A slave in, master out(2)
GPIO59 0, 4, 8, 12 I/O General-purpose input/output 59(3)
MFSRA 1 I/O McBSP-A receive frame synch
M16 104 53
SPISOMIA 15 I/O SPI-A slave out, master in(2)

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
MCLKRB 1 I/O McBSP-B receive clock
M17 105 54
SPISIMOB 6 I/O SPI-B slave in, master out
SPICLKA 15 I/O SPI-A clock(2)
MFSRB 1 I/O McBSP-B receive frame synch
L16 107 56
SPISOMIB 6 I/O SPI-B slave out, master in
SPISTEA 15 I/O SPI-A slave transmit enable(2)
EM2D6 3 J17 108 57 I/O External memory interface 2 data line 6
J16 109 58
SPISIMOB 15 I/O SPI-B slave in, master out(2)
L17 110 59
SPISOMIB 15 I/O SPI-B slave out, master in(2)
K16 111 60
SPICLKB 15 I/O SPI-B clock(2)

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
EM2D2 3 K17 112 61 I/O External memory interface 2 data line 2
SPISTEB 15 I/O SPI-B slave transmit enable(2)
EM1D17 2 B19 132 – I/O External memory interface 1 data line 17
EM1D16 2 C18 133 – I/O External memory interface 1 data line 16
B18 134 75
SPISIMOC 15 I/O SPI-C slave in, master out(2)
CANRXA 5 A17 135 76 I CAN-A receive
SPISOMIC 15 I/O SPI-C slave out, master in(2)
CANTXA 5 B17 136 77 O CAN-A transmit
SPICLKC 15 I/O SPI-C clock(2)
GPIO72 General-purpose input/output 72.(3) This is the factory
0, 4, 8, 12 I/O
default boot mode select pin 1.
B16 139 80
SPISTEC 15 I/O SPI-C slave transmit enable(2)
XCLKOUT 3 O/Z External clock output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
The clock signal is chosen using the
A16 140 81
CLKSRCCTL3.XCLKOUTSEL bit field while the divide
ratio is chosen using the
XCLKOUTDIVSEL.XCLKOUTDIV bit field.
SCIRXDC 6 I SCI-C receive
C17 141 –
D16 142 –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
EM1D7 2 A15 144 – I/O External memory interface 1 data line 7
EM1D6 2 B15 145 82 I/O External memory interface 1 data line 6
EM1D4 2 D15 148 – I/O External memory interface 1 data line 4
EM1D3 2 A14 149 – I/O External memory interface 1 data line 3
B14 150 –
C14 151 –
General-purpose input/output 84. This is the factory
GPIO84 0, 4, 8, 12 I/O
default boot mode select pin 0.
SCITXDA 5 A11 154 85 O SCI-A transmit data
MDXA 15 O McBSP-A transmit serial data
SCIRXDA 5 B11 155 86 I SCI-A receive data
MDRB 6 I McBSP-B receive serial data
MDRA 15 I McBSP-A receive serial data
EM1CAS 3 O External memory interface 1 column address strobe
C11 156 87
MCLKXB 6 I/O McBSP-B transmit clock
MCLKXA 15 I/O McBSP-A transmit clock
EM1RAS 3 O External memory interface 1 row address strobe
D11 157 88
MFSXB 6 I/O McBSP-B transmit frame synch
MFSXA 15 I/O McBSP-A transmit frame synch

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
EM1A15 2 C6 170 – O External memory interface 1 address line 15
EM1DQM0 3 O External memory interface 1 Input/output mask for byte 0
D6 171 96
A5 172 97
B5 173 98
A4 174 99
EM1BA1 3 O External memory interface 1 bank address 1
EM1BA0 3 B4 175 – O External memory interface 1 bank address 0
A3 176 –
GPIO95 0, 2, 4, 8 B3 – – I/O General-purpose input/output 95
EM2DQM1 3 C3 – – O External memory interface 2 Input/output mask for byte 1
EM2DQM0 3 A2 – – O External memory interface 2 Input/output mask for byte 0
EM2A0 3 F1 – – O External memory interface 2 address line 0
EM2A1 3 G1 17 14 O External memory interface 2 address line 1
H1 – –
SPISIMOC 6 I/O SPI-C slave in, master out
H2 – –
SPISOMIC 6 I/O SPI-C slave out, master in

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
H3 – –
SPICLKC 6 I/O SPI-C clock
J1 – –
SPISTEC 6 I/O SPI-C slave transmit enable
EM2A6 3 J2 – – O External memory interface 2 address line 6
EM2A7 3 J3 – – O External memory interface 2 address line 7
L2 – –
L3 – –
L4 – –
N2 – –
M2 – –
EM2WAIT 3 I External memory interface 2 Asynchronous SRAM WAIT
M4 – –
M3 – –
N4 – –
EM2CAS 3 O External memory interface 2 column address strobe
N3 – –
EM2RAS 3 O External memory interface 2 row address strobe
V12 – –
W10 – –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
U12 – –
EM2SDCKE 3 O External memory interface 2 SDRAM clock enable
T12 – –
EM2CLK 3 O External memory interface 2 clock
T15 – –
EM2RNW 3 O External memory interface 2 read not write
EM2WE 3 U15 – – O External memory interface 2 write enable
USB0PFLT 15 I/O USB external regulator power fault indicator
EM2OE 3 W16 – – O External memory interface 2 output enable
USB0EPEN 15 I/O USB external regulator enable
SPISIMOC 6 T8 – – I/O SPI-C slave in, master out
SPISOMIC 6 U8 – – I/O SPI-C slave out, master in
SPICLKC 6 V8 – – I/O SPI-C clock
SPISTEC 6 T9 – – I/O SPI-C slave transmit enable
U9 – –
V9 – –
W9 – –
T10 – –
U10 – –
V10 – –
W18 – –
GPIO133/AUXCLKIN 0, 4, 8, 12 I/O General-purpose input/output 133. The AUXCLKIN
function of this GPIO pin could be used to provide a
single-ended 3.3-V level clock signal to the Auxiliary
G18 118 – Phase-Locked Loop (AUXPLL), whose output is used for
the USB module. The AUXCLKIN clock may also be
used for the CAN module.

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
V18 – –
SCITXDA 6 U18 – – O SCI-A transmit data
SCIRXDA 6 T17 – – I SCI-A receive data
SCITXDB 6 T18 – – O SCI-B transmit data
T19 – –
N19 – –
M19 – –
M18 – –
L19 – –
GPIO143 0, 4, 8, 12 F18 – – I/O General-purpose input/output 143
GPIO144 0, 4, 8, 12 F17 – – I/O General-purpose input/output 144
E17 – –
D18 – –
D17 – –
D14 – –
A13 – –
B13 – –
C13 – –
D13 – –
A12 – –
B12 – –
C12 – –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
D12 – –
B10 – –
C10 – –
D10 – –
B9 – –
C9 – –
D9 – –
A8 – –
B8 – –
C5 – –
D5 – –
C4 – –
D4 – –
RESET
Device Reset (in) and Watchdog Reset (out). The
devices have a built-in power-on reset (POR) circuit.
During a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset or NMI watchdog reset
occurs. During watchdog reset, the XRS pin is driven low
XRS F19 124 69 I/OD for the watchdog reset duration of 512 OSCCLK cycles.
A resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be
100 nF or smaller. These values will allow the watchdog
to properly drive the XRS pin to VOL within 512 OSCCLK
cycles when the watchdog reset is asserted. The output
buffer of this pin is an open drain with an internal pullup.
CLOCKS
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
X1 G19 123 68 I this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
On-chip crystal-oscillator output. A quartz crystal may be
X2 J19 121 66 O connected across X1 and X2. If X2 is not used, it must
be left unconnected.

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
NO CONNECT
No connect. BGA ball is electrically open and not
NC H4 – –
connected to the die.
JTAG
TCK V15 81 50 I JTAG test clock with internal pullup (see Section 5.5)
JTAG test data input (TDI) with internal pullup. TDI is
TDI W13 77 46 I clocked into the selected register (instruction or data) on
a rising edge of TCK.
JTAG scan out, test data output (TDO). The contents of
TDO W15 78 47 O/Z the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK.(3)
JTAG test-mode select (TMS) with internal pullup. This
TMS W14 80 49 I serial control input is clocked into the TAP controller on
the rising edge of TCK.
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained
low at all times during normal device operation. An
external pulldown resistor is required on this pin. The
TRST V14 79 48 I
value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ
or smaller resistor generally offers adequate protection.
The value of the resistor is application-specific. TI
recommends that each target board be validated for
proper operation of the debugger and the application.
This pin has an internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
Internal voltage regulator enable with internal pulldown.
VREGENZ J18 119 64 I To enable the 1.2-V VREG, pull low to VSS. To disable,
pull high to VDDIO.
ANALOG, DIGITAL, AND I/O POWER
E9 16 16
E11 21 39
F9 61 45
F11 76 63
G14 117 71
1.2-V digital logic power pins. If the internal 1.2-V VREG
G15 126 78 is used, place a decoupling capacitor near each VDD pin
J14 137 84 and distribute 12 µF to 26 µF evenly across all VDD pins.
VDD If an external supply is used, TI recommends a minimum
J15 153 89 total capacitance of 20 µF. The exact value of the
K5 158 95 decoupling capacitance should be determined by your
system voltage regulation solution.
K6 169 –
P10 – –
P13 – –
R10 – –
R13 – –
R11 72 41 3.3-V Flash power pin. Place a minimum 0.1-µF
VDD3VFL
R12 – – decoupling capacitor on each pin.
P6 36 18 3.3-V analog power pins. Place a minimum 2.2-µF
VDDA
R6 54 38 decoupling capacitor to VSSA on each pin.

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
A9 3 2
A18 11 10
B1 15 15
E7 20 40
E10 26 44
E13 62 55
E16 68 62
F4 75 72
F7 82 79
F10 88 83
F13 91 90
F16 99 94
G4 106 –
3.3-V digital I/O power pins. Place a minimum 0.1-µF
G5 114 – decoupling capacitor on each pin. The exact value of the
VDDIO
G6 116 – decoupling capacitance should be determined by your
system voltage regulation solution.
H5 127 –
H6 138 –
L14 147 –
L15 152 –
M1 159 –
M5 168 –
M6 – –
N14 – –
N15 – –
P9 – –
R9 – –
V19 – –
W8 – –
H16 120 65 Power pins for the 3.3-V on-chip crystal oscillator (X1
and X2) and the two zero-pin internal oscillators
VDDOSC
H17 125 70 (INTOSC). Place a 0.1-μF (minimum) decoupling
capacitor on each pin.

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
A1
A10
A19
E5
E6
E8
E12
E14
E15
F5
F6
F8
F12
F14
F15
G16
G17
H8
H9
H10
H11 Analog and digital ground. For Quad Flatpacks (QFPs),
PWR PWR
VSS the PowerPAD on the bottom of the package must be
H12 PAD PAD
soldered to the ground plane of the PCB.
H14
H15
J5
J6
J8
J9
J10
J11
J12
K8
K9
K10
K11
K12
K14
K15
L5
L6
L8
L9

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
L10
L11
L12
L18
M8
M9
M10
M11
M12
M14
M15
N1
N5 Analog and digital ground. For Quad Flatpacks (QFPs),
PWR PWR
VSS the PowerPAD on the bottom of the package must be
N6 PAD PAD
soldered to the ground plane of the PCB.
P7
P8
P11
P12
P14
P15
R7
R8
R14
R15
W7
W19
H18 122 67 Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of the
VSSOSC
H19 – – external crystal oscillator circuit.
If an external crystal is not used, this pin may be
connected to the board ground.
P1 34 17
P5 52 35
Analog module ground pins.
VSSA R5 – 36 On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. This pin must be connect to VSSA.
V7 – –
W1 – –

TMS320F28379S, TMS320F28377S

TERMINAL
MUX
NAME BALL PIN PIN
POSITION
NO. NO. NO.
SPECIAL FUNCTIONS
ERRORSTS U19 92 – O Error status output. This pin has an internal pulldown.
TEST PINS
Flash test pin 1. Reserved for TI. Must be left
FLT1 W12 73 42 I/O
unconnected.
Flash test pin 2. Reserved for TI. Must be left
FLT2 V13 74 43 I/O
unconnected.
(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance
(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in
SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system
PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination
resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be performed
with the provided IBIS models. The termination is not required if this pin is used for input function.
4.3 Pins With Internal Pullup and Pulldown

Some pins on the device have internal pullups or pulldowns. Table 4-2 lists the pull direction and when it
is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order
to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are
not bonded out in a particular package. Other pins noted in Table 4-2 with pullups and pulldowns are
always on and cannot be disabled.
Table 4-2. Pins With Internal Pullup and Pulldown

RESET
PIN DEVICE BOOT APPLICATION SOFTWARE
(XRS = 0)
Pullup enable is application-
GPIOx Pullup disabled Pullup disabled (1)
defined
TRST Pulldown active
TCK Pullup active
TMS Pullup active
TDI Pullup active
XRS Pullup active
VREGENZ Pulldown active
ERRORSTS Pulldown active
Other pins No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.

TMS320F28379S, TMS320F28377S
4.4 Connections for Unused Pins

For applications that do not need to use all functions of the device, Table 4-3 lists acceptable conditioning
for any unused pins. When multiple options are listed in Table 4-3, any are acceptable. Pins not listed in
Table 4-3 must be connected according to Table 4-1.
Table 4-3. Connections for Unused Pins

SIGNAL NAME ACCEPTABLE PRACTICE
Analog
VREFHIx Tie to VDDA
VREFLOx Tie to VSSA
• No Connect
ADCINx
• Tie to VSSA
Digital
• Input mode with internal pullup enabled
GPIOx • Input mode with external pullup or pulldown resistor
• Output mode with internal pullup disabled
X1 Tie to VSS
X2 No Connect
• No Connect
TCK
• Pullup resistor
• No Connect
TDI
• Pullup resistor
TDO No Connect
TMS No Connect
TRST Pulldown resistor (2.2 kΩ or smaller)
VREGENZ Tie to VDDIO
ERRORSTS No Connect
FLT1 No Connect
FLT2 No Connect
Power and Ground
VDD All VDD pins must be connected per Table 4-1.
VDDA If a separate analog supply is not used, tie to VDDIO.
VDDIO All VDDIO pins must be connected per Table 4-1.
VDD3VFL Must be tied to VDDIO
VDDOSC Must be tied to VDDIO
VSS All VSS pins must be connected to board ground.
VSSA If a separate analog ground is not used, tie to VSS.
VSSOSC If an external crystal is not used, this pin may be connected to the board ground.

TMS320F28379S, TMS320F28377S
4.5 Pin Multiplexing
4.5.1 GPIO Muxed Pins

Table 4-4 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions
can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The
GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from
alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 4-4. GPIO Muxed Pins (1) (2)
GPIO Mux Selection

GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO0 EPWM1A (O) SDAA (I/OD)
GPIO1 EPWM1B (O) MFSRB (I/O) SCLA (I/OD)
GPIO2 EPWM2A (O) OUTPUTXBAR1 (O) SDAB (I/OD)
GPIO3 EPWM2B (O) OUTPUTXBAR2 (O) MCLKRB (I/O) OUTPUTXBAR2 (O) SCLB (I/OD)
GPIO4 EPWM3A (O) OUTPUTXBAR3 (O) CANTXA (O)
GPIO5 EPWM3B (O) MFSRA (I/O) OUTPUTXBAR3 (O) CANRXA (I)
GPIO6 EPWM4A (O) OUTPUTXBAR4 (O) EXTSYNCOUT (O) EQEP3A (I) CANTXB (O)
GPIO7 EPWM4B (O) MCLKRA (I/O) OUTPUTXBAR5 (O) EQEP3B (I) CANRXB (I)
GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O) EQEP3S (I/O) SCITXDA (O)
GPIO9 EPWM5B (O) SCITXDB (O) OUTPUTXBAR6 (O) EQEP3I (I/O) SCIRXDA (I)
GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O) EQEP1A (I) SCITXDB (O) UPP-WAIT (I/O)
GPIO11 EPWM6B (O) SCIRXDB (I) OUTPUTXBAR7 (O) EQEP1B (I) SCIRXDB (I) UPP-START (I/O)
GPIO12 EPWM7A (O) CANTXB (O) MDXB (O) EQEP1S (I/O) SCITXDC (O) UPP-ENA (I/O)
GPIO13 EPWM7B (O) CANRXB (I) MDRB (I) EQEP1I (I/O) SCIRXDC (I) UPP-D7 (I/O)
GPIO14 EPWM8A (O) SCITXDB (O) MCLKXB (I/O) OUTPUTXBAR3 (O) UPP-D6 (I/O)
GPIO15 EPWM8B (O) SCIRXDB (I) MFSXB (I/O) OUTPUTXBAR4 (O) UPP-D5 (I/O)
GPIO16 SPISIMOA (I/O) CANTXB (O) OUTPUTXBAR7 (O) EPWM9A (O) SD1_D1 (I) UPP-D4 (I/O)
GPIO17 SPISOMIA (I/O) CANRXB (I) OUTPUTXBAR8 (O) EPWM9B (O) SD1_C1 (I) UPP-D3 (I/O)
GPIO18 SPICLKA (I/O) SCITXDB (O) CANRXA (I) EPWM10A (O) SD1_D2 (I) UPP-D2 (I/O)
GPIO19 SPISTEA (I/O) SCIRXDB (I) CANTXA (O) EPWM10B (O) SD1_C2 (I) UPP-D1 (I/O)
GPIO20 EQEP1A (I) MDXA (O) CANTXB (O) EPWM11A (O) SD1_D3 (I) UPP-D0 (I/O)
GPIO21 EQEP1B (I) MDRA (I) CANRXB (I) EPWM11B (O) SD1_C3 (I) UPP-CLK (I/O)
GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O) EPWM12A (O) SPICLKB (I/O) SD1_D4 (I)
GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I) EPWM12B (O) SPISTEB (I/O) SD1_C4 (I)
GPIO24 OUTPUTXBAR1 (O) EQEP2A (I) MDXB (O) SPISIMOB (I/O) SD2_D1 (I)
GPIO25 OUTPUTXBAR2 (O) EQEP2B (I) MDRB (I) SPISOMIB (I/O) SD2_C1 (I)
GPIO26 OUTPUTXBAR3 (O) EQEP2I (I/O) MCLKXB (I/O) OUTPUTXBAR3 (O) SPICLKB (I/O) SD2_D2 (I)
GPIO27 OUTPUTXBAR4 (O) EQEP2S (I/O) MFSXB (I/O) OUTPUTXBAR4 (O) SPISTEB (I/O) SD2_C2 (I)
GPIO28 SCIRXDA (I) EM1CS4 (O) OUTPUTXBAR5 (O) EQEP3A (I) SD2_D3 (I)
GPIO29 SCITXDA (O) EM1SDCKE (O) OUTPUTXBAR6 (O) EQEP3B (I) SD2_C3 (I)
GPIO30 CANRXA (I) EM1CLK (O) OUTPUTXBAR7 (O) EQEP3S (I/O) SD2_D4 (I)
GPIO31 CANTXA (O) EM1WE (O) OUTPUTXBAR8 (O) EQEP3I (I/O) SD2_C4 (I)
GPIO32 SDAA (I/OD) EM1CS0 (O)
GPIO33 SCLA (I/OD) EM1RNW (O)
GPIO34 OUTPUTXBAR1 (O) EM1CS2 (O) SDAB (I/OD)
GPIO35 SCIRXDA (I) EM1CS3 (O) SCLB (I/OD)
GPIO36 SCITXDA (O) EM1WAIT (I) CANRXA (I)
GPIO37 OUTPUTXBAR2 (O) EM1OE (O) CANTXA (O)
GPIO38 EM1A0 (O) SCITXDC (O) CANTXB (O)
GPIO39 EM1A1 (O) SCIRXDC (I) CANRXB (I)
(1) I = Input, O = Output, OD = Open Drain

(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
TMS320F28379S, TMS320F28377S
Table 4-4. GPIO Muxed Pins(1)(2) (continued)

GPIO Mux Selection
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO40 EM1A2 (O) SDAB (I/OD)
GPIO41 EM1A3 (O) SCLB (I/OD)
GPIO42 SDAA (I/OD) SCITXDA (O)
GPIO43 SCLA (I/OD) SCIRXDA (I)
GPIO44 EM1A4 (O)
GPIO45 EM1A5 (O)
GPIO46 EM1A6 (O) SCIRXDD (I)
GPIO47 EM1A7 (O) SCITXDD (O)
GPIO48 OUTPUTXBAR3 (O) EM1A8 (O) SCITXDA (O) SD1_D1 (I)
GPIO49 OUTPUTXBAR4 (O) EM1A9 (O) SCIRXDA (I) SD1_C1 (I)
GPIO50 EQEP1A (I) EM1A10 (O) SPISIMOC (I/O) SD1_D2 (I)
GPIO51 EQEP1B (I) EM1A11 (O) SPISOMIC (I/O) SD1_C2 (I)
GPIO52 EQEP1S (I/O) EM1A12 (O) SPICLKC (I/O) SD1_D3 (I)
GPIO53 EQEP1I (I/O) EM1D31 (I/O) EM2D15 (I/O) SPISTEC (I/O) SD1_C3 (I)
GPIO54 SPISIMOA (I/O) EM1D30 (I/O) EM2D14 (I/O) EQEP2A (I) SCITXDB (O) SD1_D4 (I)
GPIO55 SPISOMIA (I/O) EM1D29 (I/O) EM2D13 (I/O) EQEP2B (I) SCIRXDB (I) SD1_C4 (I)
GPIO56 SPICLKA (I/O) EM1D28 (I/O) EM2D12 (I/O) EQEP2S (I/O) SCITXDC (O) SD2_D1 (I)
GPIO57 SPISTEA (I/O) EM1D27 (I/O) EM2D11 (I/O) EQEP2I (I/O) SCIRXDC (I) SD2_C1 (I)
GPIO58 MCLKRA (I/O) EM1D26 (I/O) EM2D10 (I/O) OUTPUTXBAR1 (O) SPICLKB (I/O) SD2_D2 (I) SPISIMOA (3) (I/O)
GPIO59 MFSRA (I/O) EM1D25 (I/O) EM2D9 (I/O) OUTPUTXBAR2 (O) SPISTEB (I/O) SD2_C2 (I) SPISOMIA (3) (I/O)
GPIO60 MCLKRB (I/O) EM1D24 (I/O) EM2D8 (I/O) OUTPUTXBAR3 (O) SPISIMOB (I/O) SD2_D3 (I) SPICLKA (3) (I/O)
GPIO61 MFSRB (I/O) EM1D23 (I/O) EM2D7 (I/O) OUTPUTXBAR4 (O) SPISOMIB (I/O) SD2_C3 (I) SPISTEA (3) (I/O)
GPIO62 SCIRXDC (I) EM1D22 (I/O) EM2D6 (I/O) EQEP3A (I) CANRXA (I) SD2_D4 (I)
GPIO63 SCITXDC (O) EM1D21 (I/O) EM2D5 (I/O) EQEP3B (I) CANTXA (O) SD2_C4 (I) SPISIMOB (3) (I/O)
GPIO64 EM1D20 (I/O) EM2D4 (I/O) EQEP3S (I/O) SCIRXDA (I) SPISOMIB (3) (I/O)
GPIO65 EM1D19 (I/O) EM2D3 (I/O) EQEP3I (I/O) SCITXDA (O) SPICLKB (3) (I/O)
GPIO66 EM1D18 (I/O) EM2D2 (I/O) SDAB (I/OD) SPISTEB (3) (I/O)
GPIO67 EM1D17 (I/O) EM2D1 (I/O)
GPIO68 EM1D16 (I/O) EM2D0 (I/O)
GPIO69 EM1D15 (I/O) SCLB (I/OD) SPISIMOC (3) (I/O)
GPIO70 EM1D14 (I/O) CANRXA (I) SCITXDB (O) SPISOMIC (3) (I/O)
GPIO71 EM1D13 (I/O) CANTXA (O) SCIRXDB (I) SPICLKC (3) (I/O)
GPIO72 EM1D12 (I/O) CANTXB (O) SCITXDC (O) SPISTEC (3) (I/O)
GPIO73 EM1D11 (I/O) XCLKOUT (O) CANRXB (I) SCIRXDC (I)
GPIO74 EM1D10 (I/O)
GPIO75 EM1D9 (I/O)
GPIO76 EM1D8 (I/O) SCITXDD (O)
GPIO77 EM1D7 (I/O) SCIRXDD (I)
GPIO78 EM1D6 (I/O) EQEP2A (I)
GPIO79 EM1D5 (I/O) EQEP2B (I)
GPIO80 EM1D4 (I/O) EQEP2S (I/O)
GPIO81 EM1D3 (I/O) EQEP2I (I/O)
GPIO82 EM1D2 (I/O)
GPIO83 EM1D1 (I/O)
GPIO84 SCITXDA (O) MDXB (O) MDXA (O)
GPIO85 EM1D0 (I/O) SCIRXDA (I) MDRB (I) MDRA (I)
GPIO86 EM1A13 (O) EM1CAS (O) SCITXDB (O) MCLKXB (I/O) MCLKXA (I/O)
GPIO87 EM1A14 (O) EM1RAS (O) SCIRXDB (I) MFSXB (I/O) MFSXA (I/O)
GPIO88 EM1A15 (O) EM1DQM0 (O)
GPIO89 EM1A16 (O) EM1DQM1 (O) SCITXDC (O)
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in
SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
TMS320F28379S, TMS320F28377S

GPIO Mux Selection
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO90 EM1A17 (O) EM1DQM2 (O) SCIRXDC (I)
GPIO91 EM1A18 (O) EM1DQM3 (O) SDAA (I/OD)
GPIO92 EM1A19 (O) EM1BA1 (O) SCLA (I/OD)
GPIO93 EM1BA0 (O) SCITXDD (O)
GPIO94 SCIRXDD (I)
GPIO95
GPIO96 EM2DQM1 (O) EQEP1A (I)
GPIO97 EM2DQM0 (O) EQEP1B (I)
GPIO98 EM2A0 (O) EQEP1S (I/O)
GPIO99 EM2A1 (O) EQEP1I (I/O)
GPIO100 EM2A2 (O) EQEP2A (I) SPISIMOC (I/O)
GPIO101 EM2A3 (O) EQEP2B (I) SPISOMIC (I/O)
GPIO102 EM2A4 (O) EQEP2S (I/O) SPICLKC (I/O)
GPIO103 EM2A5 (O) EQEP2I (I/O) SPISTEC (I/O)
GPIO104 SDAA (I/OD) EM2A6 (O) EQEP3A (I) SCITXDD (O)
GPIO105 SCLA (I/OD) EM2A7 (O) EQEP3B (I) SCIRXDD (I)
GPIO106 EM2A8 (O) EQEP3S (I/O) SCITXDC (O)
GPIO107 EM2A9 (O) EQEP3I (I/O) SCIRXDC (I)
GPIO108 EM2A10 (O)
GPIO109 EM2A11 (O)
GPIO110 EM2WAIT (I)
GPIO111 EM2BA0 (O)
GPIO112 EM2BA1 (O)
GPIO113 EM2CAS (O)
GPIO114 EM2RAS (O)
GPIO115 EM2CS0 (O)
GPIO116 EM2CS2 (O)
GPIO117 EM2SDCKE (O)
GPIO118 EM2CLK (O)
GPIO119 EM2RNW (O)
GPIO120 EM2WE (O) USB0PFLT
GPIO121 EM2OE (O) USB0EPEN
GPIO122 SPISIMOC (I/O) SD1_D1 (I)
GPIO123 SPISOMIC (I/O) SD1_C1 (I)
GPIO124 SPICLKC (I/O) SD1_D2 (I)
GPIO125 SPISTEC (I/O) SD1_C2 (I)
GPIO126 SD1_D3 (I)
GPIO127 SD1_C3 (I)
GPIO128 SD1_D4 (I)
GPIO129 SD1_C4 (I)
GPIO130 SD2_D1 (I)
GPIO131 SD2_C1 (I)
GPIO132 SD2_D2 (I)
GPIO133/
SD2_C2 (I)
AUXCLKIN
GPIO134 SD2_D3 (I)
GPIO135 SCITXDA (O) SD2_C3 (I)
GPIO136 SCIRXDA (I) SD2_D4 (I)
GPIO137 SCITXDB (O) SD2_C4 (I)
GPIO138 SCIRXDB (I)
GPIO139 SCIRXDC (I)
GPIO140 SCITXDC (O)

TMS320F28379S, TMS320F28377S

GPIO Mux Selection
GPIO Index 0, 4, 8, 12 1 2 3 5 6 7 15
GPyGMUXn. 00b, 01b,
00b 01b 11b
GPIOz = 10b, 11b
GPyMUXn.
00b 01b 10b 11b 01b 10b 11b 11b
GPIOz =
GPIO141 SCIRXDD (I)
GPIO142 SCITXDD (O)
GPIO143
GPIO144
GPIO145 EPWM1A (O)
GPIO146 EPWM1B (O)
GPIO147 EPWM2A (O)
GPIO148 EPWM2B (O)
GPIO149 EPWM3A (O)
GPIO150 EPWM3B (O)
GPIO151 EPWM4A (O)
GPIO152 EPWM4B (O)
GPIO153 EPWM5A (O)
GPIO154 EPWM5B (O)
GPIO155 EPWM6A (O)
GPIO156 EPWM6B (O)
GPIO157 EPWM7A (O)
GPIO158 EPWM7B (O)
GPIO159 EPWM8A (O)
GPIO160 EPWM8B (O)
GPIO161 EPWM9A (O)
GPIO162 EPWM9B (O)
GPIO163 EPWM10A (O)
GPIO164 EPWM10B (O)
GPIO165 EPWM11A (O)
GPIO166 EPWM11B (O)
GPIO167 EPWM12A (O)
GPIO168 EPWM12B (O)

TMS320F28379S, TMS320F28377S
4.5.2 Input X-BAR

The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 4-7). Table 4-5 shows the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xS Delfino
Microcontrollers Technical Reference Manual.
INPUT7 eCAP1
GPIO0 INPUT8 eCAP2
Asynchronous INPUT9 eCAP3
Synchronous Input X-BAR
INPUT10 eCAP4
GPIOx Sync. + Qual.
INPUT11 eCAP5
INPUT12 eCAP6
INPUT14
INPUT13
INPUT6
INPUT5
INPUT4
INPUT3
INPUT2
INPUT1
TZ1,TRIP1
XINT5 TZ2,TRIP2
XINT4 TZ3,TRIP3
CPU PIE
XINT3
CLA XINT2 TRIP4
XINT1 TRIP5
TRIP7 ePWM
ePWM TRIP8 Modules
X-BAR TRIP9
TRIP10
TRIP11
TRIP12
TRIP6
ADC ADCEXTSOC
EXTSYNCIN1 ePWM and eCAP
EXTSYNCIN2 Sync Chain
Output X-BAR
Figure 4-7. Input X-BAR
Table 4-5. Input X-BAR Destinations

INPUT DESTINATIONS
INPUT1 EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR
INPUT4 XINT1, EPWM X-BAR, Output X-BAR
INPUT5 XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR
INPUT6 XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR
INPUT7 ECAP1
INPUT8 ECAP2
INPUT9 ECAP3
INPUT10 ECAP4
INPUT11 ECAP5
INPUT12 ECAP6
INPUT13 XINT4
INPUT14 XINT5

TMS320F28379S, TMS320F28377S
4.5.3 Output X-BAR and ePWM X-BAR

The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The
ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for
both the Output X-BAR and ePWM X-BAR are shown in Figure 4-8. For details on the Output X-BAR and
ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xS Delfino Microcontrollers
Technical Reference Manual.
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)
ePWM and eCAP EXTSYNCOUT

Sync Chain
OUTPUT1
OUTPUT2
ADCSOCAO ADCSOCAO OUTPUT3
Select Ckt Output OUTPUT4 GPIO
X-BAR
OUTPUT5 Mux
ADCSOCBO OUTPUT6
ADCSOCBO OUTPUT7
Select Ckt OUTPUT8
eCAPx ECAPxOUT
EVT1
EVT2
ADCx EVT3 TRIP4
EVT4 TRIP5
TRIP7 All
INPUT1 ePWM TRIP8
ePWM
INPUT2 X-BAR TRIP9
TRIP10
Modules
INPUT3
INPUT4 TRIP11
Input X-Bar TRIP12
INPUT5
INPUT6
OTHER DESTINATIONS
(see Input X-BAR)
X-BAR Flags
FLT1.COMPH (shared)
FLT1.COMPL
SDFMx
FLT4.COMPH
FLT4.COMPL
Figure 4-8. Output X-BAR and ePWM X-BAR

TMS320F28379S, TMS320F28377S
4.5.4 USB Pin Muxing

Table 4-6 shows assignment of the alternate USB function mapping. These can be configured with the
GPBAMSEL register.
Table 4-6. Alternate USB Function

GPIO GPBAMSEL SETTING USB FUNCTION
GPIO42 GPBAMSEL[10] = 1b USB0DM
GPIO43 GPBAMSEL[11] = 1b USB0DP
4.5.5 High-Speed SPI Pin Muxing

The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special
GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by
the SPI when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 4-7.
Table 4-7. GPIO Configuration for High-Speed SPI

GPIO SPI SIGNAL MUX CONFIGURATION
SPIA
GPIO58 SPISIMOA GPBGMUX2[21:20]=11b GPBMUX2[21:20]=11b
GPIO59 SPISOMIA GPBGMUX2[23:22]=11b GPBMUX2[23:22]=11b
GPIO60 SPICLKA GPBGMUX2[25:24]=11b GPBMUX2[25:24]=11b
GPIO61 SPISTEA GPBGMUX2[27:26]=11b GPBMUX2[27:26]=11b
SPIB
GPIO63 SPISIMOB GPBGMUX2[31:30]=11b GPBMUX2[31:30]=11b
GPIO64 SPISOMIB GPCGMUX1[1:0]=11b GPCMUX1[1:0]=11b
GPIO65 SPICLKB GPCGMUX1[3:2]=11b GPCMUX1[3:2]=11b
GPIO66 SPISTEB GPCGMUX1[5:4]=11b GPCMUX1[5:4]=11b
SPIC
GPIO69 SPISIMOC GPCGMUX1[11:10]=11b GPCMUX1[11:10]=11b
GPIO70 SPISOMIC GPCGMUX1[13:12]=11b GPCMUX1[13:12]=11b
GPIO71 SPICLKC GPCGMUX1[15:14]=11b GPCMUX1[15:14]=11b
GPIO72 SPISTEC GPCGMUX1[17:16]=11b GPCMUX1[17:16]=11b

TMS320F28379S, TMS320F28377S
5 Specifications
5.1 Absolute Maximum Ratings (1) (2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDDIO with respect to VSS –0.3 4.6
VDD3VFL with respect to VSS –0.3 4.6
Supply voltage V
VDDOSC with respect to VSS –0.3 4.6
VDD with respect to VSS –0.3 1.5
Analog voltage VDDA with respect to VSSA –0.3 4.6 V
Input voltage VIN (3.3 V) –0.3 4.6 V
Output voltage VO –0.3 4.6 V
Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO) –20 20
Analog input (per pin), IIKANALOG
–20 20
Input clamp current (VIN < VSSA or VIN > VDDA) mA
Total for all inputs, IIKTOTAL
–20 20
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current Digital output (per pin), IOUT –20 20 mA
Free-Air temperature TA –40 125 °C
Operating junction temperature TJ –40 150 °C
(3)
Storage temperature Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see Semiconductor and IC Package Thermal Metrics.
5.2 ESD Ratings

VALUE UNIT
TMS320F2837xS in 337-ball ZWT package
Human body model (HBM), per All pins ±2000
AEC Q100-002 (1)
V(ESD) Electrostatic discharge Charged device model (CDM), All pins ±500 V
per AEC Q100-011
Corner balls on 337-ball ZWT: ±750
A1, A19, W1, W19
TMS320F2837xS in 176-pin PTP package
AEC Q100-002 (1)
per AEC Q100-011
Corner pins on 176-pin PTP: ±750
1, 44, 45, 88, 89, 132, 133, 176
TMS320F2837xS in 100-pin PZP package
AEC Q100-002 (1)
per AEC Q100-011
Corner pins on 100-pin PZP: ±750
1, 25, 26, 50, 51, 75, 76, 100
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Copyright © 2014–2016, Texas Instruments Incorporated Specifications 47

TMS320F28379S, TMS320F28377S
5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.47 V
Device supply voltage, VDD 1.14 1.2 1.26 V
Supply ground, VSS 0 V
Analog supply voltage, VDDA 3.14 3.3 3.47 V
Analog ground, VSSA 0 V
T version –40 105
Junction temperature, TJ S version (2) –40 125 °C
(2)
Q version (Q100 qualification) –40 150
Free-Air temperature, TA Q version (Q100 qualification) –40 125 °C
(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
48 Specifications Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
5.4 Power Consumption Summary

Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Table 5-1 shows the device current consumption at 200-MHz SYSCLK.
Table 5-1. Device Current Consumption at 200-MHz SYSCLK

IDD IDDIO (1) IDDA IDD3VFL
MODE TEST CONDITIONS (2) (3)
TYP MAX TYP (2) MAX (3) TYP (2) MAX (3) TYP (2) MAX (3)
• Code is running out of RAM. (4)

• All I/O pins are left unconnected.
Operational • Peripherals not active have their 245 mA 360 mA 30 mA 13 mA 20 mA 33 mA 40 mA
(RAM) clocks disabled.
• FLASH is read and in active state.
• XCLKOUT is enabled at SYSCLK/4.
• CPU1 is in IDLE mode.

IDLE • Flash is powered down. 80 mA 185 mA 3 mA 10 mA 10 µA 150 µA 10 µA 150 µA
• XCLKOUT is turned off.
• CPU1 is in STANDBY mode.

STANDBY • Flash is powered down. 30 mA 135 mA 3 mA 10 mA 5 µA 150 µA 10 µA 150 µA
• CPU1 watchdog is running.

HALT • Flash is powered down. 1.5 mA 110 mA 750 µA 2 mA 5 µA 150 µA 10 µA 150 µA
HIBERNATE • CPU1.M0 and CPU1.M1 RAMs are in 300 µA 4 mA 750 µA 2 mA 5 µA 75 µA 1 µA 50 µA

low-power data retention mode.
• CPU1 is running from RAM.

• All I/O pins are left unconnected.
Flash • Peripheral clocks are disabled. 154 mA 230 mA 3 mA 10 mA 10 µA 150 µA 45 mA 55 mA
Erase/Program
• CPU1 is performing Flash Erase and
Programming.
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) TYP: Vnom, 30°C
(3) MAX: Vmax, 125°C
(4) The following is executed in a loop on CPU1:
• All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
• SDFM1 to SDFM4 active
• ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
• CPU TIMERs active
• DMA does 32-bit burst transfers
• CLA1 does multiply-accumulate tasks
• All ADCs perform continuous conversion
• All DACs ramp voltage up/down at 150 kHz
• CMPSS1 to CMPSS8 active
• VCU does complex multiply/accumulate with parallel load
• TMU calculates a cosine
• FPU does multiply/accumulate with parallel load

TMS320F28379S, TMS320F28377S
5.4.1 Current Consumption Graphs

Figure 5-1 and Figure 5-2 are a typical representation of the relationship between frequency and current
consumption/power on the device. The operational test from Table 5-1 was run across frequency at Vmax
and high temperature. Actual results will vary based on the system implementation and conditions.
0.5
0.45
0.4
0.35
0.3
0.25
Current (A)
0.2
0.15
0.1
0.05
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
VDD VDDIO VDDA VDD3VFL
Figure 5-1. Operational Current Versus Frequency
1
0.9
0.8
0.7
0.6
0.5
Power (W)
0.4
0.3
0.2
0.1
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
Power
Figure 5-2. Power Versus Frequency

TMS320F28379S, TMS320F28377S
Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD
current between TYP and MAX conditions can be seen in Figure 5-3. The current consumption in HALT
mode is primarily leakage current as there is no active switching if the internal oscillator has been powered
down.
Figure 5-3 shows the typical leakage current across temperature. The device was placed into HALT mode
under nominal voltage conditions.
Figure 5-3. IDD Leakage Current Versus Temperature

TMS320F28379S, TMS320F28377S
5.4.2 Reducing Current Consumption

The F2837xS devices provide some methods to reduce the device current consumption:
• Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered
during idle periods in the application.
• The flash module may be powered down if the code is run from RAM.
• Disable the pullups on pins that assume an output function.
• Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 5-2
indicates the typical current reduction that may be achieved by disabling the clocks using the
PCLKCRx register.
Table 5-2. Current on VDD Supply by Various

Peripherals (at 200 MHz) (1)
PERIPHERAL IDD CURRENT
MODULE (2) REDUCTION (mA)
ADC (3) 3.3
CAN 3.3
CLA 1.4
CMPSS (3) 1.4
CPUTIMER 0.3
(3)
DAC 0.6
DMA 2.9
eCAP 0.6
EMIF1 2.9
EMIF2 2.6
ePWM1 to ePWM4 (4) 4.5
(4)
ePWM5 to ePWM12 1.7
HRPWM (4) 1.7
I2C 1.3
McBSP 1.6
SCI 0.9
SDFM 2
SPI 0.5
uPP 7.3
USB and AUXPLL at 60 MHz 23.8
(1) At Vmax and 125°C.

(2) All peripherals are disabled upon reset. Use the PCLKCRx register
to individually enable peripherals. For peripherals with multiple
instances, the current quoted is for a single module.
(3) This number represents the current drawn by the digital portion of
the ADC, CMPSS, and DAC modules.
(4) The ePWM is at /2 of SYSCLK.

TMS320F28379S, TMS320F28377S
5.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
IOH = IOH MIN VDDIO * 0.8
VOH High-level output voltage V
IOH = –100 μA VDDIO – 0.2
IOL = IOL MAX 0.4
VOL Low-level output voltage V
IOL = 100 µA 0.2
High-level output source current for all output
IOH –4 mA
pins
IOL Low-level output sink current for all output pins 4 mA
GPIO0–GPIO7,
High-level input voltage GPIO42–GPIO43, VDDIO * 0.7 VDDIO + 0.3
VIH GPIO46–GPIO47 V
(3.3 V)
All other pins 2.0 VDDIO + 0.3
VIL Low-level input voltage (3.3 V) VSS – 0.3 0.8 V
Digital inputs with VDDIO = 3.3 V
Ipulldown Input current 120 µA
pulldown (1) VIN = VDDIO
Digital inputs with VDDIO = 3.3 V
Ipullup Input current 150 µA
pullup enabled (1) VIN = 0 V
Pullups disabled
Digital 2
0 V ≤ VIN ≤ VDDIO
Analog (except
ILEAK Pin leakage ADCINB0 or 2 µA
DACOUTx)
0 V ≤ VIN ≤ VDDA
ADCINB0 2 11 (2)
DACOUTx 66
CI Input capacitance 2 pF
(1) See Table 4-2 for a list of pins with a pullup or pulldown.
(2) The MAX input leakage shown on ADCINB0 is at high temperature.

TMS320F28379S, TMS320F28377S
5.6 Thermal Resistance Characteristics
5.6.1 ZWT Package

°C/W (1) AIR FLOW (lfm) (2)
RΘJC Junction-to-case thermal resistance 8.3 N/A
RΘJB Junction-to-board thermal resistance 11.6 N/A
RΘJA (High k PCB) Junction-to-free air thermal resistance 21.5 0
19.0 150
RΘJMA Junction-to-moving air thermal resistance 17.8 250
16.5 500
0.2 0
0.3 150
PsiJT Junction-to-package top
0.4 250
0.5 500
11.4 0
11.3 150
PsiJB Junction-to-board
11.2 250
11.0 500
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
5.6.2 PTP Package

12.8 150
10.1 500
0.11 0
0.24 150
0.33 250
0.42 500
6.1 0
5.5 150
5.4 250
5.3 500

TMS320F28379S, TMS320F28377S
5.6.3 PZP Package

14.3 150
11.4 500
0.03 0
0.09 150
0.12 250
0.20 500
6.0 0
5.5 150
5.5 250
5.3 500

TMS320F28379S, TMS320F28377S
5.7 System
5.7.1 Power Sequencing

An external power supply must be used to supply 3.3 V to VDDIO, VDD3VFL, VDDOSC, and VDDA and to
provide 1.2 V to VDD. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high
to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 5-3 shows the supply ramp rate.
Table 5-3. Supply Ramp Rate

MIN MAX UNIT
5
Supply ramp rate VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS 330 10 V/s
The voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times. VDDIO,
VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during
operation. Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any
digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance
state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on
the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.
5.7.2 Reset Timing

XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in
power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI
watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should
be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These
values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the
watchdog reset is asserted. Figure 5-4 shows the recommended reset circuit.
VDDIO
2.2 kW – 10 kW
XRS
£100 nF
Figure 5-4. Reset Circuit

TMS320F28379S, TMS320F28377S
5.7.2.1 Reset Sources

The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and
HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xS Delfino
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources
will drive XRS low. Use this to disable any other devices driving the boot pins.
The SCCRESET and debugger reset sources do not drive XRS; therefore, the
pins used for boot mode should not be actively driven by other devices in the
system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2837xS Delfino Microcontrollers
5.7.2.2 Reset Electrical Data and Timing

Table 5-4 shows the reset (XRS) timing requirements. Table 5-5 shows the reset (XRS) switching
characteristics. Figure 5-5 shows the power-on reset. Figure 5-6 shows the warm reset.
Table 5-4. Reset (XRS) Timing Requirements

MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1.5 ms
tw(RSL2) Pulse duration, XRS low on warm reset 3.2 µs
Table 5-5. Reset (XRS) Switching Characteristics

Pulse duration, XRS driven low by device after supplies are
tw(RSL1) 100 µs
stable
tw(WDRS) Pulse duration, reset pulse generated by watchdog 512tc(OSCCLK) cycles

TMS320F28379S, TMS320F28377S
VDDIO, VDDA
(3.3 V)
VDD (1.2 V)
tw(RSL1)
(A)
XRS
Boot ROM
CPU
Execution
Phase
User-code
th(boot-mode)(B) User-code dependent
Boot-Mode
GPIO pins as input
Pins
Peripheral/GPIO function
Boot-ROM execution starts
Based on boot code
I/O Pins GPIO pins as input (pullups are disabled)
User-code dependent
A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 4-1. On-chip POR logic
will hold this pin low until the supplies are in a valid range.
B. After reset from any source (see Section 5.7.2.1), the boot ROM code samples Boot Mode pins. Based on the status
of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code
executes after power-on conditions (in debugger environment), the boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 5-5. Power-on Reset
tw(RSL2)
XRS
User Code
CPU
Execution User Code Boot ROM
Phase
Boot-ROM execution starts
(initiated by any reset source) th(boot-mode)(A)
Boot-Mode
Peripheral/GPIO Function GPIO Pins as Input Peripheral/GPIO Function
Pins
User-Code Execution Starts
I/O Pins User-Code Dependent GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see Section 5.7.2.1), the Boot ROM code samples BOOT Mode pins. Based on the
status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code
executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 5-6. Warm Reset

TMS320F28379S, TMS320F28377S
5.7.3 Clock Specifications
5.7.3.1 Clock Sources

Table 5-6 lists four possible clock sources. Figure 5-7 provides an overview of the device's clocking
system.
Table 5-6. Possible Reference Clock Sources

CLOCK SOURCE MODULES CLOCKED COMMENTS
INTOSC1 Can be used to provide clock for: Internal oscillator 1.
• Watchdog block Zero-pin overhead 10-MHz internal oscillator.
• Main PLL
• CPU-Timer 2
INTOSC2 (1) Can be used to provide clock for: Internal oscillator 2.
• Main PLL Zero-pin overhead 10-MHz internal oscillator.
• Auxiliary PLL
• CPU-Timer 2
XTAL Can be used to provide clock for: External crystal or resonator connected between the X1 and X2 pins
• Main PLL or single-ended clock connected to the X1 pin.
• Auxiliary PLL
• CPU-Timer 2
AUXCLKIN Can be used to provide clock for: Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
• Auxiliary PLL should be used to provide the input clock.
• CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).

TMS320F28379S, TMS320F28377S
INTOSC1 WDCLK To watchdog timer
INTOSC2 CLKSRCCTL1 SYSPLLCTL1 SYSCLKDIVSEL
SYSCLK To GS RAMs, GPIOs,

OSCCLK PLLSYSCLK
Divider and NMIWDs
X1(XTAL) System PLL PLLRAWCLK
SYSCLK CPU CPU1.CPUCLK To local memories
To ePIEs, LS RAMs,
CPU1.SYSCLK CLA message RAMs,
and DCSMs
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK To peripherals
One per LSPCLK peripheral

LOSPCP
PCLKCRx
To SCIs, SPIs, and

LSP PERx.LSPCLK
LSPCLK McBSPs
Divider
One per ePWM
EPWMCLKDIV PCLKCRx
PLLSYSCLK /1 EPWMCLK To ePWMs

/2
HRPWM
PCLKCRx
HRPWMCLK To HRPWMs
One per CAN module
CLKSRCCTL2
CAN Bit Clock To CANs

AUXCLKIN
CLKSRCCTL2 AUXPLLCTL1 AUXCLKDIVSEL
AUXCLK
AUXOSCCLK AUXPLLCLK To USB bit clock
Divider
Auxiliary PLL AUXPLLRAWCLK
Figure 5-7. Clocking System

TMS320F28379S, TMS320F28377S
5.7.3.2 Clock Frequencies, Requirements, and Characteristics

This section provides the frequencies and timing requirements of the input clocks, PLL lock times,
frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.
5.7.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 5-7 shows the frequency requirements for the input clocks. Table 5-16 shows the crystal equivalent
series resistance requirements. Table 5-8 shows the X1 input level characteristics when using an external
clock source. Table 5-9 and Table 5-10 show the timing requirements for the input clocks. Table 5-11
shows the PLL lock times for the Main PLL and the USB PLL.
Table 5-7. Input Clock Frequency

MIN MAX UNIT
f(XTAL) Frequency, X1/X2, from external crystal or resonator 10 20 MHz
Frequency, X1, from external oscillator (PLL enabled) 2 20 MHz
f(X1)
Frequency, X1, from external oscillator (PLL disabled) 2 100 MHz
f(AUXI) Frequency, AUXCLKIN, from external oscillator 2 60 MHz
Table 5-8. X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
PARAMETER MIN MAX UNIT
X1 VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
X1 VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V
Table 5-9. X1 Timing Requirements

MIN MAX UNIT
tf(X1) Fall time, X1 6 ns
tr(X1) Rise time, X1 6 ns
tw(X1L) Pulse duration, X1 low as a percentage of tc(X1) 45% 55%
tw(X1H) Pulse duration, X1 high as a percentage of tc(X1) 45% 55%
Table 5-10. AUXCLKIN Timing Requirements

MIN MAX UNIT
tf(AUXI) Fall time, AUXCLKIN 6 ns
tr(AUXI) Rise time, AUXCLKIN 6 ns
tw(AUXL) Pulse duration, AUXCLKIN low as a percentage of tc(XCI) 45% 55%
tw(AUXH) Pulse duration, AUXCLKIN high as a percentage of tc(XCI) 45% 55%
Table 5-11. PLL Lock Times

MIN NOM MAX UNIT
(1)
t(PLL) Lock time, Main PLL (X1, from external oscillator) 50 µs + 2500 * tc(OSCCLK) µs
t(USB) Lock time, USB PLL (AUXCLKIN, from external oscillator) 50 µs + 2500 * tc(OSCCLK) (1) µs
(1) The PLL lock time here includes the two required PLL lock sequences. Cycle count includes code execution of the PLL initialization
routine, which could vary depending on compiler optimizations and flash wait states.

TMS320F28379S, TMS320F28377S
5.7.3.2.2 Internal Clock Frequencies

Table 5-12 provides the clock frequencies for the internal clocks.
Table 5-12. Internal Clock Frequencies

MIN NOM MAX UNIT
f(SYSCLK) Frequency, device (system) clock 2 200 MHz
tc(SYSCLK) Period, device (system) clock 5 500 ns
Frequency, system PLL output (before SYSCLK
f(PLLRAWCLK) 120 400 MHz
divider)
Frequency, auxiliary PLL output (before AUXCLK
f(AUXPLLRAWCLK) 120 400 MHz
divider)
f(AUXPLL) Frequency, AUXPLLCLK 60 60 MHz
f(PLL) Frequency, PLLSYSCLK 2 200 MHz
(1)
f(LSP) Frequency, LSPCLK 2 200 MHz
tc(LSPCLK) Period, LSPCLK 5 500 ns
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
f(OSCCLK) See respective clock MHz
XTAL or X1)
f(EPWM) Frequency, EPWMCLK (2) 100 MHz
f(HRPWM) Frequency, HRPWMCLK 60 100 MHz
(1) Lower LSPCLK will reduce device power consumption. The default at reset is SYSCLK/4.
(2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
5.7.3.2.3 Output Clock Frequency and Switching Characteristics

Table 5-13 provides the frequency of the output clock. Table 5-14 shows the switching characteristics of
the output clock, XCLKOUT.
Table 5-13. Output Clock Frequency

MIN MAX UNIT
f(XCO) Frequency, XCLKOUT 50 MHz
Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
tf(XCO) Fall time, XCLKOUT 5 ns
tr(XCO) Rise time, XCLKOUT 5 ns
tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns
tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)

TMS320F28379S, TMS320F28377S
5.7.3.3 Input Clocks and PLLs

In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 5-8
shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also
referred to as XTAL) and AUXCLKIN.
X1 vssosc X2 X1 vssosc X2
RESONATOR
CRYSTAL
RD C L2 C L1
X1 vssosc X2 GPIO133/AUXCLKIN
NC
3.3V CLK 3.3V CLK
VDD OUT VDD OUT
GND GND
3.3V OSCILLATOR 3.3V OSCILLATOR
Figure 5-8. Connecting Input Clocks to a 2837xS Device

TMS320F28379S, TMS320F28377S
5.7.3.4 Crystal Oscillator

When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should
be as small as possible because the size of the resistance affects start-up time (smaller RD = faster start-
up time). TI recommends that the crystal manufacturer characterize the crystal with the application board.
Table 5-15 shows the crystal oscillator parameters. Table 5-16 shows the crystal equivalent series
resistance (ESR) requirements. Table 5-17 shows the crystal oscillator electrical characteristics.
Table 5-15. Crystal Oscillator Parameters

MIN MAX UNIT
CL1, CL2 Load capacitance 12 24 pF
C0 Crystal shunt capacitance 7 pF
Table 5-16. Crystal Equivalent Series Resistance (ESR) Requirements (1) (2)
MAXIMUM ESR (Ω) MAXIMUM ESR (Ω)
CRYSTAL FREQUENCY (MHz)
(CL1 = CL2 = 12 pF) (CL1 = CL2 = 24 pF)
10 55 110
12 50 95
14 50 90
16 45 75
18 45 65
20 45 50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
Table 5-17. Crystal Oscillator Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 20 MHz
ESR MAX = 50 Ω
Start-up time (1) 2 ms
CL1 = CL2 = 24 pF
C0 = 7 pF
Crystal drive level (DL) 1 mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.

TMS320F28379S, TMS320F28377S
5.7.3.5 Internal Oscillators

To reduce production board costs and application development time, all F2837xS devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are
enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and
INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system
reference clock (OSCCLK). Table 5-18 provides the electrical characteristics of the internal oscillators to
determine if this module meets the clocking requirements of the application.
Table 5-18 provides the electrical characteristics of the two internal oscillators.
NOTE
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to
frequencies above 194 MHz.
Table 5-18. Internal Oscillator Electrical Characteristics

f(INTOSC) Frequency, INTOSC1 and INTOSC2 9.7 10.3 MHz
Frequency stability at room temperature 30°C ±0.1%
tOSCST Start-up and settling time 22 µs

TMS320F28379S, TMS320F28377S
5.7.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash
through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal
to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of
approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2×
improvement in performance when migrating from the previous generation Delfino MCUs. Note that an
extra wait state is automatically added when code is fetched or data is read from Bank 1 (compared to
that of Bank 0), even for prefetched data.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module
(DCSM), which cannot be erased after it is programmed.
Table 5-19 shows the minimum required flash wait states at different frequencies. Table 5-20 shows the
flash parameters at 200 MHz. Table 5-21 shows the flash/OTP endurance. Table 5-22 shows the flash
data retention duration.
Table 5-19. Flash Wait States

CPUCLK (MHz) (1)
MINIMUM WAIT STATES
EXTERNAL OSCILLATOR OR CRYSTAL INTOSC1 OR INTOSC2
150 < CPUCLK ≤ 200 145 < CPUCLK ≤ 194 3
100 < CPUCLK ≤ 150 97 < CPUCLK ≤ 145 2
50 < CPUCLK ≤ 100 48 < CPUCLK ≤ 97 1
CPUCLK ≤ 50 CPUCLK ≤ 48 0
(1) Minimum required FRDCNTL[RWAIT].
Table 5-20. Flash Parameters at 200 MHz (1)

128 data bits + 16 ECC bits 40 300 µs
(2)
Program Time 8KW sector 90 180 ms
32KW sector 360 720 ms
Erase Time (3) 8KW sector 25 50
ms
at < 25 cycles 32KW sector 30 55
Erase Time (3) 8KW sector 105 4000
ms
at 50k cycles 32KW sector 110 4000
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Program time includes overhead of the flash state machine but does not include the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the emulator used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(3) Erase time includes Erase verify by the CPU.

TMS320F28379S, TMS320F28377S
Table 5-21. Flash/OTP Endurance

MIN TYP MAX UNIT
Nf Flash endurance for the array (write/erase cycles) 20000 50000 cycles
Table 5-22. Flash Data Retention Duration

PARAMETER TEST CONDITIONS MIN MAX UNIT
tretention Data retention duration TJ = 85°C 20 years

TMS320F28379S, TMS320F28377S
5.7.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always
be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0
and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always
be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 5-9 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 5-10
shows how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4
are not used and should be grounded.
The PD (Power Detect) terminal of the emulator header should be connected to the board 3.3-V supply.
Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also
be connected to board ground. The JTAG clock should be looped from the header TCK output terminal
back to the RTCK input terminal of the header (to sense clock continuity by the emulator). Header terminal
RESET is an open-drain output from the emulator header that enables board components to be reset
through emulator commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the
JTAG header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain.
Otherwise, each signal should be buffered. Additionally, for most emulator operations at 10 MHz, no
series resistors are needed on the JTAG signals. However, if high emulation speeds are expected
(35 MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.
See the XDS Target Connection Guide for more information about JTAG emulation.
Distance between the header and the target

should be less than 6 inches (15.24 cm).
2.2 kW
TRST GND
1 2
TMS TMS TRST
3 4
TDI TDI TDIS GND
100 W
MCU 5 6
3.3 V PD KEY
7 8
TDO TDO GND
9 10
RTCK GND
TCK 11 12
TCK GND
4.7 kW 4.7 kW
13 14
3.3 V EMU0 EMU1 3.3 V
Figure 5-9. Connecting to the 14-Pin JTAG Header

TMS320F28379S, TMS320F28377S
Distance between the header and the target

should be less than 6 inches (15.24 cm). 2.2 kW
TRST GND
1 2
TMS TMS TRST
3 4
TDI TDI TDIS GND
100 W
MCU 5 6
3.3V PD KEY
7 8
TDO TDO GND
9 RTCK GND 10
11 12
TCK TCK GND
4.7 kW 4.7 kW
3.3 V 13 EMU0 EMU1 14 3.3 V
15 16
RESET GND
open
drain 17 18
EMU2 EMU3
A low pulse from the emulator 19 20

EMU4 GND
can be tied with other reset
sources to reset the board. GND GND
Figure 5-10. Connecting to the 20-Pin JTAG Header

TMS320F28379S, TMS320F28377S
5.7.5.1 JTAG Electrical Data and Timing

Table 5-23 lists the JTAG timing requirements. Table 5-24 lists the JTAG switching characteristics.
Figure 5-11 shows the JTAG timing.
Table 5-23. JTAG Timing Requirements

NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 66.66 ns
1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.66 ns
1b tw(TCKL) Pulse duration, TCK low (40% of tc) 26.66 ns
tsu(TDI-TCKH) Input setup time, TDI valid to TCK high 13 ns
3
tsu(TMS-TCKH) Input setup time, TMS valid to TCK high 13 ns
th(TCKH-TDI) Input hold time, TDI valid from TCK high 7 ns
4
th(TCKH-TMS) Input hold time, TMS valid from TCK high 7 ns
Table 5-24. JTAG Switching Characteristics

NO. PARAMETER MIN MAX UNIT
2 td(TCKL-TDO) Delay time, TCK low to TDO valid 6 25 ns
1
1a 1b
TCK
TDO
3 4
TDI/TMS
Figure 5-11. JTAG Timing

TMS320F28379S, TMS320F28377S
5.7.6 GPIO Electrical Data and Timing

The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO
pins are configured as inputs. For specific inputs, the user can also select the number of input qualification
cycles to filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed
to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an
Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s),
eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
5.7.6.1 GPIO - Output Timing

Table 5-25 shows the general-purpose output switching characteristics. Figure 5-12 shows the general-
purpose output timing.
Table 5-25. General-Purpose Output Switching Characteristics

tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 (1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 8 (1) ns
tfGPO Toggling frequency, GPO pins 25 MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPO)
tf(GPO)
Figure 5-12. General-Purpose Output Timing

TMS320F28379S, TMS320F28377S
5.7.6.2 GPIO - Input Timing

Table 5-26 shows the general-purpose input timing requirements. Figure 5-13 shows the sampling mode.
Table 5-26. General-Purpose Input Timing Requirements

MIN MAX UNIT
QUALPRD = 0 1tc(SYSCLK) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SYSCLK) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n (1) – 1) cycles
(2)
Synchronous mode 2tc(SYSCLK) cycles
tw(GPI) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)
1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window (SYSCLK cycle * 2 * QUALPRD) * 5
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n",
the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be
sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide
pulse ensures reliable recognition.
Figure 5-13. Sampling Mode

TMS320F28379S, TMS320F28377S
5.7.6.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 5-14 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 5-14. General-Purpose Input Timing

TMS320F28379S, TMS320F28377S
5.7.7 Interrupts
Figure 5-15 provides a high-level view of the interrupt architecture.
As shown in Figure 5-15, the devices support five external interrupts (XINT1 to XINT5) that can be
mapped onto any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU
interrupt groups, with 16 interrupts per group.
CPU1.TINT0
CPU1.TIMER0
LPM Logic CPU1.LPMINT

CPU1.W AKEINT
CPU1.WD NMI
CPU1.W DINT CPU1.NMIWD
CPU1
INPUTXBAR4 CPU1.XINT1 Control
GPIO0
GPIO1 INPUTXBAR5 CPU1.XINT2 Control INT1
...
Input CPU1.XINT3 Control
CPU1. to
INPUTXBAR6
... X-BAR CPU1.XINT4 Control
ePIE INT12
INPUTXBAR13
GPIOx
INPUTXBAR14 CPU1.XINT5 Control
CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
CPU1.TIMER2 INT14
Peripherals
Figure 5-15. External and ePIE Interrupt Sources

TMS320F28379S, TMS320F28377S
5.7.7.1 External Interrupt (XINT) Electrical Data and Timing

Table 5-27 lists the external interrupt timing requirements. Table 5-28 lists the external interrupt switching
characteristics. Figure 5-16 shows the external interrupt timing.
Table 5-27. External Interrupt Timing Requirements (1)

MIN MAX UNIT
Synchronous 2tc(SYSCLK) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Table 5-26.
Table 5-28. External Interrupt Switching Characteristics (1)

td(INT) Delay time, INT low/high to interrupt-vector fetch (2) tw(IQSW) + 14tc(SYSCLK) tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(2) This assumes that the ISR is in a single-cycle memory.
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
Interrupt Vector
(internal)
Figure 5-16. External Interrupt Timing

TMS320F28379S, TMS320F28377S
5.7.8 Low-Power Modes

This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low Power Modes section of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
5.7.8.1 Clock-Gating Low-Power Modes

IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 5-29
describes the effect on the system when any of the clock-gating low-power modes are entered.
Table 5-29. Effect of Clock-Gating Low-Power Modes on the Device

MODULES/
CPU1 IDLE CPU1 STANDBY HALT
CLOCK DOMAIN
CPU1.CLKIN Active Gated Gated
CPU1.SYSCLK Active Gated Gated
CPU1.CPUCLK Gated Gated Gated
Clock to modules Connected to Active Gated Gated
PERx.SYSCLK
CPU1.WDCLK Active Active Gated if CLKSRCCTL1.WDHALTI = 0
AUXPLLCLK Active Active Gated
PLL Powered Powered Software must power down PLL before
entering HALT
INTOSC1 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
INTOSC2 Powered Powered Powered down if CLKSRCCTL1.WDHALTI = 0
Flash Powered Powered Software-Controlled
X1/X2 Crystal Oscillator Powered Powered Powered-Down
5.7.8.2 Power-Gating Low-Power Modes

HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the
supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote
wakeup capability, and can be used to save power during long periods of inactivity. Table 5-30 describes
the effects on the system when the HIBERNATE mode is entered.
Table 5-30. Effect of Power-Gating Low-Power Mode on the Device

MODULES/POWER DOMAINS HIBERNATE
M0 and M1 memories ● Remain on with memory retention if LPMCR.M0M1MODE = 0x00
● Are off when LPMCR.M0M1MODE = 0x01
CPU1 digital peripherals Powered down
Dx, LSx, GSx memories Power down, memory contents are lost
IOs On with output state preserved
Oscillators, PLL, analog Enters Low-Power Mode
peripherals, Flash

TMS320F28379S, TMS320F28377S
5.7.8.3 Low-Power Mode Wakeup Timing

Table 5-31 shows the IDLE mode timing requirements, Table 5-32 shows the switching characteristics,
and Figure 5-17 shows the timing diagram for IDLE mode.
Table 5-31. IDLE Mode Timing Requirements (1)

MIN MAX UNIT
Without input qualifier 2tc(SYSCLK)
tw(WAKE) Pulse duration, external wake-up signal cycles
With input qualifier 2tc(SYSCLK) + tw(IQSW)
Table 5-32. IDLE Mode Switching Characteristics (1)

(2)
Delay time, external wake signal to program execution resume
• Wakeup from Flash Without input qualifier 40tc(SYSCLK)
– Flash module in active state With input qualifier 40tc(SYSCLK) + tw(WAKE)
td(WAKE-IDLE) • Wakeup from Flash Without input qualifier 6700tc(SYSCLK) (3) cycles
– Flash module in sleep state With input qualifier 6700tc(SYSCLK) (3) + tw(WAKE)
Without input qualifier 25tc(SYSCLK)
• Wakeup from RAM
With input qualifier 25tc(SYSCLK) + tw(WAKE)
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
(A)
WAKE
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK
cycles (minimum) is needed before the wake-up signal could be asserted.
Figure 5-17. IDLE Entry and Exit Timing Diagram

TMS320F28379S, TMS320F28377S
Table 5-33 shows the STANDBY mode timing requirements, Table 5-34 shows the switching
characteristics, and Figure 5-18 shows the timing diagram for STANDBY mode.
Table 5-33. STANDBY Mode Timing Requirements

MIN MAX UNIT
QUALSTDBY = 0 | 2tc(OSCCLK) 3tc(OSCCLK)
Pulse duration, external
tw(WAKE-INT) QUALSTDBY > 0 | cycles
wake-up signal (2 + QUALSTDBY) * tc(OSCCLK)
(2 + QUALSTDBY)tc(OSCCLK) (1)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
Table 5-34. STANDBY Mode Switching Characteristics

Delay time, IDLE instruction executed to
td(IDLE-XCOS) 16tc(INTOSC1) cycles
XCLKOUT stop
Delay time, external wake signal to
program execution resume (1)
• Wakeup from flash
175tc(SYSCLK) + tw(WAKE-INT)
– Flash module in active state
td(WAKE-STBY) cycles
• Wakeup from flash (2)
6700tc(SYSCLK) + tw(WAKE-INT)
– Flash module in sleep state
3tc(OSC) + 15tc(SYSCLK) +
• Wakeup from RAM tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.

TMS320F28379S, TMS320F28377S
(A) (C) (F)

(B) (D)(E) (G)
Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before
being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before
the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 5-18. STANDBY Entry and Exit Timing Diagram

TMS320F28379S, TMS320F28377S
Table 5-35 shows the HALT mode timing requirements, Table 5-36 shows the switching characteristics,
and Figure 5-19 shows the timing diagram for HALT mode.
Table 5-35. HALT Mode Timing Requirements

MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal (1) toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal (1) toscst + 8tc(OSCCLK) cycles
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Table 5-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 5.7.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
Table 5-36. HALT Mode Switching Characteristics

td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 16tc(INTOSC1) cycles
Delay time, external wake signal end to CPU1 program
execution resume
• Wakeup from flash
75tc(OSCCLK)
td(WAKE-HALT) – Flash module in active state cycles
• Wakeup from flash (1)
17500tc(OSCCLK)
– Flash module in sleep state
• Wakeup from RAM 75tc(OSCCLK)

TMS320F28379S, TMS320F28377S
(A) (C) (F)

(B) (D)(E) (G)
Device
HALT HALT
Status
Flushing Pipeline Normal

Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being
turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very
little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in
HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay
of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables
the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The
HALT mode is now exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 5-19. HALT Entry and Exit Timing Diagram

TMS320F28379S, TMS320F28377S
Table 5-37 shows the HIBERNATE mode timing requirements, Table 5-38 shows the switching
characteristics, and Figure 5-20 shows the timing diagram for HIBERNATE mode.
Table 5-37. HIBERNATE Mode Timing Requirements

MIN MAX UNIT
tw(HIBWAKE) Pulse duration, HIBWAKE signal 40 µs
tw(WAKEXRS) Pulse duration, XRS wake-up signal 40 µs
Table 5-38. HIBERNATE Mode Switching Characteristics

td(IDLE-XCOS) Delay time, IDLE instruction executed to XCLKOUT stop 30tc(SYSCLK) cycles
td(WAKE-HIB) Delay time, external wake signal to lORestore function start 1.5 ms

TMS320F28379S, TMS320F28377S
(A) (B) (C) (D) (F) (G)(H) (I)(J)

(E)
CPU1 HIB CPU1 IDLE

Device Status Device Active HIBERNATE CPU1 Boot ROM IoRestore() or Application Specific Operation
config Instruction
Td(WAKE-HIB)
GPIOHIBWAKEn,
XRSn
tw(HIBWAKEn),
tw(XRSn)
I/O Isolation
Bypassed &
PLLs Enabled Application SpecificOperation
Powered -Down
INTOSC1,INTOSC2,
On Powered Down Powering up On
X1/X2
XCLKCOUT Inactive Application Specific Operation
td(IDLE-XCOS)
A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if
using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank,
USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the
PLL and peripheral clocks before entering HIBERNATE.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained.
CPU1 is powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash
are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their
memory contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2,
and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of
these clock sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of
the remainder of the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the
CPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined
IoRestore function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O
isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the
application requirements.
I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will
disable I/O isolation automatically if it was not taken care of inside of IoRestore.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral
Booting chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more information.
Figure 5-20. HIBERNATE Entry and Exit Timing Diagram
NOTE
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue
its execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM
Code and Peripheral Booting chapter of the TMS320F2837xS Delfino Microcontrollers
Technical Reference Manual for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function.
Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is
not defined, the BootROM will automatically disable isolation before booting as
determined by the HIBBOOTMODE register.

TMS320F28379S, TMS320F28377S
5.7.9 External Memory Interface (EMIF)

The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).
5.7.9.1 Asynchronous Memory Support

The EMIF supports asynchronous memories:
• SRAMs
• NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access.
The EMIF module supports up to three chip selects (EMIF_CS[4:2]). Each chip select has the following
individually programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turnaround time
• Extended wait option with programmable time-out
• Select strobe option
5.7.9.2 Synchronous DRAM Support

The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit
data bus. The EMIF has a single SDRAM chip select (EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of
the program address bus and can only be accessed through the data bus, which places a restriction on
the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the
user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the
examples in controlSUITE™ (CONTROLSUITE) and the TMS320F2837xS Delfino Microcontrollers
SDRAM configurations supported are:
• One-bank, two-bank, and four-bank SDRAM devices
• Devices with 8-, 9-, 10-, and 11-column addresses
• CAS latency of two or three clock cycles
• 16-bit/32-bit data bus width
• 3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh
mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the
SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode
achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if
data retention is required. The EMIF module does not support mobile SDRAM devices.

TMS320F28379S, TMS320F28377S
5.7.9.3 EMIF Electrical Data and Timing
5.7.9.3.1 Asynchronous RAM

Table 5-39 shows the EMIF asynchronous memory timing requirements. Table 5-40 shows the EMIF
asynchronous memory switching characteristics. Figure 5-21 through Figure 5-24 show the EMIF
asynchronous memory timing diagrams.
Table 5-39. EMIF Asynchronous Memory Timing Requirements

NO. MIN MAX UNIT
Reads and Writes
E EMIF clock period tc(SYSCLK) ns
Pulse duration, EMxWAIT assertion and
2 tw(EM_WAIT) 2E ns
deassertion
Reads
12 tsu(EMDV-EMOEH) Setup time, EMxD[y:0] valid before EMxOE high 15 ns
13 th(EMOEH-EMDIV) Hold time, EMxD[y:0] valid after EMxOE high 0 ns
Setup Time, EMxWAIT asserted before end of
14 tsu(EMOEL-EMWAIT) 4E+20 ns
Strobe Phase (1)
Writes
Setup Time, EMxWAIT asserted before end of
28 tsu(EMWEL-EMWAIT) 4E+20 ns
Strobe Phase (1)
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 5-22 and Figure 5-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-40. EMIF Asynchronous Memory Switching Characteristics (1) (2) (3)
Reads and Writes
1 td(TURNAROUND) Turn around time (TA)*E–3 (TA)*E+2 ns
Reads
EMIF read cycle time (EW = 0) (RS+RST+RH+2)*E–3 (RS+RST+RH+2)*E+2 ns
3 tc(EMRCYCLE) (RS+RST+RH+2+ (RS+RST+RH+2+
EMIF read cycle time (EW = 1) ns
(EWC*16))*E–3 (EWC*16))*E+2
Output setup time, EMxCS[y:2] low
(RS)*E–3 (RS)*E+2 ns
to EMxOE low (SS = 0)
4 tsu(EMCEL-EMOEL)
–3 2 ns
to EMxOE low (SS = 1)
Output hold time, EMxOE high to
(RH)*E–3 (RH)*E ns
EMxCS[y:2] high (SS = 0)
5 th(EMOEH-EMCEH)
–3 0 ns
Output setup time, EMxBA[y:0]
6 tsu(EMBAV-EMOEL) (RS)*E–3 (RS)*E+2 ns
valid to EMxOE low
7 th(EMOEH-EMBAIV) (RH)*E–3 (RH)*E ns
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
8 tsu(EMAV-EMOEL) (RS)*E–3 (RS)*E+2 ns
to EMxOE low
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more
information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more information.
TMS320F28379S, TMS320F28377S
Table 5-40. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)

9 th(EMOEH-EMAIV) (RH)*E–3 (RH)*E ns
EMxA[y:0] invalid
EMxOE active low width (EW = 0) (RST)*E–1 (RST)*E+1 ns
10 tw(EMOEL)
EMxOE active low width (EW = 1) (RST+(EWC*16))*E–1 (RST+(EWC*16))*E+1 ns
Delay time from EMxWAIT
11 td(EMWAITH-EMOEH) 4E+10 5E+15 ns
deasserted to EMxOE high
Output setup time, EMxDQM[y:0]
29 tsu(EMDQMV-EMOEL) (RS)*E–3 (RS)*E+2 ns
valid to EMxOE low
30 th(EMOEH-EMDQMIV) (RH)*E–3 (RH)*E ns
EMxDQM[y:0] invalid
Writes
EMIF write cycle time (EW = 0) (WS+WST+WH+2)*E–3 (WS+WST+WH+2)*E+1 ns
15 tc(EMWCYCLE) (WS+WST+WH+2+ (WS+WST+WH+2+
EMIF write cycle time (EW = 1) ns
(EWC*16))*E–3 (EWC*16))*E+1
(WS)*E–3 (WS)*E+1 ns
to EMxWE low (SS = 0)
16 tsu(EMCEL-EMWEL)
–3 1 ns
to EMxWE low (SS = 1)
Output hold time, EMxWE high to
(WH)*E–3 (WH)*E ns
17 th(EMWEH-EMCEH)
–3 0 ns
Output setup time, EMxDQM[y:0]
18 tsu(EMDQMV-EMWEL) (WS)*E–3 (WS)*E+1 ns
valid to EMxWE low
19 th(EMWEH-EMDQMIV) (WH)*E–3 (WH)*E ns
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0]
20 tsu(EMBAV-EMWEL) (WS)*E–3 (WS)*E+1 ns
valid to EMxWE low
21 th(EMWEH-EMBAIV) (WH)*E–3 (WH)*E ns
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
22 tsu(EMAV-EMWEL) (WS)*E–3 (WS)*E+1 ns
to EMxWE low
23 th(EMWEH-EMAIV) (WH)*E–3 (WH)*E ns
EMxA[y:0] invalid
EMxWE active low width
(WST)*E–1 (WST)*E+1 ns
(EW = 0)
24 tw(EMWEL)
EMxWE active low width
(WST+(EWC*16))*E–1 (WST+(EWC*16))*E+1 ns
(EW = 1)
Delay time from EMxWAIT
25 td(EMWAITH-EMWEH) 4E+10 5E+15 ns
deasserted to EMxWE high
Output setup time, EMxD[y:0] valid
26 tsu(EMDV-EMWEL) (WS)*E–3 (WS)*E+1 ns
to EMxWE low
27 th(EMWEH-EMDIV) (WH)*E–3 (WH)*E ns
EMxD[y:0] invalid

TMS320F28379S, TMS320F28377S
3
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
4 5
8 9
6 7
29 30
10
EMxOE
13
12
EMxD[y:0]
EMxWE
Figure 5-21. Asynchronous Memory Read Timing
SETUP STROBE Extended Due to EMxWAIT STROBE HOLD

EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
14
11
EMxOE
2
2
EMxWAIT Asserted Deasserted
Figure 5-22. EMxWAIT Read Timing Requirements

TMS320F28379S, TMS320F28377S
15
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
16 17
18 19
20 21
24
22 23
EMxWE
27
26
EMxD[y:0]
EMxOE
Figure 5-23. Asynchronous Memory Write Timing
SETUP STROBE Extended Due to EMxWAIT STROBE HOLD

EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
28
25
EMxWE
2
2
EMxWAIT Asserted Deasserted
Figure 5-24. EMxWAIT Write Timing Requirements

TMS320F28379S, TMS320F28377S
5.7.9.3.2 Synchronous RAM

Table 5-41 shows the EMIF synchronous memory timing requirements. Table 5-42 shows the EMIF
synchronous memory switching characteristics. Figure 5-25 and Figure 5-26 show the synchronous
memory timing diagrams.
Table 5-41. EMIF Synchronous Memory Timing Requirements

NO. MIN MAX UNIT
19 tsu(EMIFDV-EM_CLKH) Input setup time, read data valid on EMxD[y:0] before EMxCLK rising 2 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMxD[y:0] after EMxCLK rising 1.5 ns
Table 5-42. EMIF Synchronous Memory Switching Characteristics

1 tc(CLK) Cycle time, EMIF clock EMxCLK 10 ns
2 tw(CLK) Pulse width, EMIF clock EMxCLK high or low 3 ns
3 td(CLKH-CSV) Delay time, EMxCLK rising to EMxCS[y:2] valid 8 ns
4 toh(CLKH-CSIV) Output hold time, EMxCLK rising to EMxCS[y:2] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMxCLK rising to EMxDQM[y:0] valid 8 ns
6 toh(CLKH-DQMIV) Output hold time, EMxCLK rising to EMxDQM[y:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid 8 ns
8 toh(CLKH-AIV) Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid 1 ns
9 td(CLKH-DV) Delay time, EMxCLK rising to EMxD[y:0] valid 8 ns
10 toh(CLKH-DIV) Output hold time, EMxCLK rising to EMxD[y:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMxCLK rising to EMxRAS valid 8 ns
12 toh(CLKH-RASIV) Output hold time, EMxCLK rising to EMxRAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMxCLK rising to EMxCAS valid 8 ns
14 toh(CLKH-CASIV) Output hold time, EMxCLK rising to EMxCAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMxCLK rising to EMxWE valid 8 ns
16 toh(CLKH-WEIV) Output hold time, EMxCLK rising to EMxWE invalid 1 ns
17 td(CLKH-DHZ) Delay time, EMxCLK rising to EMxD[y:0] tri-stated 8 ns
18 toh(CLKH-DLZ) Output hold time, EMxCLK rising to EMxD[y:0] driving 1 ns

TMS320F28379S, TMS320F28377S
BASIC SDRAM 1
READ OPERATION 2 2
EMxCLK
3 4
EMxCS[y:2]
5 6
EMxDQM[y:0]
7 8
EMxBA[y:0]
7 8
EMxA[y:0]
19
2 EM_CLK Delay
17 20 18
EMxD[y:0]
11 12
EMxRAS
13 14
EMxCAS
EMxWE
Figure 5-25. Basic SDRAM Read Operation

TMS320F28379S, TMS320F28377S
BASIC SDRAM 1
WRITE OPERATION 2 2
EMxCLK
3 4
EMxCS[y:2]
5 6
EMxDQM[y:0]
7 8
EMxBA[y:0]
7 8
EMxA[y:0]
9
10
EMxD[y:0]
11 12
EMxRAS
13
EMxCAS
15 16
EMxWE
Figure 5-26. Basic SDRAM Write Operation

TMS320F28379S, TMS320F28377S
5.8 Analog Peripherals

This analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
• Flexible voltage references
– VREFHIA and VREFLOA, VREFHIB and VREFLOB, VREFHIC and VREFLOC, and VREFHID and VREFLOD externally
supplied reference voltage pins
• Selectable by ADCs and buffered DACs
– VDAC externally supplied reference voltage pin
• Selectable by buffered DACs and comparator subsystem DACs
• Low reference is VSSA
• Flexible pin usage
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
• Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 5-27 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. Figure 5-28
shows the Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 5-29 shows the Analog
Subsystem Block Diagram for the 100-pin PZP package.

TMS320F28379S, TMS320F28377S
VREFHIA
DACOUTA
VREFHIA VDAC Comparator Subsystem 1
DACOUTA/ADCINA0 0 REFHI CMPIN1P
DACOUTB/ADCINA1 1 DACREFSEL
Digital CTRIP1H
CMPIN1P/ADCINA2 2 VDDA or VDAC Filter CTRIPOUT1H
CMPIN1N/ADCINA3 3
CMPIN2P/ADCINA4 4 12-bit DAC12
CMPIN2N/ADCINA5 5 Buffered
6
ADC-A DAC12
DAC Digital CTRIP1L
7 16-bits
CMPIN1N Filter CTRIPOUT1L
VREFLOA 8 or VSSA
VREFLOA 9 12-bits
10 (selectable) Comparator Subsystem 2
CMPIN2P
DACOUTB
11 VREFHIA VDAC
Digital CTRIP2H
12
VDDA or VDAC Filter CTRIPOUT2H
TEMP SENSOR 13 DACREFSEL
CMPIN4P/ADCIN14 14
DAC12
CMPIN4N/ADCIN15 15 REFLO
12-bit
DAC12 Digital CTRIP2L
Buffered
VREFLOA Filter
DAC CMPIN2N CTRIPOUT2L
VREFHIB
VSSA
Comparator Subsystem 3
VDAC/ADCINB0 0 REFHI CMPIN3P
DACOUTC/ADCINB1 1 Digital CTRIP3H
DACOUTC
CMPIN3P/ADCINB2 2 VREFHIB VDAC VDDA or VDAC Filter CTRIPOUT3H
CMPIN3N/ADCINB3 3
ADCINB4 4 DACREFSEL DAC12
ADCINB5 5
6
ADC-B DAC12 Digital CTRIP3L
7 16-bits 12-bit
8 or Buffered
VREFLOB
VREFLOB 9 12-bits DAC
11 VSSA CMPIN4P
12 Digital CTRIP4H
13 VDDA or VDAC Filter CTRIPOUT4H
14
DAC12
15 REFLO
DAC12 Digital
VREFLOB CTRIP4L
VREFHIC
0 REFHI CMPIN5P
1 Digital CTRIP5H
CMPIN6P/ADCINC2 2 VDDA or VDAC Filter CTRIPOUT5H
CMPIN6N/ADCINC3 3
CMPIN5P/ADCINC4 4 DAC12
CMPIN5N/ADCINC5 5
6
ADC-C DAC12 Digital CTRIP5L
7 16-bits
VREFLOC 8 or
VREFLOC 9 12-bits
11 CMPIN6P
Digital CTRIP6H
12
13
14
DAC12
15 REFLO
DAC12 Digital
VREFLOC CTRIP6L
VREFHID
CMPIN7P/ADCIND0 0 REFHI CMPIN7P
CMPIN7N/ADCIND1 1 Digital CTRIP7H
CMPIN8P/ADCIND2 2 VDDA or VDAC Filter CTRIPOUT7H
CMPIN8N/ADCIND3 3
ADCIND4 4 DAC12
ADCIND5 5 ADC-D
6 DAC12 Digital CTRIP7L
7 16-bits
or CMPIN7N Filter CTRIPOUT7L
VREFLOD 8
VREFLOD 9 12-bits
11 CMPIN8P
12 Digital CTRIP8H
14
15 DAC12
REFLO
VREFLOD
Figure 5-27. Analog Subsystem Block Diagram (337-Ball ZWT)

TMS320F28379S, TMS320F28377S
VREFHIA
DACOUTA
Digital CTRIP1H
CMPIN1N/ADCINA3 3
6
ADC-A DAC12
DAC Digital CTRIP1L
7 16-bits
VREFLOA 8 or VSSA
VREFLOA 9 12-bits
DACOUTB
11 VREFHIA VDAC CMPIN2P
Digital CTRIP2H
12
TEMP SENSOR 13 DACREFSEL
CMPIN4P/ADCIN14 14
DAC12
CMPIN4N/ADCIN15 15 REFLO 12-bit
Buffered DAC12 Digital CTRIP2L
VREFLOA DAC Filter
CMPIN2N CTRIPOUT2L
VREFHIB
VSSA
DACOUTC/ADCINB1 1 CTRIP3H
DACOUTC
VREFHIB VDAC Digital
CMPIN3P/ADCINB2 2 VDDA or VDAC Filter CTRIPOUT3H
CMPIN3N/ADCINB3 3
DACREFSEL
4 DAC12
5
6
ADC-B DAC12
12-bit Digital CTRIP3L
7 16-bits
Buffered CMPIN3N Filter CTRIPOUT3L
8 or
VREFLOB DAC
9 12-bits
VREFLOB
10 (selectable) VSSA Comparator Subsystem 4
11 CMPIN4P
12 Digital CTRIP4H
14
DAC12
15 REFLO
DAC12 Digital
VREFLOB CTRIP4L
VREFHIC
0 REFHI CMPIN5P
1 Digital CTRIP5H
CMPIN6P/ADCINC2 2 VDDA or VDAC Filter CTRIPOUT5H
CMPIN6N/ADCINC3 3
CMPIN5P/ADCINC4 4 DAC12
5
6
ADC-C DAC12 Digital CTRIP5L
7 16-bits
Filter CTRIPOUT5L
VREFLOC 8 or
VREFLOC 9 12-bits
11 CMPIN6P
Digital CTRIP6H
12
13
14
DAC12
15 REFLO
DAC12 Digital
VREFLOC CTRIP6L
VREFHID
CMPIN7P/ADCIND0 0 REFHI CMPIN7P
CMPIN7N/ADCIND1 1 Digital CTRIP7H
CMPIN8P/ADCIND2 2 VDDA or VDAC Filter CTRIPOUT7H
CMPIN8N/ADCIND3 3
ADCIND4 4 DAC12
5 ADC-D
6 DAC12 Digital CTRIP7L
7 16-bits
or CMPIN7N Filter CTRIPOUT7L
VREFLOD 8
VREFLOD 9 12-bits
11 CMPIN8P
12 Digital CTRIP8H
14
15 DAC12
REFLO
VREFLOD
Figure 5-28. Analog Subsystem Block Diagram (176-Pin PTP)

TMS320F28379S, TMS320F28377S
VREFHIA
DACOUTA
Digital CTRIP1H
CMPIN1N/ADCINA3 3
6
ADC-A DAC12
DAC Digital CTRIP1L
7 16-bits
VREFLOA 8 or VSSA
VREFLOA 9 12-bits
DACOUTB
VREFHIA VDAC CMPIN2P
11
12 Digital CTRIP2H
DACREFSEL VDDA or VDAC Filter CTRIPOUT2H
TEMP SENSOR 13
CMPIN4P/ADCIN14 14
DAC12
CMPIN4N/ADCIN15 15 REFLO 12-bit
Buffered DAC12 CTRIP2L
Digital
VREFLOA DAC
VREFHIB VSSA
DACOUTC
DACOUTC/ADCINB1 1 VREFHIB VDAC Digital CTRIP3H
CMPIN3P/ADCINB2 2 VDDA or VDAC Filter CTRIPOUT3H
CMPIN3N/ADCINB3 3 DACREFSEL
ADCINB4 4 DAC12
ADCINB5 5
6
ADC-B 12-bit DAC12 Digital CTRIP3L
7 16-bits Buffered
8 or DAC
VREFLOB
9 12-bits
VREFLOB
10 (selectable) VSSA Comparator Subsystem 4
11 CMPIN4P
12 Digital CTRIP4H
14
DAC12
15 REFLO
DAC12 Digital
VREFLOB CTRIP4L
Figure 5-29. Analog Subsystem Block Diagram (100-Pin PZP)

TMS320F28379S, TMS320F28377S
5.8.1 Analog-to-Digital Converter (ADC)

The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of
either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC
wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
Each ADC has the following features:
• Selectable resolution of 16 bits or 12 bits
• Ratiometric external reference set by VREFHI and VREFLO
• Differential signal conversions (16-bit mode only)
• Single-ended signal conversions (12-bit mode only)
• Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• Multiple trigger sources
– Software immediate start
– All ePWMs
– GPIO XINT2
– CPU timers
– ADCINT1 or 2
• Four flexible PIE interrupts
• Burst mode
• Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture

TMS320F28379S, TMS320F28377S
Figure 5-30 shows the ADC module block diagram.
Analog to Digital Core Analog to Digital Wrapper Logic

SIGNALMODE
SIGNALMODE
Input Circuit RESOLUTION RESOLUTION
TRIGSEL
SOCx (0-15)
Triggers
CHSEL [15:0]
SOC
[15:0]
ADCSOC Arbitration ACQPS
ADCIN0 0
ADCIN1 1 & Control [15:0]
CHSEL
ADCIN2 2
ADCIN3 3
SOCxSTART[15:0]
...
...
ADCIN4 4
ADCIN5
EOCx[15:0]
5
ADCIN6 6
xV1IN+
ADCCOUNTER TRIGGER[15:0]
ADCIN7 7
u
DOUT1
ADCIN8 8
xV
ADCIN9 9
2 IN-
ADCIN10 10
ADCIN11 11 SOC Delay Trigger
ADCIN12 12
S/H Circuit Converter Timestamp Timestamp
ADCIN13 13
ADCIN14 14
ADCIN15 15 RESULT + -
S ADCPPBxOFFCAL
ADCRESULT
0–15 Regs
saturate
ADCPPBxOFFREF
+ -
S ADCPPBxRESULT
VREFHI Event
ADCEVT
CONFIG ADCEVTINT
Logic
VREFLO
Reference Voltage Levels Post Processing Block (1-4)
Interrupt Block (1-4)

ADCINT1-4
Figure 5-30. ADC Module Block Diagram

TMS320F28379S, TMS320F28377S
5.8.1.1 ADC Electrical Data and Timing

Table 5-43 shows the ADC operating conditions for 16-bit differential mode. Table 5-44 shows the ADC
characteristics for 16-bit differential mode. Table 5-45 shows the ADC operating conditions for 12-bit
single-ended mode. Table 5-46 shows the ADC characteristics for 12-bit single-ended mode. Table 5-47
shows the ADCEXTSOC timing requirements.
Table 5-43. ADC Operating Conditions (16-Bit Differential Mode)

MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
320 ns
Sample window duration (set by ACQPS and PERx.SYSCLK)
1 ADCCLK
VREFHI 2.4 2.5 or 3.0 VDDA V
VREFLO VSSA 0 VSSA V
VREFHI – VREFLO 2.4 VDDA V
ADC input conversion range VREFLO VREFHI V
ADC input signal common mode voltage (1) VREFCM – 50 VREFCM VREFCM + 50 mV
(1) VREFCM = (VREFHI + VREFLO)/2
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC or DAC inputs using the same VREF.

TMS320F28379S, TMS320F28377S
Table 5-44. ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted) (1)
ADC conversion cycles (2) 29.6 31 ADCCLKs
Power-up time (after setting
500 µs
ADCPWDNZ to first conversion)
Gain error –64 ±9 64 LSBs
Offset error (3) –16 ±9 16 LSBs
Channel-to-channel gain error ±6 LSBs
Channel-to-channel offset error ±3 LSBs
ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±6 LSBs
ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±3 LSBs
DNL (4) > –1 ±0.5 1 LSBs
INL –3 ±1.5 3 LSBs
(5) (6)
SNR VREFHI = 2.5 V, fin = 10 kHz 87.6 dB
THD (5) (6) VREFHI = 2.5 V, fin = 10 kHz –93.5 dB
SFDR (5) (6) VREFHI = 2.5 V, fin = 10 kHz 95.4 dB
SINAD (5) (6) VREFHI = 2.5 V, fin = 10 kHz 86.6 dB
VREFHI = 2.5 V, fin = 10 kHz,
14.1
single ADC (7)
ENOB (5) (6) 14.1 bits
synchronous ADCs (8)
VREFHI = 2.5 V, fin = 10 kHz, Not
asynchronous ADCs (9) supported
VDDA = 3.3-V DC + 200 mV
PSRR 77 dB
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
PSRR 74 dB
Sine at 800 kHz
CMRR DC to 1 MHz 60 dB
VREFHI input current 190 µA
VREFHI = 2.5 V, synchronous ADCs (8) –2 2
ADC-to-ADC isolation (6) (10) (11) Not LSBs
VREFHI = 2.5 V, asynchronous ADCs (9)
supported
(1) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(2) See Section 5.8.1.1.2.
(3) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.
(4) No missing codes.
(5) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(6) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(7) One ADC operating while all other ADCs are idle.
(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(10) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(11) Value based on characterization.

TMS320F28379S, TMS320F28377S
Table 5-45. ADC Operating Conditions (12-Bit Single-Ended Mode)

MIN TYP MAX UNIT
ADCCLK (derived from PERx.SYSCLK) 5 50 MHz
75 ns
Sample window duration (set by ACQPS and PERx.SYSCLK)
1 ADCCLK
VREFHI 2.4 2.5 or 3.0 VDDA V
VREFLO VSSA 0 VSSA V
VREFHI – VREFLO 2.4 VDDA V
ADC input conversion range VREFLO VREFHI V
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC or DAC inputs using the same VREF.

TMS320F28379S, TMS320F28377S
Table 5-46. ADC Characteristics (12-Bit Single-Ended Mode)

ADC conversion cycles (2) 10.1 11 ADCCLKs
Power-up time 500 µs
Gain error –5 ±3 5 LSBs
Offset error –4 ±2 4 LSBs
Channel-to-channel gain error ±4 LSBs
Channel-to-channel offset error ±2 LSBs
ADC-to-ADC gain error Identical VREFHI and VREFLO for all ADCs ±4 LSBs
ADC-to-ADC offset error Identical VREFHI and VREFLO for all ADCs ±2 LSBs
(3)
DNL > –1 ±0.5 1 LSBs
INL –2 ±1.0 2 LSBs
SNR (4) (5) VREFHI = 2.5 V, fin = 100 kHz 68.8 dB
(4) (5)
THD VREFHI = 2.5 V, fin = 100 kHz –78.4 dB
SFDR (4) (5) VREFHI = 2.5 V, fin = 100 kHz 79.2 dB
SINAD (4) (5) VREFHI = 2.5 V, fin = 100 kHz 68.4 dB
11.1
single ADC (6), all packages
11.1
synchronous ADCs (7), all packages
Not
asynchronous ADCs (8),
(4) (5) supported
ENOB 100-pin PZP package bits
asynchronous ADCs (8), 9.7
176-pin PTP package
asynchronous ADCs (8), 10.9
337-ball ZWT package
VDDA = 3.3-V DC + 200 mV
PSRR 60 dB
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
PSRR 57 dB
Sine at 800 kHz
(7)
VREFHI = 2.5 V, synchronous ADCs ,
–1 1
all packages
VREFHI = 2.5 V, asynchronous ADCs (8), Not
(5) (9) (10)
100-pin PZP package supported
ADC-to-ADC isolation LSBs
VREFHI = 2.5 V, asynchronous ADCs (8),
–9 9
176-pin PTP package
VREFHI = 2.5 V, asynchronous ADCs (8),
–2 2
337-ball ZWT package
VREFHI input current 130 µA
(1) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(2) See Section 5.8.1.1.2.
(3) No missing codes.
(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(5) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(6) One ADC operating while all other ADCs are idle.
(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(9) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(10) Value based on characterization.

TMS320F28379S, TMS320F28377S
Table 5-47. ADCEXTSOC Timing Requirements (1)

MIN MAX UNIT
tw(INT) Pulse duration, INT input low/high
With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles
5.8.1.1.1 ADC Input Models
NOTE
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.
For single-ended operation, the ADC input characteristics are given by Table 5-48 and Figure 5-31.
Table 5-48. Single-Ended Input Model Parameters

DESCRIPTION VALUE (12-BIT MODE)
Cp Parasitic input capacitance See Table 5-50
Ron Sampling switch resistance 425 Ω
Ch Sampling capacitor 14.5 pF
Rs Nominal source impedance 50 Ω
ADC
ADCINx
Rs
Switch Ron
AC Cp Ch
VREFLO
Figure 5-31. Single-Ended Input Model
For differential operation, the ADC input characteristics are given by Table 5-49 and Figure 5-32.
Table 5-49. Differential Input Model Parameters

DESCRIPTION VALUE (16-BIT MODE)
Cp Parasitic input capacitance See Table 5-50
Ron Sampling switch resistance 700 Ω
Ch Sampling capacitor 16.5 pF
Rs Nominal source impedance 50 Ω
ADC
Rs ADCINxP
Cp Switch Ron
AC VSSA Ch
Cp
ADCINxN Switch Ron

Rs
Figure 5-32. Differential Input Model

TMS320F28379S, TMS320F28377S
Table 5-50 shows the parasitic capacitance on each channel. Also, enabling a comparator adds
approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative
comparator inputs.
Table 5-50. Per-Channel Parasitic Capacitance

Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED COMPARATOR ENABLED
ADCINA0 12.9 N/A
ADCINA1 10.3 N/A
ADCINA2 5.9 7.3
ADCINA3 6.3 8.8
ADCINA4 5.9 7.3
ADCINA5 6.3 8.8
ADCINB0 117.0 N/A
ADCINB1 10.6 N/A
ADCINB2 5.9 7.3
ADCINB3 6.2 8.7
ADCINB4 5.2 N/A
ADCINB5 5.1 N/A
ADCINC2 5.5 6.9
ADCINC3 5.8 8.3
ADCINC4 5.0 6.4
ADCINC5 5.3 7.8
ADCIND0 5.3 6.7
ADCIND1 5.7 8.2
ADCIND2 5.3 6.7
ADCIND3 5.6 8.1
ADCIND4 4.3 N/A
ADCIND5 4.3 N/A
ADCIN14 8.6 10.0
ADCIN15 9.0 11.5
These input models should be used along with actual signal source impedance to determine the
acquisition window duration. See the Choosing an Acquisition Window Duration section of the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will
require assuming that Ch could start the S+H window completely charged to VREFHI or completely
discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered
channel, or vice-versa, the actual initial voltage on Ch will be close to being completely discharged to
VREFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on Ch will be close to the
voltage of the previously converted channel.

TMS320F28379S, TMS320F28377S
5.8.1.1.2 ADC Timing Diagrams

Table 5-51 shows the ADC timings in 12-bit mode (SYSCLK cycles). Table 5-52 shows the ADC timings in
16-bit mode. Figure 5-33 and Figure 5-34 show the ADC conversion timings for two SOCs given the
following assumptions:
• SOC0 and SOC1 are configured to use the same trigger.
• No other SOCs are converting or pending when the trigger occurs.
• The round robin pointer is in a state that causes SOC0 to convert first.
• ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE
module).
The following parameters are identified in the timing diagrams:
• The parameter tSH is the duration of the S+H window. At the end of this window, the value on the S+H
capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS +
1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be
the same for different SOCs.
• The parameter tLAT is the time from the end of the S+H window until the ADC conversion results latch
in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous
conversion results will be returned.
• The parameter tEOC is the time from the end of the S+H window until the next ADC conversion S+H
window can begin. In 16-bit mode, this will coincide with the latching of the conversion results, while in
12-bit mode, the subsequent sample can start before the conversion results are latched.
• The parameter tINT is the time from the end of the S+H window until an ADCINT flag is set (if
configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, this will coincide with the
conversion results being latched into the result register. If the bit is cleared, this will coincide with the
end of the S+H window.

TMS320F28379S, TMS320F28377S
Table 5-51. ADC Timings in 12-Bit Mode (SYSCLK Cycles)

ADCCLK
ADCCLK PRESCALE SYSCLK CYCLES
CYCLES
ADCCTL2 RATIO
tEOC tLAT tINT(EARLY) tINT(LATE) tEOC
[PRESCALE] ADCCLK:SYSCLK
0 1 11 13 1 11 11.0
1 1.5 Invalid
2 2 21 23 1 21 10.5
3 2.5 26 28 1 26 10.4
4 3 31 34 1 31 10.3
5 3.5 36 39 1 36 10.3
6 4 41 44 1 41 10.3
7 4.5 46 49 1 46 10.2
8 5 51 55 1 51 10.2
9 5.5 56 60 1 56 10.2
10 6 61 65 1 61 10.2
11 6.5 66 70 1 66 10.2
12 7 71 76 1 71 10.1
13 7.5 76 81 1 76 10.1
14 8 81 86 1 81 10.1
15 8.5 86 91 1 86 10.1
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H SOC0 SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0 (old data) Sample n
ADCRESULT1 (old data) Sample n+1
ADCINTFLG.ADCINTx
tSH tLAT
tEOC
tINT
Figure 5-33. ADC Timings for 12-Bit Mode

TMS320F28379S, TMS320F28377S
Table 5-52. ADC Timings in 16-Bit Mode

ADCCLK
ADCCLK PRESCALE SYSCLK CYCLES
CYCLES
ADCCTL2 RATIO
tEOC tLAT tINT(EARLY) tINT(LATE) tEOC
[PRESCALE] ADCCLK:SYSCLK
0 1 31 32 1 31 31.0
1 1.5 Invalid
2 2 60 61 1 60 30.0
3 2.5 75 75 1 75 30.0
4 3 90 91 1 90 30.0
5 3.5 104 106 1 104 29.7
6 4 119 120 1 119 29.8
7 4.5 134 134 1 134 29.8
8 5 149 150 1 149 29.8
9 5.5 163 165 1 163 29.6
10 6 178 179 1 178 29.7
11 6.5 193 193 1 193 29.7
12 7 208 209 1 208 29.7
13 7.5 222 224 1 222 29.6
14 8 237 238 1 237 29.6
15 8.5 252 252 1 252 29.6
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H SOC0 SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0 (old data) Sample n
ADCRESULT1 (old data) Sample n+1
ADCINTFLG.ADCINTx
tSH tLAT
tEOC
tINT
Figure 5-34. ADC Timings for 16-Bit Mode

TMS320F28379S, TMS320F28377S
5.8.1.2 Temperature Sensor Electrical Data and Timing

The temperature sensor can be used to measure the device junction temperature. The temperature
sensor is sampled through an internal connection to the ADC and translated into a temperature through
TI-provided software. When sampling the temperature sensor, the ADC must meet the acquisition time in
Table 5-53.
Table 5-53. Temperature Sensor Electrical Characteristics

Temperature accuracy ±15 °C
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor) 500 µs
ADC acquisition time 700 ns

TMS320F28379S, TMS320F28377S
5.8.2 Comparator Subsystem (CMPSS)

Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs),
two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of
these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the
positive input of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the
negative comparator inputs. There are two comparators, and therefore two outputs from the CMPSS
module, which are connected to the input of a digital filter module before being passed on to the
Comparator TRIP crossbar and either PWM modules or directly to a GPIO pin. Figure 5-35 shows the
CMPSS connectivity on the 337-ball ZWT and 176-pin PTP packages. Figure 5-36 shows CMPSS
connectivity on the 100-pin PZP package.
CMPIN1P Pin CTRIP1H
Digital
DAC12
CTRIP1H
CTRIP1L
DAC12 CTRIP1L CTRIP2H
Digital
CTRIPOUT1L CTRIP2L ePWMs
CMPIN1N Pin Filter ePWM X-BAR
Comparator Subsystem 2 CTRIP8H

CMPIN2P Pin CTRIP2H CTRIP8L
Digital
DAC12
DAC12 CTRIP2L
Digital
Filter CTRIPOUT2L
CMPIN2N Pin
CTRIPOUT1H
CTRIPOUT1L
Comparator Subsystem 8 CTRIPOUT2H
CMPIN8P Pin CTRIP8H CTRIPOUT2L
Digital Output X-BAR GPIO Mux
CTRIPOUT8H
DAC12 CTRIPOUT8L
DAC12 CTRIP8L
Digital
Filter CTRIPOUT8L
CMPIN8N Pin
Figure 5-35. CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)

TMS320F28379S, TMS320F28377S
CMPIN1P Pin CTRIP1H
Digital
CTRIP1H
DAC12
CTRIP1L
DAC12 CTRIP1L CTRIP2H
Digital CTRIP2L
Filter CTRIPOUT1L ePWM X-BAR ePWMs
CMPIN1N Pin CTRIP3H
CTRIP3L
CTRIP4H
CMPIN2P Pin CTRIP4L
CTRIP2H
Digital
DAC12
DAC12 CTRIP2L
Digital
Filter CTRIPOUT2L
CMPIN2N Pin
CMPIN3P Pin CTRIP3H
Digital
VDDA or VDAC Filter CTRIPOUT3H CTRIPOUT1H
CTRIPOUT1L
DAC12 CTRIPOUT2H
CTRIPOUT2L Output X-BAR
CTRIP3L GPIO Mux
DAC12 Digital CTRIPOUT3H
Filter CTRIPOUT3L CTRIPOUT3L
CMPIN3N Pin
CTRIPOUT4H
CTRIPOUT4L
CMPIN4P Pin CTRIP4H
Digital
DAC12
DAC12 CTRIP4L
Digital
Filter CTRIPOUT4L
CMPIN4N Pin
Figure 5-36. CMPSS Connectivity (100-Pin PZP)

TMS320F28379S, TMS320F28377S
5.8.2.1 CMPSS Electrical Data and Timing

Table 5-54 shows the comparator electrical characteristics. Figure 5-37 shows the CMPSS comparator
input referred offset. Figure 5-38 shows the CMPSS comparator hysteresis.
Table 5-54. Comparator Electrical Characteristics

Power-up time (from COMPCTL[COMPDACE] to
10 µs
comparator ready)
Comparator input (CMPINxx) range 0 VDDA V
Input referred offset error –20 20 mV
1x 12
2x 24 CMPSS
Hysteresis (1)
3x 36 DAC LSB
4x 48
Step response 21 60
Response time (delay from CMPINx input change
Ramp response (1.65 V/µs) 26 ns
to output on ePWM X-BAR or Output X-BAR)
Ramp response (8.25 mV/µs) 30
(1) Hysteresis will scale with the CMPSS reference voltage.
NOTE
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If
a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal
comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V.
During this time, the internal comparator input will be floating and can decay below VDDA
within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect
result depending on the value of the other comparator input.
Input Referred Offset
CTRIPx
Logic Level CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0 CMPINxN or
DACxVAL
Figure 5-37. CMPSS Comparator Input Referred Offset
Hysteresis
CTRIPx
Logic Level CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0 CMPINxN or
DACxVAL
Figure 5-38. CMPSS Comparator Hysteresis

TMS320F28379S, TMS320F28377S
Table 5-55 shows the CMPSS DAC static electrical characteristics. Figure 5-39 shows the CMPSS DAC
static offset. Figure 5-40 shows the CMPSS DAC static gain. Figure 5-41 shows the CMPSS DAC static
linearity.
Table 5-55. CMPSS DAC Static Electrical Characteristics

Internal reference 0 VDDA
CMPSS DAC output range V
External reference 0 VDAC
Static offset error (1) –25 25 mV
Static gain error (1) –2 2 % of FSR
Static DNL Endpoint corrected >–1 4 LSB
Static INL Endpoint corrected –16 16 LSB
Settling to 1 LSB after full-scale output
Settling time 1 µs
change
Resolution 12 bits
Error induced by comparator trip or
CMPSS DAC output disturbance (2) CMPSS DAC code change within the –100 100 LSB
same CMPSS module
CMPSS DAC disturbance time (2) 200 ns
VDAC reference voltage When VDAC is reference 2.4 2.5 or 3.0 VDDA V
VDAC load (3) When VDAC is reference 6 kΩ
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
Offset Error
Figure 5-39. CMPSS DAC Static Offset

TMS320F28379S, TMS320F28377S
Ideal Gain
Actual Gain
Actual Linear Range
Figure 5-40. CMPSS DAC Static Gain
Linearity Error
Figure 5-41. CMPSS DAC Static Linearity

TMS320F28379S, TMS320F28377S
5.8.3 Buffered Digital-to-Analog Converter (DAC)

The buffered DAC module consists of an internal reference DAC and an analog output buffer that is
capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a
known pin voltage when the output buffer is disabled. This pulldown resistor cannot be disabled and
remains as a passive component on the pin, even for other shared pin mux functions. Software writes to
the DAC value register can take effect immediately or can be synchronized with PWMSYNC events.
Each buffered DAC has the following features:
• 12-bit programmable internal DAC
• Selectable reference voltage
• Pulldown resistor on output
• Ability to synchronize with PWMSYNC
The block diagram for the buffered DAC is shown in Figure 5-42.
DACCTL[DACREFSEL]
VDAC 0
VREFHI 1
VDDA
SYSCLK > DACCTL[LOADMODE]
DACVALS D Q 0
12-bit
DACVALA DAC
Buffer
D Q 1
RPD
PWMSYNC1 0
PWMSYNC2 1 > VSSA
PWMSYNC3 2 VSSA
... …
PWMSYNCn n-1
DACCTL[SYNCSEL]
Figure 5-42. DAC Module Block Diagram

TMS320F28379S, TMS320F28377S
5.8.3.1 Buffered DAC Electrical Data and Timing

Table 5-56 shows the buffered DAC electrical characteristics. Figure 5-43 shows the buffered DAC offset.
Figure 5-44 shows the buffered DAC gain. Figure 5-45 shows the buffered DAC linearity.
Table 5-56. Buffered DAC Electrical Characteristics

Power-up time (DACOUTEN to DAC
10 µs
output valid)
Trimmed offset error Midpoint –10 10 mV
Gain error (2) –2.5 2.5 % of FSR
DNL (3) Endpoint corrected > –1 1 LSB
INL Endpoint corrected –5 5 LSB
Settling to 2 LSBs after 0.3V-to-3V
DACOUTx settling time 2 µs
transition
Resolution 12 bits
Voltage output range (4) 0.3 VDDA – 0.3 V
Capacitive load Output drive capability 100 pF
Resistive load Output drive capability 5 kΩ
RPD 50 kΩ
Reference voltage (5) VDAC or VREFHI 2.4 2.5 or 3.0 VDDA V
Reference load (6) VDAC or VREFHI 170 kΩ
Integrated noise from 100 Hz to 100 kHz 500 µVrms
Output noise
Noise density at 10 kHz 711 nVrms/√Hz
Glitch energy 1.5 V-ns
DC up to 1 kHz 70
PSRR (7) dB
100 kHz 30
SNR 1020 Hz 67 dB
THD 1020 Hz –63 dB
1020 Hz, including harmonics and spurs 66
SFDR dBc
1020 Hz, including only spurs 104
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V unless otherwise noted. Minimum and Maximum values are tested
or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
(6) Per active Buffered DAC module.
(7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
NOTE
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC
may float to 0 V internally, giving improper DAC output.

TMS320F28379S, TMS320F28377S
Offset Error
Code 2048
Figure 5-43. Buffered DAC Offset
Actual Gain
Ideal Gain
Code 373 Code 3722
Linear Range
(3.3-V Reference)
Figure 5-44. Buffered DAC Gain

TMS320F28379S, TMS320F28377S
Linearity Error
Code 373 Code 3722
Linear Range
(3.3-V Reference)
Figure 5-45. Buffered DAC Linearity

TMS320F28379S, TMS320F28377S
5.9 Control Peripherals
NOTE
For the actual number of each peripheral on a specific device, see Table 3-1.
5.9.1 Enhanced Capture (eCAP)

The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
• Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall
sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
• 4-event time-stamp registers (each 32 bits)
• Edge-polarity selection for up to four sequenced time-stamp capture events
• Interrupt on either of the four events
• Single shot capture of up to four event timestamps
• Continuous mode capture of timestamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All of the above resources dedicated to a single input pin
• When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to
GPIO pins through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 4.5.2 and
Section 4.5.3.
Figure 5-46 shows the block diagram of an eCAP module.

TMS320F28379S, TMS320F28377S
CTRPHS
(phase register−32 bit) APWM mode
SYNC
SYNCIn
OVF CTR_OVF
TSCTR CTR [0−31]
SYNCOut PWM
(counter−32 bit) Delta−mode PRD [0−31] compare
RST
logic
CMP [0−31]
32
CTR [0−31] CTR=PRD

CTR=CMP
32
PRD [0−31]
eCAPx
MODE SELECT
32 CAP1 LD1 Polarity
LD
(APRD active) select
APRD 32
shadow CMP [0−31]
32
32 CAP2 LD2 Polarity

LD
(ACMP active) select
Event Event
32 ACMP
qualifier
shadow Prescale
32 Polarity
CAP3 LD3 select
LD
(APRD shadow)
32 CAP4 LD4
LD Polarity
(ACMP shadow) select
4
Capture events 4
CEVT[1:4]
Interrupt Continuous /
to PIE Trigger Oneshot
and CTR_OVF Capture Control
Flag
CTR=PRD
control
CTR=CMP
Figure 5-46. eCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.

The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually
(for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock
is off.

TMS320F28379S, TMS320F28377S
5.9.1.1 eCAP Electrical Data and Timing

Table 5-57 shows the eCAP timing requirement and Table 5-58 shows the eCAP switching characteristics.
Table 5-57. eCAP Timing Requirement (1)

MIN MAX UNIT
Asynchronous 2tc(SYSCLK) cycles
tw(CAP) Capture input pulse width Synchronous 2tc(SYSCLK) cycles
With input qualifier 1tc(SYSCLK) + tw(IQSW) cycles
Table 5-58. eCAP Switching Characteristics

tw(APWM) Pulse duration, APWMx output high/low 20 ns

TMS320F28379S, TMS320F28377S
5.9.2 Enhanced Pulse Width Modulator (ePWM)

The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme,
advanced trip-zone functionality, and global register reload capabilities.
Figure 5-47 shows the signal interconnections with the ePWM. Figure 5-48 shows the ePWM trip input
connectivity.

TMS320F28379S, TMS320F28377S
TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable 00
CTR=CPMC 01
TBPRD Shadow (24) CTR=CPMD 10
TBPRDHR (8) Rsvd 11 CTR=ZERO Sync EPWMxSYNCO
TBPRD Active (24) Out
TBCTL[SWFSYNC] CTR=CMPB
8 Select
CTR=PRD EPWMxSYNCI
TBCTL[PHSEN] TBCTL[SYNCOSEL]
Counter DCAEVT1.sync
(A)
Up/Down (A)
DCBEVT1.sync
(16 Bit)
CTR=ZERO
TBCTR
Active (16) CTR_Dir
CTR=PRD
EPWMxINT
TBPHSHR (8) CTR=ZERO
16 8 CTR=PRD or ZERO
Phase EPWMxSOCA On-chip
TBPHS Active (24) CTR=CMPA Event
Control ADC
CTR=CMPB Trigger EPWMxSOCB
CTR=CMPC and
Interrupt
CTR=CMPD (ET) ADCSOCOUTSEL
Counter Compare (CC)
Action CTR_Dir
Qualifier (A) Select and pulse stretch
CTR=CMPA (AQ) DCAEVT1.soc
(A) for external ADC
DCBEVT1.soc
CMPAHR (8)
EPWMSOCAO
16 EPWMSOCBO
HiRes PWM (HRPWM)
CMPA Active (24) CMPAHR (8)
CMPA Shadow (24) EPWMA ePWMxA
Dead PWM Trip

CTR=CMPB Chopper Zone
Band
CMPBHR (8) (DB) (PC) (TZ)
16
EPWMB ePWMxB
CMPB Active (24)
CMPB Shadow (24)

CMPBHR (8)
EPWMxTZINT
TBCNT(16) TZ1 to TZ3
CTR=CMPC
CTR=ZERO EMUSTOP
CMPC[15-0] 16 DCAEVT1.inter CLOCKFAIL
DCBEVT1.inter
EQEPxERR
CMPC Active (16) DCAEVT2.inter (A)
DCBEVT2.inter DCAEVT1.force
(A)
CMPC Shadow (16) DCAEVT2.force
(A)
DCBEVT1.force
(A)
TBCNT(16) DCBEVT2.force
CTR=CMPD
CMPD[15-0] 16
CMPD Active (16)
CMPD Shadow (16)

A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 5-47. ePWM Submodules and Critical Internal Signal Interconnects

TMS320F28379S, TMS320F28377S
GPIO0 Async/
INPUT14 XINT5 PIE(s),
Sync/ Input X-Bar CLA(s)
INPUT13 XINT4
Sync+Filter
GPIOx
INPUT10
INPUT12
INPUT11
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
eCAP6
eCAP5
XINT1 eCAP4
PIE(s),
XINT2 eCAP3
CLA(s)
XINT3 eCAP2
eCAP1
ADC EXTSYNCIN1 ePWM and eCAP
Wrapper(s) Sync Chain
EXTSYNCIN2
TZ1
TZ2 EPWMINT PIE(s),
TZ3 TZINT CLA(s)
TRIP1
EPWMx.EPWMCLK
TRIP2 EPWMENCLK
TRIP3 TBCLKSYNC
TRIP6
TRIP4
ADCSOCAO Select Ckt
TRIP5
TRIP7
ePWM TRIP8 ADCSOCBO Select Ckt
X-Bar TRIP9 All
TRIP10 ePWM SOCA ADC
TRIP11 Modules Wrapper(s)
TRIP12 SOCB
Reserved TRIP13
ECCERR TRIP14
CPU1.PIEVECTERROR TRIP15 SD1
EQEPERR TZ4 Filter-Reset FLT1
PWM11.CMPC FLT1
CLKFAIL TZ5 Filter-Reset FLT1
CPU1.EMUSTOP TZ6 PWM11.CMPD FLT1
EPWMn.EMUSTOP
Filter-Reset FLT1
PWM12.CMPC FLT1
PWM12.CMPD Filter-Reset FLT1
FLT1
SD2
Figure 5-48. ePWM Trip Input Connectivity

TMS320F28379S, TMS320F28377S
5.9.2.1 Control Peripherals Synchronization

The ePWM and eCAP synchronization chain allows synchronization between multiple modules for the
system. Figure 5-49 shows the synchronization chain architecture.
EXTSYNCIN1 EXTSYNCIN2
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM3 EPWM4
EPWM4SYNCOUT EXTSYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
EPWM5 Cycles)
SYNCSEL.EPWM4SYNCIN
EPWM6
EPWM7
EPWM7SYNCOUT
EPWM8
SYNCSEL.EPWM7SYNCIN
EPWM9
EPWM10 EPWM10SYNCOUT
EPWM11
SYNCSEL.EPWM10SYNCIN
EPWM12 ECAP1
ECAP1SYNCOUT
SYNCSEL.SYNCOUT
ECAP2
SYNCSEL.ECAP1SYNCIN
ECAP3 ECAP4
SYNCSEL.ECAP4SYNCIN
ECAP5
ECAP6
Figure 5-49. Synchronization Chain Architecture

TMS320F28379S, TMS320F28377S
5.9.2.2 ePWM Electrical Data and Timing

Table 5-59 shows the PWM timing requirements and Table 5-60 shows the PWM switching
characteristics.
Table 5-59. ePWM Timing Requirements (1)

MIN MAX UNIT
Asynchronous 2tc(EPWMCLK) cycles
tw(SYNCIN) Sync input pulse width Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles
Table 5-60. ePWM Switching Characteristics

tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SYSCLK) cycles
Delay time, trip input active to PWM forced high
td(TZ-PWM) Delay time, trip input active to PWM forced low 25 ns
Delay time, trip input active to PWM Hi-Z
5.9.2.2.1 Trip-Zone Input Timing

Table 5-61 shows the trip-zone input timing requirements. Figure 5-50 shows the PWM Hi-Z
characteristics.
Table 5-61. Trip-Zone Input Timing Requirements (1)

MIN MAX UNIT
Asynchronous 1tc(EPWMCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(EPWMCLK) cycles
With input qualifier 1tc(EPWMCLK) + tw(IQSW) cycles
EPWMCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)
(B)
PWM
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-50. PWM Hi-Z Characteristics

TMS320F28379S, TMS320F28377S
5.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing

Table 5-62 shows the external ADC start-of-conversion switching characteristics. Figure 5-51 shows the
ADCSOCAO or ADCSOCBO timing.
Table 5-62. External ADC Start-of-Conversion Switching Characteristics

tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(SYSCLK) cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 5-51. ADCSOCAO or ADCSOCBO Timing

TMS320F28379S, TMS320F28377S
5.9.3 Enhanced Quadrature Encoder Pulse (eQEP)

The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position,
direction, and speed information from rotating machines used in high-performance motion and position-
control systems.
Each eQEP peripheral comprises five major functional blocks:
• Quadrature Capture Unit (QCAP)
• Position Counter/Control Unit (PCCU)
• Quadrature Decoder Unit (QDU)
• Unit Time Base for speed and frequency measurement (UTIME)
• Watchdog timer for detecting stalls (QWDOG)
The eQEP peripherals are clocked by PERx.SYSCLK. Figure 5-52 shows the eQEP block diagram.

TMS320F28379S, TMS320F28377S
System Control
Registers
To CPU
EQEPxENCLK
SYSCLK
Data Bus
QCPRD
QCAPCTL QCTMR
16 16
16
Quadrature
Capture
QCTMRLAT Unit
(QCAP)
QCPRDLAT
Registers QUTMR QWDTMR

Used by QUPRD QWDPRD
Multiple Units
32 16
QEPCTL
QEPSTS UTOUT
UTIME QWDOG QDECCTL
QFLG
16
WDTOUT
EQEPxAIN
EQEPxINT QCLK EQEPxA/XCLK
PIE EQEPxBIN
QDIR
EQEPxIIN
16 Position Counter/ QI EQEPxB/XDIR
EQEPxIOUT
Control Unit QS Quadrature GPIO
(PCCU) Decoder EQEPxIOE
QPOSLAT PHE (QDU) MUX EQEPxI
EQEPxSIN
QPOSSLAT PCSOUT
EQEPxSOUT
QPOSILAT EQEPxS
EQEPxSOE
32 32 16
QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL
eQEP Peripheral
Figure 5-52. eQEP Block Diagram

TMS320F28379S, TMS320F28377S
5.9.3.1 eQEP Electrical Data and Timing

Table 5-63 lists the eQEP timing requirement and Table 5-64 lists the eQEP switching characteristics.
Table 5-63. eQEP Timing Requirements (1)

MIN MAX UNIT
tw(QEPP) QEP input period
With input qualifier 2[1tc(SYSCLK) + tw(IQSW)] cycles
tw(INDEXH) QEP Index Input High time
tw(INDEXL) QEP Index Input Low time
tw(STROBH) QEP Strobe High time
tw(STROBL) QEP Strobe Input Low time
Table 5-64. eQEP Switching Characteristics

td(CNTR)xin Delay time, external clock to counter increment 4tc(SYSCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SYSCLK) cycles

TMS320F28379S, TMS320F28377S
5.9.4 High-Resolution Pulse Width Modulator (HRPWM)

The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module, there are two HR outputs:
• HR Duty and Deadband control on Channel A
• HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
NOTE
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
5.9.4.1 HRPWM Electrical Data and Timing

Table 5-65 lists the high-resolution PWM switching characteristics.
Table 5-65. High-Resolution PWM Characteristics

Micro Edge Positioning (MEP) step size (1) 150 310 ps
(1) Maximum MEP step size is based on worst-case process, maximum temperature and minimum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.

TMS320F28379S, TMS320F28377S
5.9.5 Sigma-Delta Filter Module (SDFM)

The SDFM is a four-channel digital filter designed specifically for current measurement and resolver
position decoding in motor control applications. Each channel can receive an independent sigma-delta
(ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital
decimation filters. The filter set includes a fast comparator for immediate digital threshold comparisons for
overcurrent and undercurrent monitoring. Figure 5-53 shows a block diagram of the SDFMs.
SDFM features include:
• Eight external pins per SDFM module:
– Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
• Four different configurable modulator clock modes:
– Modulator clock rate equals modulator data rate
– Modulator clock rate running at half the modulator data rate
– Modulator data is Manchester encoded. Modulator clock not required.
– Modulator clock rate is double that of modulator data rate
• Four independent configurable comparator units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value and under-value conditions
– Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
• Four independent configurable data filter units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
– Ability to enable or disable individual filter module
– Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable
(MFE) bit or the PWM signals.
• Filter data can be 16-bit or 32-bit representation
• PWMs can be used to generate modulator clock for sigma-delta modulators

TMS320F28379S, TMS320F28377S
SDFM- Sigma Delta Filter Module
G4 Filter Channel 1
Streams
IEL SD1INT
R
Comparator filter IEH Interrupt
SD1_D1 SD2INT
Unit
Input PIE
SD1_C1 Ctrl Data filter R
FILRES
PWM11.CMPC
SD1_D2 Filter Channel 2

SD1_C2
FILRES
Register Data bus

SD1_D3 Filter Channel 3 Map
SD1_C3
FILRES
PWM11.CMPD

SD1_C4 SD1FLT1.IEH
FILRES
SD1FLT1.IEL
SD1FLT2.IEH
SD1FLT2.IEL
SD1FLT3.IEH
GPIO SD1FLT3.IEL
MUX SD1FLT4.IEH
SDFM- Sigma Delta Filter Module SD1FLT4.IEL
Output
G4 Filter Channel 1 XBar
Streams
IEL SD2FLT1.IEH
R
Comparator filter IEH Interrupt SD2FLT1.IEL
SD2_D1 Unit
Input SD2FLT2.IEH
SD2_C1 Ctrl Data filter R
Data filter SD2FLT2.IEL
FILRES
SD2FLT3.IEH
PWM12.CMPC SD2FLT3.IEL
SD2_D2 Filter Channel 2 SD2FLT4.IEH
SD2_C2 SD2FLT4.IEL
FILRES
Register Data bus

SD2_D3 Filter Channel 3 Map
SD2_C3
PWM12.CMPD FILRES

SD2_C4
FILRES
Figure 5-53. SDFM Block Diagram

TMS320F28379S, TMS320F28377S
5.9.5.1 SDFM Electrical Data and Timing

Table 5-66 shows the SDFM timing requirements. Figure 5-54 through Figure 5-57 show the SDFM timing
diagrams.
Table 5-66. SDFM Timing Requirements

MIN MAX UNIT
Mode 0
tc(SDC)M0 Cycle time, SDx_Cy 40 256 * SYSCLK period ns
tw(SDCH)M0 Pulse duration, SDx_Cy high 10 tc(SDC)M0 – 10 ns
Setup time, SDx_Dy valid before SDx_Cy goes
tsu(SDDV-SDCH)M0 5 ns
high
th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 1
tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes low 5 ns
high
th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns
Mode 2
tc(SDD)M2 Cycle time, SDx_Dy 8 * tc(SYSCLK) 20 * tc(SYSCLK) ns
tw(SDDH)M2 Pulse duration, SDx_Dy high 10 ns
Mode 3
high
Mode 0 tw(SDCH)M0 tc(SDC)M0
SDx_Cy
tsu(SDDV-SDCH)M0 th(SDCH-SDD)M0
SDx_Dy
Figure 5-54. SDFM Timing Diagram – Mode 0
Mode 1
tw(SDCH)M1 tc(SDC)M1
SDx_Cy
tsu(SDDV-SDCL)M1 tsu(SDDV-SDCH)M1
SDx_Dy
th(SDCL-SDD)M1 th(SDCH-SDD)M1

TMS320F28379S, TMS320F28377S
Mode 2
(Manchester-encoded bit stream)
tc(SDD)M2
Modulator
internal clock
tw(SDDH)M2
Modulator
1 1 0 1 1 0 0 1 1
internal data
SDx-Dy
Mode 3 (CLKx is driven externally)

tc(SDC)M3
tw(SDCH)M3
SDx_Cy
tsu(SDDV-SDCH)M3 th(SDCH-SDD)M3
SDx_Dy

TMS320F28379S, TMS320F28377S
5.10 Communications Peripherals
NOTE
For the actual number of each peripheral on a specific device, see Table 3-1.
5.10.1 Controller Area Network (CAN)
NOTE
The CAN module uses the IP known as D_CAN. This document uses the names CAN and
D_CAN interchangeably to reference this peripheral.
The CAN module implements the following features:

• Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
• Bit rates up to 1 Mbps
• Multiple clock sources
• 32 message objects, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Programmable receive and identifier masks for each object
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
• Individual identifier mask for each message object
• Programmable FIFO mode for receive message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Two interrupt lines
• Global power down and wakeup support
NOTE
For a CANx Bit-CLK of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
NOTE
The accuracy of the on-chip zero-pin oscillator is in Table 5-18, Internal Oscillator Electrical
Characteristics. Depending on parameters such as the CAN bit timing settings, bit rate, bus
length, and propagation delay, the accuracy of this oscillator may not meet the requirements
of the CAN protocol. In this situation, an external clock source must be used.

TMS320F28379S, TMS320F28377S
5.10.2 Inter-Integrated Circuit (I2C)

The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 16-byte receive FIFO and one 16-byte transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode

TMS320F28379S, TMS320F28377S
Figure 5-58 shows how the I2C peripheral module interfaces within the device.
2
I C Module
I2CXSR I2CDXR
TX FIFO
SDA FIFO Interrupt to
CPU/PIE
RX FIFO
Peripheral Bus
I2CRSR I2CDRR
Control/Status
Registers CPU
Clock
SCL Synchronizer
Prescaler
Noise Filters
Interrupt to
I2C INT
CPU/PIE
Arbitrator
Figure 5-58. I2C Peripheral Module Interfaces

TMS320F28379S, TMS320F28377S
5.10.2.1 I2C Electrical Data and Timing

Table 5-67 shows the I2C timing requirements. Table 5-68 shows the I2C switching characteristics.
Table 5-67. I2C Timing Requirements

MIN MAX UNIT
Hold time, START condition, SCL fall delay
th(SDA-SCL)START 0.6 µs
after SDA fall
Setup time, Repeated START, SCL rise before
tsu(SCL-SDA)START 0.6 µs
SDA fall delay
th(SCL-DAT) Hold time, data after SCL fall 0 µs
tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
tr(SDA) Rise time, SDA Input tolerance 20 300 ns
tr(SCL) Rise time, SCL Input tolerance 20 300 ns
tf(SDA) Fall time, SDA Input tolerance 11.4 300 ns
tf(SCL) Fall time, SCL Input tolerance 11.4 300 ns
Setup time, STOP condition, SCL rise before
tsu(SCL-SDA)STOP 0.6 µs
SDA rise delay
Table 5-68. I2C Switching Characteristics

fSCL SCL clock frequency 0 400 kHz
tw(SCLL) Pulse duration, SCL clock low 1.3 µs
tw(SCLH) Pulse duration, SCL clock high 0.6 µs
Pulse duration of spikes that will be
tw(SP) 0 50 ns
suppressed by the input filter
Bus free time between STOP and START
tBUF 1.3 µs
conditions
tv(SCL-DAT) Valid time, data after SCL fall 0.9 µs
tv(SCL-ACK) Valid time, Acknowledge after SCL fall 0.9 µs
VIL Valid low-level input voltage –0.3 0.3 * VDDIO V
VIH Valid high-level input voltage 0.7 * VDDIO VDDIO + 0.3 V
VOL Low-level output voltage Sinking 3 mA 0 0.4 V
II Input current on pins 0.1 Vbus < Vi < 0.9 Vbus –10 10 µA

TMS320F28379S, TMS320F28377S
5.10.3 Multichannel Buffered Serial Port (McBSP)

The McBSP module has the following features:
• Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
• Full-duplex communication
• Double-buffered data registers that allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• 8-bit data transfer mode can be configured to transmit with LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
• Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
• Supports AC97, I2S, and SPI protocols
• McBSP clock rate,
CLKSRG
CLKG =
(1 + CLKGDV )
where CLKSRG source could be LSPCLK, CLKX, or CLKR.

TMS320F28379S, TMS320F28377S
Figure 5-59 shows the block diagram of the McBSP module.
TX
MXINT Interrupt
Peripheral Write Bus CPU
To CPU TX Interrupt Logic
McBSP Transmit 16 16
Interrupt Select Logic
PERx.LSPCLK DXR2 Transmit Buffer DXR1 Transmit Buffer

16 MFSXx
16
Compand Logic MCLKXx
XSR2 XSR1 MDXx

Peripheral Bus
Bridge
RSR1 MDRx
CPU DMA Bus RSR2
16
MCLKRx
16 Expand Logic
MFSRx
RBR2 Register RBR1 Register
16 16
DRR2 Receive Buffer DRR1 Receive Buffer
McBSP Receive
Interrupt Select Logic 16 16
RX
MRINT RX Interrupt Logic Interrupt
Peripheral Read Bus CPU
To CPU
Figure 5-59. McBSP Block Diagram

TMS320F28379S, TMS320F28377S
5.10.3.1 McBSP Electrical Data and Timing
5.10.3.1.1 McBSP Transmit and Receive Timing

Table 5-69 shows the McBSP timing requirements. Table 5-70 shows the McBSP switching
characteristics. Figure 5-60 and Figure 5-61 show the McBSP timing diagrams.
Table 5-69. McBSP Timing Requirements (1) (2)
NO. MIN MAX UNIT

1 kHz
McBSP module clock (CLKG, CLKX, CLKR) range
25 MHz
40 ns
McBSP module cycle time (CLKG, CLKX, CLKR) range
1 ms
M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P ns
M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–7 ns
M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns
M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns
CLKR int 18
M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low ns
CLKR ext 2
CLKR int 0
M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low ns
CLKR ext 6
CLKR int 18
M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 5
CLKR int 0
M18 th(CKRL-DRV) Hold time, DR valid after CLKR low ns
CLKR ext 3
CLKX int 18
M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low ns
CLKX ext 2
CLKX int 0
M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns
CLKX ext 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).

TMS320F28379S, TMS320F28377S
Table 5-70. McBSP Switching Characteristics (1) (2)

M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P ns
(3) (3)
M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D–5 D+5 ns
(3) (3)
M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C–5 C+5 ns
CLKR int 0 4
M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid ns
CLKR ext 3 27
CLKX int 0 4
M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns
CLKX ext 3 27
Disable time, CLKX high to DX high impedance CLKX int 8
M6 tdis(CKXH-DXHZ) ns
following last data bit CLKX ext 14
Delay time, CLKX high to DX valid. CLKX int 9
This applies to all bits except the first bit
CLKX ext 28
transmitted.
Delay time, CLKX high to DX CLKX int 8
M7 td(CKXH-DXV) DXENA = 0 ns
valid CLKX ext 14
Only applies to first bit CLKX int P+8
transmitted when in Data
DXENA = 1
Delay 1 or 2 (XDATDLY=01b CLKX ext P + 14
or 10b) modes
Enable time, CLKX high to CLKX int 0
DXENA = 0
DX driven CLKX ext 6
M8 ten(CKXH-DX) Only applies to first bit CLKX int P ns
DXENA = 1
Delay 1 or 2 (XDATDLY=01b CLKX ext P+6
or 10b) modes
Delay time, FSX high to DX FSX int 8
DXENA = 0
valid FSX ext 14
M9 td(FXH-DXV) Only applies to first bit FSX int P+8 ns
DXENA = 1
Delay 0 (XDATDLY=00b) FSX ext P + 14
mode.
Enable time, FSX high to DX FSX int 0
DXENA = 0
driven FSX ext 6
M10 ten(FXH-DX) Only applies to first bit FSX int P ns
DXENA = 1
Delay 0 (XDATDLY=00b) FSX ext P+6
mode
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P

TMS320F28379S, TMS320F28377S
M1, M11
M2, M12
M13
M3, M12
CLKR
M4 M4 M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR Bit (n−1) (n−2) (n−3) (n−4)

(RDATDLY=00b)
M17
M18
DR Bit (n−1) (n−2) (n−3)
(RDATDLY=01b)
M17 M18
DR Bit (n−1) (n−2)
(RDATDLY=10b)
Figure 5-60. McBSP Receive Timing
M1, M11
M2, M12 M13
M3, M12
CLKX
M5 M5
FSX (int)
M19
M20
FSX (ext)
M9
M10 M7
DX
(XDATDLY=00b) Bit 0 Bit (n−1) (n−2) (n−3)
M7
M8
DX
(XDATDLY=01b) Bit 0 Bit (n−1) (n−2)
M6 M7
M8
DX
(XDATDLY=10b) Bit 0 Bit (n−1)
Figure 5-61. McBSP Transmit Timing

TMS320F28379S, TMS320F28377S
5.10.3.1.2 McBSP as SPI Master or Slave Timing

For CLKSTP = 10b and CLKXP = 0, Table 5-71 shows the timing requirements, Table 5-72 shows the
switching characteristics, and Figure 5-62 shows the timing diagram.
Table 5-71. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns
M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high 8P + 10 ns
M33 tc(CKX) Cycle time, CLKX 2P (2) 16P ns
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 5-72. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating
Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P (1) ns
M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P ns
Disable time, DX high impedance following
M28 tdis(FXH-DXHZ) 6 6P + 6 ns
last data bit from FSX high
M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns
(1) 2P = 1/CLKG
LSB M32 MSB M33

CLKX
M24 M25
FSX
M28 M29
DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M30
M31
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Figure 5-62. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

TMS320F28379S, TMS320F28377S
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns
M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high 16P + 10 ns
CLKGDV = 1.
(2) 2P = 1/CLKG
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M34 th(CKXL-FXL) Hold time, FSX low after CLKX low P ns
M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P (1) ns
Disable time, DX high impedance following last data bit
M37 tdis(CKXL-DXHZ) P+6 7P + 6 ns
from CLKX low
(1) 2P = 1/CLKG
MSB M42
LSB M41
CLKX
M34 M35
FSX
M37 M38
DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M39
M40
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

TMS320F28379S, TMS320F28377S
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 30 8P – 10 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 8P – 10 ns
M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 8P + 10 ns
CLKGDV = 1.
(2) 2P = 1/CLKG
MASTER SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M43 th(CKXH-FXL) Hold time, FSX low after CLKX high 2P (1) ns
M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P ns
Disable time, DX high impedance following last data bit from
M47 tdis(FXH-DXHZ) 6 6P + 6 ns
FSX high
(1) 2P = 1/CLKG
LSB M51 MSB M52

CLKX
M43 M44
FSX
M47 M48
DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M49
M50
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

TMS320F28379S, TMS320F28377S
MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 30 8P – 10 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 1 8P – 10 ns
M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low 16P + 10 ns
CLKGDV = 1.
(2) 2P = 1/CLKG
Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1) (1)
MASTER (2) SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
M53 th(CKXH-FXL) Hold time, FSX low after CLKX high P ns
M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P (1) ns
M55 td(CLKXH-DXV) Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns
Disable time, DX high impedance following last
M56 tdis(CKXH-DXHZ) P+6 7P + 6 ns
data bit from CLKX high
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60 MSB M61

LSB
CLKX
M53 M54
FSX
M56 M57 M55
DX Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

M58
M59
DR Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

TMS320F28379S, TMS320F28377S
5.10.4 Serial Communications Interface (SCI)

The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard non-
return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register. Figure 5-66 shows the SCI block diagram.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wakeup multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
• Auto baud-detect hardware logic
• 16-level transmit and receive FIFO
NOTE
All registers in this module are 8-bit registers. When a register is accessed, the register data
is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the
upper byte has no effect.

TMS320F28379S, TMS320F28377S
SCICTL1.1
Frame Format and Mode SCITXD

TXSHF SCITXD
Parity Register TXENA
TX EMPTY
Even/Odd Enable
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY TX INT ENA
Transmitter-Data
Buffer Register SCICTL2.7
TXWAKE SCICTL2.0
8
SCICTL1.3
TX FIFO _0
TX FIFO Interrupt TX Interrupt TXINT
1 TX FIFO _1
Logic
−−−−−
To CPU
TX FIFO _15
WUT SCITXBUF.7−0 SCI TX Interrupt select logic
TX FIFO registers
SCIFFENA Auto baud detect logic

SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Baud Rate SCIRXD
MSbyte Register
Register RXWAKE
LSPCLK SCIRXST.1
SCILBAUD. 7 − 0 RXENA
SCICTL1.0
Baud Rate 8
LSbyte SCICTL2.1
Register RXRDY RX/BK INT ENA
Receive Data
Buffer register SCIRXST.6
SCIRXBUF.7−0
8 BRKDT
RX FIFO _15 SCIRXST.5

−−−−−
RX FIFO_1
RX Interrupt RXINT
RX FIFO _0
RX FIFO Interrupt Logic To CPU
SCIRXBUF.7−0
RX FIFO registers
RXFFOVF
SCIRXST.7 SCIRXST.4 – 2
SCIFFRX.15
RX Error FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 5-66. SCI Block Diagram

TMS320F28379S, TMS320F28377S
The major elements used in full-duplex operation include:

• A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts
data onto the SCITXD pin, 1 bit at a time
• A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data
from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and
SCIRXEMU registers
• A programmable baud generator
• Data-memory-mapped control and status registers enable the CPU to access the I2C module registers
and FIFOs.
The SCI receiver and transmitter operate independently.

TMS320F28379S, TMS320F28377S
5.10.5 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of
programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The SPI is normally used for communications between the microcontroller and external peripherals or
another controller. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI. The port supports 16-level receive and transmit FIFOs for reducing
CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
• 16-level transmit and receive FIFO
• Delayed transmit control
• 3-wire SPI mode
• SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
• DMA support
• High-speed mode for up to 50-MHz full-duplex communication

TMS320F28379S, TMS320F28377S
The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK
signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the
SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit
(SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result,
both controllers send and receive data simultaneously. The application software determines whether the
data is meaningful or dummy data. There are three possible methods for data transmission:
• Master sends data; slave sends dummy data
• Master sends data; slave sends data
• Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
Figure 5-67 shows the SPI CPU Interface.
PCLKCR8
Low-Speed
LSPCLK
Prescaler
SYSCLK CPU
Bit
Peripheral Bus
Clock
SYSRS
SPISIMO
GPIO SPISOMI
MUX SPICLK
SPI SPIINT
SPITXINT PIE
SPISTE
SPIRXDMA
SPITXDMA DMA
Figure 5-67. SPI CPU Interface

TMS320F28379S, TMS320F28377S
5.10.5.1 SPI Electrical Data and Timing

The following sections contain the SPI External Timings in Non-High-Speed Mode:
Section 5.10.5.1.1 Master Mode External Timings Where Clock Phase = 0

Section 5.10.5.1.2 Master Mode External Timings Where Clock Phase = 1
Section 5.10.5.1.3 Slave Mode External Timings Where Clock Phase = 0
Section 5.10.5.1.4 Slave Mode External Timings Where Clock Phase = 1
The following sections contain the SPI External Timings in High-Speed Mode:
Section 5.10.5.1.5 High-Speed Master Mode External Timings Where Clock Phase = 0
Section 5.10.5.1.6 High-Speed Master Mode External Timings Where Clock Phase = 1
Section 5.10.5.1.7 High-Speed Slave Mode External Timings Where Clock Phase = 0
Section 5.10.5.1.8 High-Speed Slave Mode External Timings Where Clock Phase = 1
NOTE
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on
SPICLK, SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter
of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see
Section 4.5.5).

TMS320F28379S, TMS320F28377S
5.10.5.1.1 Master Mode External Timings Where Clock Phase = 0

Table 5-79 shows the SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2.
Table 5-80 shows the SPI master mode external timings where (SPIBRR + 1) is odd and SPIBRR > 3.
Figure 5-68 shows the SPI master mode external timing where the clock phase = 0.
Table 5-79. SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2
NO. MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) ns
Pulse duration, SPICLK high
tw(SPCH)M 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
(clock polarity = 0)
2 ns
Pulse duration, SPICLK low
tw(SPCL)M 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 ns
Delay time, SPICLK high to SPISIMO valid
td(SPCH-SIMO)M 3
4 ns
Delay time, SPICLK low to SPISIMO valid
td(SPCL-SIMO)M 3
Valid time, SPISIMO data valid after SPICLK
tv(SPCL-SIMO)M 0.5tc(SPC)M – 3
low (clock polarity = 0)
5 ns
tv(SPCH-SIMO)M 0.5tc(SPC)M – 3
high (clock polarity = 1)
Setup time, SPISOMI before SPICLK low
tsu(SOMI-SPCL)M 20
8 ns
Setup time, SPISOMI before SPICLK high
tsu(SOMI-SPCH)M 20
Hold time, SPISOMI data valid after SPICLK
th(SPCL-SOMI)M 0
9 ns
th(SPCH-SOMI)M 0
Delay time, SPISTE low to SPICLK high (clock
td(STE-SPCH)M 0.5tc(SPC) – 3
polarity = 0)
23 ns
Delay time, SPISTE low to SPICLK low (clock
td(STE-SPCL)M 0.5tc(SPC) – 3
polarity = 1)
Delay time, SPICLK low to SPISTE invalid
td(SPCL-STE)M 0.5tc(SPC) – 3
24 ns
Delay time, SPICLK high to SPISTE invalid
td(SPCH-STE)M 0.5tc(SPC) – 3

TMS320F28379S, TMS320F28377S
Table 5-80. SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3
NO. MIN MAX UNIT
tw(SPCH)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1
2 ns
tw(SPCL)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1
3 ns
Delay time, SPICLK high to SPISIMO
td(SPCH-SIMO)M 3
valid (clock polarity = 0)
4 ns
Delay time, SPICLK low to SPISIMO
td(SPCL-SIMO)M 3
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3
SPICLK low (clock polarity = 0)
5 ns
tv(SPCH-SIMO)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
tsu(SOMI-SPCL)M 20
8 ns
tsu(SOMI-SPCH)M 20
Hold time, SPISOMI data valid after
th(SPCL-SOMI)M 0
9 ns
th(SPCH-SOMI)M 0
Delay time, SPISTE low to SPICLK
23 ns
Delay time, SPICLK low to SPISTE
invalid (clock polarity = 0)
24 ns
Delay time, SPICLK high to SPISTE

TMS320F28379S, TMS320F28377S
SPICLK
SPICLK
4
5
SPISIMO Master Out Data Is Valid
Master In Data
SPISOMI
Must Be Valid
23 24
(A)
SPISTE
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
Figure 5-68. SPI Master Mode External Timing (Clock Phase = 0)

TMS320F28379S, TMS320F28377S
5.10.5.1.2 Master Mode External Timings Where Clock Phase = 1

Table 5-81 shows the SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2.
Table 5-82 shows the SPI master mode external timings where (SPIBRR + 1) is odd or SPIBRR > 3.
Figure 5-69 shows the SPI master mode external timing where the clock phase = 1.
Table 5-81. SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2
NO. MIN MAX UNIT
2 ns
tw(SPCL))M 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 ns
Delay time, SPISIMO data valid to SPICLK
td(SIMO-SPCH)M 0.5tc(SPC)M – 3
6 ns
Delay time, SPISIMO data valid to SPICLK low
td(SIMO-SPCL)M 0.5tc(SPC)M – 3
7 ns
tsu(SOMI-SPCH)M 20
10 ns
tsu(SOMI-SPCL)M 20
th(SPCH-SOMI)M 0
11 ns
th(SPCL-SOMI)M 0
polarity = 0)
23 ns
polarity = 1)
24 ns

TMS320F28379S, TMS320F28377S
Table 5-82. SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3
NO. MIN MAX UNIT
tw(SPCH)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1
2 ns
tw(SPCL))M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1
tw(SPCL)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1
3 ns
Delay time, SPISIMO data valid to
td(SIMO-SPCH)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
6 ns
td(SIMO-SPCL)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 3
7 ns
tv(SPCL-SIMO)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
tsu(SOMI-SPCH)M 20
10 ns
tsu(SOMI-SPCL)M 20
th(SPCH-SOMI)M 0
11 ns
th(SPCL-SOMI)M 0
23 ns
Delay time, SPISTE low to SPICLK low
24 ns
1
SPICLK
2
SPICLK
6
7
10
11
SPISOMI Master In Data Must

Be Valid
24
(A) 23
SPISTE
non-FIFO modes.
Figure 5-69. SPI Master Mode External Timing (Clock Phase = 1)

TMS320F28379S, TMS320F28377S
5.10.5.1.3 Slave Mode External Timings Where Clock Phase = 0

Table 5-83 and Figure 5-70 show the SPI slave mode external timings where the clock phase = 0.
Table 5-83. SPI Slave Mode External Timings Where Clock Phase = 0
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 2tc(SYSCLK) – 1
13 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 2tc(SYSCLK) – 1
14 ns
td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 20
15 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 20
Valid time, SPISOMI data valid after SPICLK high
tv(SPCH-SOMI)S 0
16 ns
Valid time, SPISOMI data valid after SPICLK low
tv(SPCL-SOMI)S 0
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 5
19 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 5
Hold time, SPISIMO data valid after SPICLK low
th(SPCL-SIMO)S 5
20 ns
Hold time, SPISIMO data valid after SPICLK high
th(SPCH-SIMO)S 5
Setup time, SPISTE valid before SPICLK high
tsu(STE-SPCH)S 2tc(SYSCLK)
25 ns
Setup time, SPISTE valid before SPICLK low
tsu(STE-SPCL)S 2tc(SYSCLK)
th(SPCL-STE)S Hold time, SPISTE invalid after SPICLK low (clock polarity = 0) 2tc(SYSCLK)
26 ns
th(SPCH-STE)S Hold time, SPISTE invalid after SPICLK high (clock polarity = 1) 2tc(SYSCLK)

TMS320F28379S, TMS320F28377S
12
SPICLK
13
14
SPICLK
15
16
SPISOMI SPISOMI Data Is Valid
19
20
SPISIMO Data
SPISIMO
Must Be Valid
25 26
SPISTE
Figure 5-70. SPI Slave Mode External Timing (Clock Phase = 0)

TMS320F28379S, TMS320F28377S
5.10.5.1.4 Slave Mode External Timings Where Clock Phase = 1

Table 5-84 and Figure 5-71 show the SPI slave mode external timings where the clock phase = 1.
Table 5-84. SPI Slave Mode External Timings Where Clock Phase = 1
NO. MIN MAX UNIT
13 ns
14 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI (clock polarity = 0) 20
17 ns
td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI (clock polarity = 1) 20
tv(SPCL-SOMI)S 0
18 ns
tv(SPCH-SOMI)S 0
21 ns
th(SPCH-SIMO)S 5
22 ns
th(SPCL-SIMO)S 5
tsu(STE-SPCH)S Setup time, SPISTE valid before SPICLK high (clock polarity = 0) 2tc(SYSCLK)
25 ns
tsu(STE-SPCL)S Setup time, SPISTE valid before SPICLK low (clock polarity = 1) 2tc(SYSCLK)
th(STE-SPCL)S Hold time, SPISTE invalid after SPICLK low (clock polarity = 0) 2tc(SYSCLK)
26 ns
th(STE-SPCH)S Hold time, SPISTE invalid after SPICLK high (clock polarity = 1) 2tc(SYSCLK)
12
SPICLK
13 14
SPICLK
17
SPISOMI SPISOMI Data Is Valid Data Valid Data Valid
21 18
22
SPISIMO SPISIMO Data

Must Be Valid
25 26
SPISTE
Figure 5-71. SPI Slave Mode External Timing (Clock Phase = 1)

TMS320F28379S, TMS320F28377S
5.10.5.1.5 High-Speed Master Mode External Timings Where Clock Phase = 0

Table 5-85 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is even or
SPIBRR = 0 or 2.
Table 5-86 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is odd and
SPIBRR > 3.
Figure 5-72 shows the high-speed SPI master mode external timing where the clock phase = 0.
Table 5-85. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Even or
SPIBRR = 0 or 2
NO. MIN MAX UNIT
2 ns
3 ns
Delay time, SPICLK high to SPISIMO valid
td(SPCH-SIMO)M 1
4 ns
Delay time, SPICLK low to SPISIMO valid
td(SPCL-SIMO)M 1
5 ns
tsu(SOMI-SPCL)M 1
8 ns
tsu(SOMI-SPCH)M 1
th(SPCL-SOMI)M 5
9 ns
th(SPCH-SOMI)M 5
polarity = 0)
23 ns
polarity = 1)
24 ns

TMS320F28379S, TMS320F28377S
Table 5-86. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3
NO. MIN MAX UNIT
2 ns
3 ns
Delay time, SPICLK high to SPISIMO
td(SPCH-SIMO)M 1
4 ns
Delay time, SPICLK low to SPISIMO
td(SPCL-SIMO)M 1
tv(SPCL-SIMO)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
5 ns
tsu(SOMI-SPCL)M 1
8 ns
tsu(SOMI-SPCH)M 1
th(SPCL-SOMI)M 5
9 ns
th(SPCH-SOMI)M 5
23 ns
24 ns

TMS320F28379S, TMS320F28377S
SPICLK
SPICLK
4
5
Master In Data
SPISOMI
Must Be Valid
23 24
(A)
SPISTE
non-FIFO modes.
Figure 5-72. High-Speed SPI Master Mode External Timing (Clock Phase = 0)

TMS320F28379S, TMS320F28377S
5.10.5.1.6 High-Speed Master Mode External Timings Where Clock Phase = 1

Table 5-87 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is even or
SPIBRR = 0 or 2.
Table 5-88 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is odd or
SPIBRR > 3.
Figure 5-73 shows the high-speed SPI master mode external timing where the clock phase = 1.
Table 5-87. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Even or
SPIBRR = 0 or 2
NO. MIN MAX UNIT
2 ns
tw(SPCL))M 0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
3 ns
Delay time, SPISIMO data valid to SPICLK
td(SIMO-SPCH)M 0.5tc(SPC)M – 1
6 ns
Delay time, SPISIMO data valid to SPICLK low
td(SIMO-SPCL)M 0.5tc(SPC)M – 1
7 ns
tsu(SOMI-SPCH)M 1
10 ns
tsu(SOMI-SPCL)M 1
th(SPCH-SOMI)M 5
11 ns
th(SPCL-SOMI)M 5
polarity = 0)
23 ns
polarity = 1)
24 ns

TMS320F28379S, TMS320F28377S
Table 5-88. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3
NO. MIN MAX UNIT
2 ns
tw(SPCL))M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1
tw(SPCL)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1
3 ns
td(SIMO-SPCH)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
6 ns
td(SIMO-SPCL)M 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
7 ns
tv(SPCL-SIMO)M 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
tsu(SOMI-SPCH)M 1
10 ns
tsu(SOMI-SPCL)M 1
th(SPCH-SOMI)M 5
11 ns
th(SPCL-SOMI)M 5
23 ns
Delay time, SPISTE low to SPICLK low
24 ns
1
SPICLK
2
SPICLK
6
7
10
11
SPISOMI Master In Data Must

Be Valid
24
(A) 23
SPISTE
non-FIFO modes.
Figure 5-73. High-Speed SPI Master Mode External Timing (Clock Phase = 1)
TMS320F28379S, TMS320F28377S
5.10.5.1.7 High-Speed Slave Mode External Timings Where Clock Phase = 0

Table 5-89 and Figure 5-74 show the high-speed SPI slave mode external timings where the clock
phase = 0.
Table 5-89. High-Speed SPI Slave Mode External Timings Where Clock Phase = 0
NO. MIN MAX UNIT
13 ns
14 ns
td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 9
15 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 9
tv(SPCH-SOMI)S 0
16 ns
tv(SPCL-SOMI)S 0
19 ns
th(SPCL-SIMO)S 5
20 ns
th(SPCH-SIMO)S 5
Setup time, SPISTE valid before SPICLK high
tsu(STE-SPCH)S 2tc(SYSCLK)
25 ns
Setup time, SPISTE valid before SPICLK low
tsu(STE-SPCL)S 2tc(SYSCLK)
th(SPCL-STE)S Hold time, SPISTE invalid after SPICLK low (clock polarity = 0) 2tc(SYSCLK)
26 ns
th(SPCH-STE)S Hold time, SPISTE invalid after SPICLK high (clock polarity = 1) 2tc(SYSCLK)

TMS320F28379S, TMS320F28377S
12
SPICLK
13
14
SPICLK
15
16
SPISOMI SPISOMI Data Is Valid
19
20
SPISIMO Data
SPISIMO
Must Be Valid
25 26
SPISTE
Figure 5-74. High-Speed SPI Slave Mode External Timing (Clock Phase = 0)

TMS320F28379S, TMS320F28377S
5.10.5.1.8 High-Speed Slave Mode External Timings Where Clock Phase = 1

Table 5-90 and Figure 5-75 show the high-speed SPI slave mode external timings where the clock
phase = 1.
Table 5-90. High-Speed SPI Slave Mode External Timings Where Clock Phase = 1
NO. MIN MAX UNIT
13 ns
14 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI (clock polarity = 0) 9
17 ns
td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI (clock polarity = 1) 9
tv(SPCL-SOMI)S 0
18 ns
tv(SPCH-SOMI)S 0
21 ns
th(SPCH-SIMO)S 5
22 ns
th(SPCL-SIMO)S 5
tsu(STE-SPCH)S Setup time, SPISTE valid before SPICLK high (clock polarity = 0) 2tc(SYSCLK)
25 ns
tsu(STE-SPCL)S Setup time, SPISTE valid before SPICLK low (clock polarity = 1) 2tc(SYSCLK)
th(STE-SPCL)S Hold time, SPISTE invalid after SPICLK low (clock polarity = 0) 2tc(SYSCLK)
26 ns
th(STE-SPCH)S Hold time, SPISTE invalid after SPICLK high (clock polarity = 1) 2tc(SYSCLK)
12
SPICLK
13 14
SPICLK
17
SPISOMI SPISOMI Data Is Valid Data Valid Data Valid
21 18
22
SPISIMO SPISIMO Data

Must Be Valid
25 26
SPISTE
Figure 5-75. High-Speed SPI Slave Mode External Timing (Clock Phase = 1)

TMS320F28379S, TMS320F28377S
5.10.6 Universal Serial Bus (USB) Controller

The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 5-76 shows the USB block diagram.
Endpoint Control
Transmit
EP0 –31
Control
Receive
CPU Interface
Interrupt Interrupts
Host
Combine Control
Transaction
Endpoints
Scheduler
EP Reg.
Decoder
Common CPU Bus

UTM Packet FIFO RAM
Synchronization Encode/Decode Controller Regs
USB PHY Rx Rx
Data Sync Packet Encode
Buff Buff Cycle
Control
HNP/SRP Packet Decode Tx Tx
Buff Buff
USB FS/LS
PHY FIFO
Timers CRC Gen/Check Cycle Control
Decoder
USB DataLines
D+ andD-
Figure 5-76. USB Block Diagram
NOTE
The accuracy of the on-chip zero-pin oscillator (Table 5-18, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external
clock source must be used for applications using USB. For applications using the USB boot
mode, see Section 6.9 (Boot ROM and Peripheral Booting) for clock frequency requirements.

TMS320F28379S, TMS320F28377S
5.10.6.1 USB Electrical Data and Timing

Table 5-91 shows the USB input ports DP and DM timing requirements. Table 5-92 shows the USB output
ports DP and DM switching characteristics.
Table 5-91. USB Input Ports DP and DM Timing Requirements

MIN MAX UNIT
V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic-low level 0.8 V
VIH Static SE input logic-high level 2.0 V
VDI Differential input voltage 0.2 V
Table 5-92. USB Output Ports DP and DM Switching Characteristics

VOH D+, D– single-ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D– single-ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D– impedance 28 44 Ω
Full speed, differential, CL = 50 pF, 10%/90%,
tr Rise time 4 20 ns
Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%,
tf Fall time 4 20 ns
Rpu on D+

TMS320F28379S, TMS320F28377S
5.10.7 Universal Parallel Port (uPP) Interface

The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals.
The uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It
can also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve
high-speed digital data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU
overhead during high-speed data transmission. All uPP transactions use internal DMA to feed data to or
retrieve data from the I/O channels. Even though there is only one I/O channel, the DMA controller
includes two DMA channels to support data interleave mode, in which all DMA resources service a single
I/O channel.
On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1,
and CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG
RAMs) are tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to
store the bulk of data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have
access to these data RAMs. Figure 5-77 shows the integration of the uPP on this device.
CPU1 RX-DATARAM
Arbi READ
512 Byte
Arbiter Y
(Dual Port
t Memory)
CPU1.CLA1
uPP DMA WRITE
CPU1
I/O Interface
Arbi uPP
Arbiter X
(Universal
CPU1.CLA1 0 t Parallel Port)
CPU1.DMA 1
uPP DMA READ
SECMSEL.PF2SEL
CPU1 TX-DATARAM
Arbi WRITE
512 Byte
Arbiter Y
(Dual Port
t Memory)
CPU1.CLA1
Figure 5-77. uPP Integration
NOTE
On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI)
module.

TMS320F28379S, TMS320F28377S
The uPP interface supports the following:

• Mainstream high-speed data converters with parallel conversion interface.
• Mainstream high-speed streaming interface with frame START indication.
• Mainstream high-speed streaming interface with data ENABLE indication.
• Mainstream high-speed streaming interface with synchronization WAIT signal.
• SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
• Multiplexing of interleaved data in SDR transmit case.
• Demultiplexing and multiplexing of interleaved data in DDR case.
• I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
• Single-channel 8-bit input receive or output transmit mode.
• Max throughput is 50MB/s for pure read or pure write.
• Available as a DSP to FPGA general-purpose streaming interface.
Figure 5-78 shows the uPP functional block diagram.
uPP
Configuration ENABLE OUT G

MMR ENABLE/GPIOx
I/F
Transmit Timing START OUT P
and Control I
WAIT IN
O
CLK OUT START/GPIOx
CPU1.SYSCLK CLKDIVIDER
M
CLK IN
U
ENABLE IN WAIT/GPIOx
X
Receive Timing
Interrupt/Trigger Control Mux START IN
and Control
WAIT OUT and
CLK/GPIOx
I/O
Arbi
I-FIFO C
64 Bit t O
MEM WR I/F DATA OUT N
DATA[7:0]/GPIOx
Internal Data Interleaving T
DMA
Arbit (TX/RX) DATA IN
R
O
64 Bit
L
MEM RD I/F Arbi
Q-FIFO
Figure 5-78. uPP Functional Block Diagram

TMS320F28379S, TMS320F28377S
5.10.7.1 uPP Electrical Data and Timing

Table 5-93 shows the uPP timing requirements. Table 5-94 shows the uPP switching characteristics.
Figure 5-79 through Figure 5-82 show the uPP timing diagrams.
Table 5-93. uPP Timing Requirements

NO. MIN MAX UNIT
SDR mode 20
1 tc(CLK) Cycle time, CLK ns
DDR mode 40
SDR mode 8
2 tw(CLKH) Pulse width, CLK high ns
DDR mode 18
SDR mode 8
3 tw(CLKL) Pulse width, CLK low ns
DDR mode 18
4 tsu(STV-CLKH) Setup time, START valid before CLK high 4 ns
5 th(CLKH-STV) Hold time, START valid after CLK high 0.8 ns
6 tsu(ENV-CLKH) Setup time, ENABLE valid before CLK high 4 ns
7 th(CLKH-ENV) Hold time, ENABLE valid after CLK high 0.8 ns
8 tsu(DV-CLKH) Setup time, DATA valid before CLK high 4 ns
9 th(CLKH-DV) Hold time, DATA valid after CLK high 0.8 ns
10 tsu(DV-CLKL) Setup time, DATA valid before CLK low 4 ns
11 th(CLKL-DV) Hold time, DATA valid after CLK low 0.8 ns
19 tsu(WTV-CLKH) Setup time, WAIT valid before CLK high SDR mode 20 ns
20 th(CLKH-WTV) Hold time, WAIT valid after CLK high SDR mode 0 ns
21 tsu(WTV-CLKL) Setup time, WAIT valid before CLK low DDR mode 20 ns
22 th(CLKL-WTV) Hold time, WAIT valid after CLK low DDR mode 0 ns
Table 5-94. uPP Switching Characteristics

SDR mode 20
12 tc(CLK) Cycle time, CLK ns
DDR mode 40
SDR mode 8
13 tw(CLKH) Pulse width, CLK high ns
DDR mode 18
SDR mode 8
14 tw(CLKL) Pulse width, CLK low ns
DDR mode 18
15 td(CLKH-STV) Delay time, START valid after CLK high 3 12 ns
16 td(CLKH-ENV) Delay time, ENABLE valid after CLK high 3 12 ns
17 td(CLKH-DV) Delay time, DATA valid after CLK high 3 12 ns
18 td(CLKL-DV) Delay time, DATA valid after CLK low 3 12 ns

TMS320F28379S, TMS320F28377S
1 2 3
CLK
4
5
START
6
7
ENABLE
WAIT
8
9
DATA[n:0] Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9
Figure 5-79. uPP Single Data Rate (SDR) Receive Timing
1 2 3
CLK
4
5
START
6
7
ENABLE
WAIT
8 10
9 11
DATA[n:0] I1 Q1 I2 Q2 I3 Q3 I4 Q4 I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
Figure 5-80. uPP Double Data Rate (DDR) Receive Timing

TMS320F28379S, TMS320F28377S
12 13 14
CLK
15
START
16
ENABLE
19 20
WAIT
17
DATA[n:0] Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9
Figure 5-81. uPP Single Data Rate (SDR) Transmit Timing
12 13 14
CLK
15
START
16
ENABLE
21
22
WAIT
17 18
DATA[n:0] I1 Q1 I2 Q2 I3 Q3 I4 Q4 I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
Figure 5-82. uPP Double Data Rate (DDR) Transmit Timing

TMS320F28379S, TMS320F28377S
6 Detailed Description
6.1 Overview
The Delfino TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz
of signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which
enables fast execution of algorithms with trigonometric operations common in transforms and torque loop
calculations; and the VCU accelerator, which reduces the time for complex math operations common in
encoded applications.
The F2837xS microcontroller family features a CLA real-time control co-processor. The CLA is an
independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA
responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel
processing capability can effectively double the computational performance of a real-time control system.
By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such
as communications and diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code
(ECC) and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for
code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable
system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple
analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM)
works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The
Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when
current limit conditions are exceeded or not met. Other analog and control peripherals include DACs,
PWMs, eCAPs, eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO11898-1/CAN 2.0B-compliant), and a new uPP interface
extend the connectivity of the F2837xS. The uPP interface is a new feature of the C2000 MCUs and
supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly,
a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their
application.
6.2 Functional Block Diagram

Figure 6-1 shows the CPU system and associated peripherals.
176 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated

TMS320F28379S, TMS320F28377S
MEMCPU1
CPU1.CLA1 to CPU1 Low-Power

CPU1.CLA1 C28 CPU-1 User-Configurable Mode Control
GPIO MUX
128x16 MSG RAM
CPU1 to CPU1.CLA1 DCSM
FPU PSWD
OTP
128x16 MSG RAM VCU-II Dual 1K x 16
TMU Code
Security (F28377S, F23875S only)
Module Flash Bank 0 Flash Bank 1
Watchdog INTOSC1
CPU1 Local Shared + 256K x 16
256K x 16
6x 2Kx16 Emulation Secure
Secure Memories Code
Secure
LS0-LS5 RAMs
shown in Red Security PUMP
Logic
CPU1.D0 RAM 2Kx16 (ECSL)
(F28377S, F28375S only)
Flash Wrapper for Main PLL INTOSC2
CPU1.D1 RAM 2Kx16 WD Timer Flash Wrapper for
Bank 0
NMI-WDT Bank 1
CPU Timer 0 External Crystal or

CPU1.M0 RAM 1Kx16 Oscillator
CPU Timer 1
A5:0 16-/12-bit ADC CPU Timer 2
A CPU1.M1 RAM 1Kx16
x4 Aux PLL
B5:0 B ePIE Global Shared AUXCLKIN
C (up to 192 16x 4Kx16
ADC
C5:2 Analog D Result
Secure-ROM 32Kx16 interrupts) GS0-GS15 RAMs
Secure TRST
MUX Config Regs
Boot-ROM 32Kx16
CPU1.CLA1 Bus
D5:0 Nonsecure TCK
JTAG TDI
ADCIN14
Data Bus TMS
ADCIN15 Bridge CPU1.CLA1 Data ROM CPU1.DMA
(4Kx16) TDO
Comparator
DAC CPU1 Buses
Subsystem
(CMPSS) x3
Data Bus Data Bus Data Bus Data Bus Data Bus
Peripheral Frame 1 Data Bus Bridge Bridge Bridge Peripheral Frame 2 Bridge Bridge Bridge
ePWM-1/../12 SCI- USB CAN- SPI- RAM

eCAP- I2C-A/B
1/../6
eQEP-1/2/3 SDFM-1/2 A/B/C/D Ctrl / A/B A/B/C McBSP-A/B uPP EMIF1 EMIF2 GPIO
(16L FIFO)
HRPWM-1/../8 (16L FIFO) PHY (32-MBOX) (16L FIFO)
EXTSYNCOUT
UPPAD[7:0]
EPWMxB
EPWMxA
SCITXDx
CANTXx
SPISIMOx
SPISOMIx
UPPACLK
EM1CTLx
EM2CTLx
SPICLKx
MCLKRx
SPISTEx
MCLKXx
UPPAWT
UPPAEN
EQEPxS
EXTSYNCIN
UPPAST
USBDM
SDx_Dy
SDx_Cy
EQEPxI
MDXx
USBDP
MFSRx
SCIRXDx
MFSXx
EM1Dx
EM1Ax
EM2Dx
EM2Ax
GPIOn
CANRXx
EQEPxB
ECAPx
EQEPxA
TZ1-TZ6
MRXx
SDAx
SCLx
GPIO MUX, Input X-BAR, Output X-BAR
Figure 6-1. Functional Block Diagram
Copyright © 2014–2016, Texas Instruments Incorporated Detailed Description 177

TMS320F28379S, TMS320F28377S
6.3 Memory
6.3.1 C28x Memory Map

The C28x memory map is described in Table 6-1. Memories accessible by the CLA or DMA (direct
memory access) are noted as well.
Table 6-1. C28x Memory Map

MEMORY SIZE START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
M0 RAM 1K × 16 0x0000 0000 0x0000 03FF
M1 RAM 1K × 16 0x0000 0400 0x0000 07FF
PieVectTable 512 × 16 0x0000 0D00 0x0000 0EFF
CLA to CPU MSGRAM 128 × 16 0x0000 1480 0x0000 14FF Yes
CPU to CLA MSGRAM 128 × 16 0x0000 1500 0x0000 157F Yes
UPP TX MSG RAM 512 × 16 0x0000 6C00 0x0000 6DFF Yes
UPP RX MSG RAM 512 × 16 0x0000 6E00 0x0000 6FFF Yes
LS0 RAM 2K × 16 0x0000 8000 0x0000 87FF Yes
LS1 RAM 2K × 16 0x0000 8800 0x0000 8FFF Yes
LS2 RAM 2K × 16 0x0000 9000 0x0000 97FF Yes
LS3 RAM 2K × 16 0x0000 9800 0x0000 9FFF Yes
LS4 RAM 2K × 16 0x0000 A000 0x0000 A7FF Yes
LS5 RAM 2K × 16 0x0000 A800 0x0000 AFFF Yes
D0 RAM 2K × 16 0x0000 B000 0x0000 B7FF
D1 RAM 2K × 16 0x0000 B800 0x0000 BFFF
GS0 RAM 4K × 16 0x0000 C000 0x0000 CFFF Yes
GS1 RAM 4K × 16 0x0000 D000 0x0000 DFFF Yes
GS2 RAM 4K × 16 0x0000 E000 0x0000 EFFF Yes
GS3 RAM 4K × 16 0x0000 F000 0x0000 FFFF Yes
GS4 RAM 4K × 16 0x0001 0000 0x0001 0FFF Yes
GS5 RAM 4K × 16 0x0001 1000 0x0001 1FFF Yes
GS6 RAM 4K × 16 0x0001 2000 0x0001 2FFF Yes
GS7 RAM 4K × 16 0x0001 3000 0x0001 3FFF Yes
GS8 RAM 4K × 16 0x0001 4000 0x0001 4FFF Yes
GS9 RAM 4K × 16 0x0001 5000 0x0001 5FFF Yes
GS10 RAM 4K × 16 0x0001 6000 0x0001 6FFF Yes
GS11 RAM 4K × 16 0x0001 7000 0x0001 7FFF Yes
GS12 RAM (1) 4K × 16 0x0001 8000 0x0001 8FFF Yes
GS13 RAM (1) 4K × 16 0x0001 9000 0x0001 9FFF Yes
GS14 RAM (1) 4K × 16 0x0001 A000 0x0001 AFFF Yes
GS15 RAM (1) 4K × 16 0x0001 B000 0x0001 BFFF Yes
CAN A Message RAM 2K × 16 0x0004 9000 0x0004 97FF
CAN B Message RAM 2K × 16 0x0004 B000 0x0004 B7FF
Flash Bank 0 256K × 16 0x0008 0000 0x000B FFFF
Flash Bank 1 256K × 16 0x000C 0000 0x000F FFFF
Secure ROM 32K × 16 0x003F 0000 0x003F 7FFF
Boot ROM 32K × 16 0x003F 8000 0x003F FFBF
Vectors 64 × 16 0x003F FFC0 0x003F FFFF
(1) Available only on F28379S, F28377S, and F28375S.

TMS320F28379S, TMS320F28377S
6.3.2 Flash Memory Map

The F28379S, F28377S, and F28375S devices have two flash banks [512KB (256KW) each] for a total of
1MB (512KW). Only one bank can be programmed or erased at a time. The Flash API can be executed
from RAM, or since there are two Flash banks for one CPU, the Flash API code can be executed from
one bank to erase/program the other bank. Note that an extra wait state is automatically added when code
is fetched or data is read from Bank 1 (compared to that of Bank 0), even for prefetched data. See
Section 5.7.4 for details on flash wait states. Table 6-2 shows the addresses of flash sectors.
Table 6-2. Addresses of Flash Sectors on F28379S, F28377S, and F28375S

SECTOR SIZE START ADDRESS END ADDRESS
OTP Sectors
TI OTP Bank 0 1K × 16 0x0007 0000 0x0007 03FF
User configurable DCSM OTP
1K × 16 0x0007 8000 0x0007 83FF
Bank 0
TI OTP Bank 1 1K × 16 0x0007 0800 0x0007 0BFF
1K × 16 0x0007 8800 0x0007 8BFF
Bank 1
Bank 0 Sectors
Sector A 8K × 16 0x0008 0000 0x0008 1FFF
Sector B 8K × 16 0x0008 2000 0x0008 3FFF
Sector C 8K × 16 0x0008 4000 0x0008 5FFF
Sector D 8K × 16 0x0008 6000 0x0008 7FFF
Sector E 32K × 16 0x0008 8000 0x0008 FFFF
Sector F 32K × 16 0x0009 0000 0x0009 7FFF
Sector G 32K × 16 0x0009 8000 0x0009 FFFF
Sector H 32K × 16 0x000A 0000 0x000A 7FFF
Sector I 32K × 16 0x000A 8000 0x000A FFFF
Sector J 32K × 16 0x000B 0000 0x000B 7FFF
Sector K 8K × 16 0x000B 8000 0x000B 9FFF
Sector L 8K × 16 0x000B A000 0x000B BFFF
Sector M 8K × 16 0x000B C000 0x000B DFFF
Sector N 8K × 16 0x000B E000 0x000B FFFF
Bank 1 Sectors
Sector O 8K × 16 0x000C 0000 0x000C 1FFF
Sector P 8K × 16 0x000C 2000 0x000C 3FFF
Sector Q 8K × 16 0x000C 4000 0x000C 5FFF
Sector R 8K × 16 0x000C 6000 0x000C 7FFF
Sector S 32K × 16 0x000C 8000 0x000C FFFF
Sector T 32K × 16 0x000D 0000 0x000D 7FFF
Sector U 32K × 16 0x000D 8000 0x000D FFFF
Sector V 32K × 16 0x000E 0000 0x000E 7FFF
Sector W 32K × 16 0x000E 8000 0x000E FFFF
Sector X 32K × 16 0x000F 0000 0x000F 7FFF
Sector Y 8K × 16 0x000F 8000 0x000F 9FFF
Sector Z 8K × 16 0x000F A000 0x000F BFFF
Sector AA 8K × 16 0x000F C000 0x000F DFFF
Sector AB 8K × 16 0x000F E000 0x000F FFFF
Flash ECC Locations
TI OTP ECC Bank 0 128 × 16 0x0107 0000 0x0107 007F

TMS320F28379S, TMS320F28377S
Table 6-2. Addresses of Flash Sectors on F28379S, F28377S, and F28375S (continued)
User-configurable DCSM OTP
128 × 16 0x0107 1000 0x0107 107F
ECC Bank 0
128 × 16 0x0107 1200 0x0107 127F
ECC Bank 1
Flash ECC Bank 0 32K × 16 0x0108 0000 0x0108 7FFF
Flash ECC Bank 1 32K × 16 0x0108 8000 0x0108 FFFF
The F28376S and F28374S devices have one flash bank of 512KB (256KW) and the code to program the
flash should be executed out of RAM. See Section 5.7.4 for details on flash wait states. Table 6-3 shows
the addresses of flash sectors.
Table 6-3. Addresses of Flash Sectors on F28376S and F28374S

OTP Sectors
TI OTP Bank 0 1K × 16 0x0007 0000 0x0007 03FF
1K × 16 0x0007 8000 0x0007 83FF
Bank 0
Bank 0 Sectors
Sector A 8K × 16 0x0008 0000 0x0008 1FFF
Sector B 8K × 16 0x0008 2000 0x0008 3FFF
Sector C 8K × 16 0x0008 4000 0x0008 5FFF
Sector D 8K × 16 0x0008 6000 0x0008 7FFF
Sector E 32K × 16 0x0008 8000 0x0008 FFFF
Sector F 32K × 16 0x0009 0000 0x0009 7FFF
Sector G 32K × 16 0x0009 8000 0x0009 FFFF
Sector H 32K × 16 0x000A 0000 0x000A 7FFF
Sector I 32K × 16 0x000A 8000 0x000A FFFF
Sector J 32K × 16 0x000B 0000 0x000B 7FFF
Sector K 8K × 16 0x000B 8000 0x000B 9FFF
Sector L 8K × 16 0x000B A000 0x000B BFFF
Sector M 8K × 16 0x000B C000 0x000B DFFF
Sector N 8K × 16 0x000B E000 0x000B FFFF
Flash ECC Locations
128 × 16 0x0107 1000 0x0107 107F
ECC Bank 0
Flash ECC Bank 0 32K × 16 0x0108 0000 0x0108 7FFF

TMS320F28379S, TMS320F28377S
6.3.3 EMIF Chip Select Memory Map

The EMIF memory map is shown in Table 6-4.
Table 6-4. EMIF Chip Select Memory Map

EMIF CHIP SELECT SIZE START ADDRESS END ADDRESS CLA ACCESS DMA ACCESS
EMIF1_CS0n - Data 256M × 16 0x8000 0000 0x8FFF FFFF Yes
EMIF1_CS2n - Program + Data 2M × 16 0x0010 0000 0x002F FFFF Yes
EMIF1_CS3n - Program + Data 512K × 16 0x0030 0000 0x0037 FFFF Yes
EMIF1_CS4n - Program + Data 393K × 16 0x0038 0000 0x003D FFFF Yes
EMIF2_CS0n - Data 64M × 16 0x9000 0000 0x93FF FFFF
EMIF2_CS2n - Program + Data 4K × 16 0x0000 2000 0x0000 2FFF Yes (Data only)
6.3.4 Peripheral Registers Memory Map

The peripheral registers memory map can be found in Table 6-5. Registers in the peripheral frames share
a secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See
the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for details on the CPU
subsystem and secondary master selection.
Table 6-5. Peripheral Registers Memory Map

START END CLA DMA
REGISTERS STRUCTURE NAME PROTECTED(1)
ADDRESS ADDRESS ACCESS ACCESS
AdcaResultRegs ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes
AdcbResultRegs ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes
AdccResultRegs ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes
AdcdResultRegs ADC_RESULT_REGS 0x0000 0B60 0x0000 0B7F Yes Yes
CpuTimer0Regs CPUTIMER_REGS 0x0000 0C00 0x0000 0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000 0C10 0x0000 0C17
PieCtrlRegs PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF
Yes –
CLA only,
Cla1SoftIntRegs CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF
no CPU
access
DmaRegs DMA_REGS 0x0000 1000 0x0000 11FF
Cla1Regs CLA_REGS 0x0000 1400 0x0000 147F
Peripheral Frame 1
EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes
EPwm11Regs EPWM_REGS 0x0000 4A00 0x0000 4AFF Yes Yes Yes
EPwm12Regs EPWM_REGS 0x0000 4B00 0x0000 4BFF Yes Yes Yes
ECap1Regs ECAP_REGS 0x0000 5000 0x0000 501F Yes Yes Yes

TMS320F28379S, TMS320F28377S
Table 6-5. Peripheral Registers Memory Map (continued)

START END CLA DMA
ECap6Regs ECAP_REGS 0x0000 50A0 0x0000 50BF Yes Yes Yes
EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes
EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes
EQep3Regs EQEP_REGS 0x0000 5180 0x0000 51BF Yes Yes Yes
DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes
DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes
DaccRegs DAC_REGS 0x0000 5C20 0x0000 5C2F Yes Yes Yes
Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes
Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes
Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes
Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes
Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes
Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes
Sdfm2Regs SDFM_REGS 0x0000 5E80 0x0000 5EFF Yes Yes Yes
Peripheral Frame 2
McbspaRegs MCBSP_REGS 0x0000 6000 0x0000 603F Yes Yes Yes
McbspbRegs MCBSP_REGS 0x0000 6040 0x0000 607F Yes Yes Yes
SpiaRegs SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes
SpibRegs SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes
SpicRegs SPI_REGS 0x0000 6120 0x0000 612F Yes Yes Yes
UppRegs UPP_REGS 0x0000 6200 0x0000 62FF Yes Yes Yes
WdRegs WD_REGS 0x0000 7000 0x0000 703F Yes

NmiIntruptRegs NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes
XintRegs XINT_REGS 0x0000 7070 0x0000 707F Yes
SciaRegs SCI_REGS 0x0000 7200 0x0000 720F Yes
ScibRegs SCI_REGS 0x0000 7210 0x0000 721F Yes
ScicRegs SCI_REGS 0x0000 7220 0x0000 722F Yes
ScidRegs SCI_REGS 0x0000 7230 0x0000 723F Yes
I2caRegs I2C_REGS 0x0000 7300 0x0000 733F Yes
I2cbRegs I2C_REGS 0x0000 7340 0x0000 737F Yes
AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes
AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes
AdccRegs ADC_REGS 0x0000 7500 0x0000 757F Yes Yes
AdcdRegs ADC_REGS 0x0000 7580 0x0000 75FF Yes Yes
InputXbarRegs INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes
XbarRegs XBAR_REGS 0x0000 7920 0x0000 793F Yes
TrigRegs TRIG_REGS 0x0000 7940 0x0000 794F Yes
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 798F Yes
EPwmXbarRegs EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes
OutputXbarRegs OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes
GpioCtrlRegs GPIO_CTRL_REGS 0x0000 7C00 0x0000 7D7F Yes
GpioDataRegs GPIO_DATA_REGS 0x0000 7F00 0x0000 7F2F Yes Yes
UsbaRegs USB_REGS 0x0004 0000 0x0004 0FFF Yes
Emif1Regs EMIF_REGS 0x0004 7000 0x0004 77FF Yes
Emif2Regs EMIF_REGS 0x0004 7800 0x0004 7FFF Yes
CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes
CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes

TMS320F28379S, TMS320F28377S
Table 6-5. Peripheral Registers Memory Map (continued)

START END CLA DMA
FlashPumpSemaphoreRegs FLASH_PUMP_SEMAPHORE_REGS 0x0005 0024 0x0005 0025 Yes
DevCfgRegs DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes
AnalogSubsysRegs ANALOG_SUBSYS_REGS 0x0005 D180 0x0005 D1FF Yes
ClkCfgRegs CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes
CpuSysRegs CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes
RomPrefetchRegs ROM_PREFETCH_REGS 0x0005 E608 0x0005 E60B Yes
DcsmZ1Regs DCSM_Z1_REGS 0x0005 F000 0x0005 F02F Yes
DcsmZ2Regs DCSM_Z2_REGS 0x0005 F040 0x0005 F05F Yes
DcsmCommonRegs DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes
MemCfgRegs MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes
Emif1ConfigRegs EMIF1_CONFIG_REGS 0x0005 F480 0x0005 F49F Yes
Emif2ConfigRegs EMIF2_CONFIG_REGS 0x0005 F4A0 0x0005 F4BF Yes
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes
RomWaitStateRegs ROM_WAIT_STATE_REGS 0x0005 F540 0x0005 F541 Yes
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes
Flash0EccRegs FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes
Flash1CtrlRegs FLASH_CTRL_REGS 0x0005 FC00 0x0005 FEFF Yes
Flash1EccRegs FLASH_ECC_REGS 0x0005 FF00 0x0005 FF3F Yes
(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.

TMS320F28379S, TMS320F28377S
6.3.5 Memory Types

Table 6-6 provides more information about each memory type.
Table 6-6. Memory Types

HIBERNATE ACCESS
MEMORY TYPE ECC-CAPABLE PARITY SECURITY
RETENTION PROTECTION
M0, M1 Yes – – Yes –
D0, D1 Yes – Yes – Yes
LSx – Yes Yes – Yes
GSx – Yes – – Yes
CPU/CLA MSGRAM – Yes Yes – Yes
Boot ROM – – – N/A –
Secure ROM – – Yes N/A –
Flash Yes – Yes N/A N/A
User-configurable DCSM OTP Yes – Yes N/A N/A
6.3.5.1 Dedicated RAM (Mx and Dx RAM)

The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1
memories are small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has
access to them). D0/D1 memories are secure blocks and also have the access-protection feature (CPU
write/CPU fetch protection).
6.3.5.2 Local Shared RAM (LSx RAM)

RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU
write/CPU fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 6-7 shows the master access for the LSx RAM.
Table 6-7. Master Access for LSx RAM

(With Assumption That all Other Access Protections are Disabled)
CPU ALLOWED CLA ALLOWED
MSEL_LSx CLAPGM_LSx COMMENT
ACCESS ACCESS
LSx memory is configured
00 X All –
as CPU dedicated RAM.
Data Read LSx memory is shared
01 0 All
Data Write between CPU and CLA1.
Emulation Read LSx memory is CLA1
01 1 Fetch Only
Emulation Write program memory.

TMS320F28379S, TMS320F28377S
6.3.5.3 Global Shared RAM (GSx RAM)

RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx
RAMs). Both the CPU and DMA have full read and write access to these memories.
All GSx RAM blocks have parity.
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
6.3.5.4 CLA Message RAM (CLA MSGRAM)

These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.

TMS320F28379S, TMS320F28377S
6.4 Identification
Table 6-8 shows the Device Identification Registers.
Table 6-8. Device Identification Registers

NAME ADDRESS SIZE (x16) DESCRIPTION
Device part identification number
TMS320F28379S 0x00F9 0400
TMS320F28377S 0x00FF 0400
PARTIDH 0x0005 D00A 2
TMS320F28376S 0x00FE 0400
TMS320F28375S 0x00FD 0400
TMS320F28374S 0x00FC 0400
Silicon revision number
REVID 0x0005 D00C 2 Revision B 0x0000 0002
Revision C 0x0000 0003
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
UID_UNIQUE 0x0007 03C0 2
a serial number in the application. This number is present only
on TMS Revision C devices.

TMS320F28379S, TMS320F28377S
6.5 Bus Architecture – Peripheral Connectivity

Table 6-9 shows a broad view of the peripheral and configuration register accessibility from each bus
master. Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master
as a group (if SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA).
Table 6-9. Bus Master Peripheral Access

PERIPHERALS
CPU1.DMA CPU1.CLA1 CPU1
(BY BUS ACCESS TYPE)
Peripheral Frame 1:
• ePWM/HRPWM
• SDFM
• eCAP (1) Y Y Y
• eQEP (1)
• CMPSS (1)
• DAC (1)
Peripheral Frame 2:
• SPI
Y Y Y
• McBSP
• uPP (1)
SCI Y
I2C Y
CAN Y
ADC Configuration Y Y
EMIF1 Y Y
EMIF2 Y Y
USB Y
Device Capability, Peripheral Reset, Peripheral CPU Select Y
GPIO Pin Mapping and Configuration Y
Analog System Control Y
uPP Message RAMs Y Y
Reset Configuration Y
Clock and PLL Configuration Y
System Configuration
Y
(WD, NMIWD, LPM, Peripheral Clock Gating)
Flash Configuration Y
CPU Timers Y
DMA and CLA Trigger Source Select Y
GPIO Data (2) Y Y
ADC Results Y Y Y
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for each CPU1 and CPU1.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more details.

TMS320F28379S, TMS320F28377S
6.6 C28x Processor

The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide.
6.6.1 Floating-Point Unit

The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
6.6.2 Trigonometric Math Unit

The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in
Table 6-10.
Table 6-10. TMU Supported Instructions

INSTRUCTIONS C EQUIVALENT OPERATION PIPELINE CYCLES
MPY2PIF32 RaH,RbH a = b * 2pi 2/3
DIV2PIF32 RaH,RbH a = b / 2pi 2/3
DIVF32 RaH,RbH,RcH a = b/c 5
SQRTF32 RaH,RbH a = sqrt(b) 5
SINPUF32 RaH,RbH a = sin(b*2pi) 4
COSPUF32 RaH,RbH a = cos(b*2pi) 4
ATANPUF32 RaH,RbH a = atan(b)/2pi 4
QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed
explanation of the workings of the FPU can be found in the TMS320C28x Extended Instruction Sets

TMS320F28379S, TMS320F28377S
6.6.3 Viterbi, Complex Math, and CRC Unit II

The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The
VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the
performance of Fast Fourier Transforms (FFTs) and communications-based algorithms. The C28x+VCU-II
supports the following algorithm types:
• Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode
algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly),
and a traceback operation. Table 6-11 shows a summary of the VCU performance for each of these
operations.
Table 6-11. Viterbi Decode Performance

VITERBI OPERATION VCU CYCLES
Branch Metric Calculation (code rate = 1/2) 1
Branch Metric Calculation (code rate = 1/3) 2p
Viterbi Butterfly (add-compare-select) 2 (1)
Traceback per Stage 3 (2)
(1) C28x CPU takes 15 cycles per butterfly.
(2) C28x CPU takes 22 cycles per stage.
• Cyclic Redundancy Check

Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit,
16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10
bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC
instruction is executed.
• Complex Math
Complex math is used in many applications, a few of which are:
– Fast Fourier Transform
The complex FFT is used in spread spectrum communications, as well as in many signal
processing algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The
C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single
cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data
to memory in a single cycle.
Table 6-12 shows a summary of the VCU operations enabled by the VCU.
Table 6-12. Complex Math Performance

COMPLEX MATH OPERATION VCU CYCLES NOTES
Add or Subtract 1 32 +/- 32 = 32-bit (Useful for filters)
Add or Subtract 1 16 +/- 32 = 15-bit (Useful for FFT)
Multiply 2p 16 x 16 = 32-bit
Multiply and Accumulate (MAC) 2p 32 + 32 = 32-bit, 16 x 16 = 32-bit
RPT MAC 2p+N Repeat MAC. Single cycle after the first operation.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

TMS320F28379S, TMS320F28377S
6.7 Control Law Accelerator

The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch
mechanism, and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or
a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a
time to completion. When a task completes, the main CPU is notified by an interrupt to the PIE and the
CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC
Result registers, ePWM, eCAP, eQEP, Comparator and DAC registers. Dedicated message RAMs provide
a method to pass additional data between the main CPU and the CLA.
Figure 6-2 shows the CLA block diagram.
CLA Control
Register Set
MIFR(16) CLA_INT1
From MPERINT1 to
MIOVF(16)
Shared to MICLR(16) CLA_INT8
Peripherals MPERINT8 MICLROVF(16) INT11 C28x
PIE
MIFRC(16) INT12 CPU
MIER(16)
MIRUN(16)
LVF
LUF
MVECT1(16)
MVECT2(16)
MVECT3(16)
SYSCLK MVECT4(16)
CLA Clock Enable MVECT5(16)
SYSRSn CPU Read/Write Data Bus
MVECT6(16)
MVECT7(16)
MVECT8(16) CLA Program
CLA Program Bus Memory (LSx)
MCTL(16)
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
CPU Data Bus

CLA Data
CLA Execution Memory (LSx)
CLA Data Bus
Register Set
MPC(16) CLA Message
MSTF(32) RAMs
MR0(32)
MR1(32)
MR2(32) Shared
MR3(32) Peripherals
MAR0(16) MEALLOW
MAR1(16)
CPU Read Data Bus
Figure 6-2. CLA Block Diagram

TMS320F28379S, TMS320F28377S
6.8 Direct Memory Access

The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of
transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing
up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally
rearrange the data as it is transferred as well as “ping-pong” data between buffers. These features are
useful for structuring data into blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start
a DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the
interrupt trigger source, there is no mechanism within the module itself to start memory transfers
periodically. The interrupt trigger source for each of the six DMA channels can be configured separately
and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer
has either started or completed. Five of the six channels are exactly the same, while Channel 1 has the
ability to be configured at a higher priority than the others.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– Multichannel buffered serial port transmit and receive
– External interrupts
– CPU timers
– EPWMxSOC signals
– SPIx transmit and receive
– SDFM
– Software trigger
• Data sources and destinations:
– GSx RAM
– ADC result registers
– ePWMx
– SPI
– McBSP
– EMIF
• Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
• Throughput: four cycles/word (without arbitration)

TMS320F28379S, TMS320F28377S
Figure 6-3 shows a device-level block diagram of the DMA.
ADC ADC Global Shared

WRAPPER XINT TIMER
RESULTS 16x 4Kx16
(4) (5) (3)
(4) GS0-15 RAMs
C28x Bus
DMA Bus
TINT (0-2)
DMA_CHx (1-6)
XINT (1-5) DMA Trigger
Source Selection
ADC INT (A-D) (1-4), EVT (A-D) DMACHSRCSEL1.CHx DMA C28x
SDxFLTy (x = 1 to 2, y = 1 to 4) DMACHSRCSEL2.CHx
SOCA (1-12), SOCB (1-12) CHx.MODE.PERINTSEL
MXEVT (A-B), MREVT (A-B) (x = 1 to 6)
PIE
SPITX (A-C), SPIRX (A-C)
DMA Trigger Source

CPU and DMA Data Path
CMPSS
eQEP
eCAP
DAC
SDFM EPWM McBSP SPI

(8) (12) (2) (3) EMIF1
Figure 6-3. DMA Block Diagram

TMS320F28379S, TMS320F28377S
6.9 Boot ROM and Peripheral Booting

The device boot ROM contains bootloading software. The device boot ROM is executed each time the
device comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to
boot the device through one of the bootable peripherals by configuring the boot mode GPIO pins.
Table 6-13 shows the possible boot modes supported on the device. The default boot mode pins are
GPIO72 (boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for
boot mode pins if they use a peripheral on these pins as well, so the pullups can be overdriven. On this
device, customers can change the factory default boot mode pins by programming user-configurable Dual
Code Security Module (DCSM) OTP locations. This is recommended only for cases in which the factory
default boot mode pins do not fit into the customer design. More details on the locations to be
programmed is available in the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
Table 6-13. Device Boot Mode

GPIO72 GPIO84
(BOOT (BOOT
MODE NO. CPU1 BOOT MODE TRST
MODE MODE
PIN 1) PIN 0)
0 Parallel IO 0 0 0
1 SCI Mode 0 0 1
2 Wait Boot Mode 0 1 0
3 Get Mode 0 1 1
4-7 EMU Boot Mode (Emulator Connected) 1 X X
NOTE
The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get
mode will result in repeated watchdog resets, which may prevent proper JTAG connection
and device initialization. Use Wait mode or another boot mode for unprogrammed devices.
CAUTION
Some reset sources are internally driven by the device. The user must ensure
the pins used for boot mode are not actively driven by other devices in the
system for these cases. The boot configuration has a provision for changing the
boot pins in OTP. For more details, see the TMS320F2837xS Delfino

TMS320F28379S, TMS320F28377S
6.9.1 EMU Boot or Emulation Boot

The CPU enters this boot when it detects that TRST is HIGH (in other words, when an emulator/debugger
is connected). In this mode, the user can program the EMUBOOTCTRL register (at location 0xD00) to
instruct the device on how to boot. If the contents of the EMUBOOTCTRL locations are invalid, then the
device would default into WAIT Boot mode. The emulation boot allows users to verify the device boot
before programming the boot mode into OTP.
6.9.2 WAIT Boot Mode

The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a
debugger on a secure device or if users do not want the device to execute an application in flash yet.
6.9.3 Get Mode

The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-
OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this
device is divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a
valid OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the
Z1-OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-
OTPBOOTCTRL is invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed,
then the device defaults to factory default operation, which is to use factory default boot mode pins to boot
to flash if the boot mode pins are set to GET MODE. Users can choose the device through which to
boot—SPI, I2C, CAN, and USB—by programming proper values into the user configurable DCSM OTP.
More details on this can be found in the TMS320F2837xS Delfino Microcontrollers Technical Reference
Manual.

TMS320F28379S, TMS320F28377S
6.9.4 Peripheral Pins Used by Bootloaders

Table 6-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of
GPIOs for each mode, as shown in Table 6-14.
Table 6-14. GPIO Pins Used by Each Peripheral Bootloader

BOOTLOADER GPIO PINS NOTES
SCITXDA: GPIO84 SCIA Boot IO option 1 (default SCI option
SCI-Boot0
SCIRXDA: GPIO85 when chosen through Boot Mode GPIOs)
SCITXDA: GPIO28
SCI-Boot1 SCIA Boot option 2 – with alternate IOs.
SCIRXDA: GPIO29
D0 – GPIO65
D1 – GPIO64
D2 – GPIO58
D3 – GPIO59
D4 – GPIO60
Parallel Boot
D5 – GPIO61
D6 – GPIO62
D7 – GPIO63
HOST_CTRL – GPIO70
DSP_CTRL – GPIO69
CANRXA: GPIO70
CAN-Boot0 CAN-A Boot -IO Option 1
CANTXA: GPIO71
CANRXA: GPIO62
CAN-Boot1 CAN-A Boot -IO option 2
CANTXA: GPIO63
SDAA: GPIO91
I2C-Boot0 I2CA Boot- IO option 1
SCLA: GPIO92
SDAA: GPIO32
I2C-Boot1 I2CA Boot- IO option 2
SCLA: GPIO33
SPISIMOA - GPIO58
SPISOMIA - GPIO59
SPI-Boot0 SPIA Boot- IO Option 1
SPICLKA - GPIO60
SPISTEA - GPIO61
SPISIMOA – GPIO16
SPISOMIA – GPIO17
SPI-Boot1 SPIA Boot - IO Option 2
SPICLKA – GPIO18
SPISTEA – GPIO19
The USB Bootloader will switch the clock
source to the external crystal oscillator (X1
USB0DM - GPIO42
USB Boot and X2 pins). A 20-MHz crystal should be
USB0DP - GPIO43
present on the board if this boot mode is
selected.

TMS320F28379S, TMS320F28377S
6.10 Dual Code Security Module

The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure”
means access to secure memories and resources is blocked. The term “unsecure” means access is
allowed; for example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP
memory and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for
each zone is stored in an OTP memory location based on a zone-specific link pointer. The link pointer
value can be changed to program a different set of security settings (including passwords) in OTP.
6.11 Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register that generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and is connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of
the CPU. If TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLK (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• X1 (XTAL)
• AUXPLLCLK
6.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)

The NMIWD module is used to handle system-level errors. The conditions monitored are:
• Missing system clock due to oscillator failure
• Uncorrectable ECC error on CPU access to flash memory
• Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after
a programmable time interval. The default time is 65536 SYSCLK cycles.

TMS320F28379S, TMS320F28377S
6.13 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional
lower limit on the time between software resets of the counter. This windowed countdown is disabled by
default, so the watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a
selectable frequency divider.
Figure 6-4 shows the various functional blocks within the watchdog module.
WDCR(WDPS(2:0)) WDCR(WDDIS)
WDCNTR(7:0)
Watchdog 8-bit 1 WDCLK

OSCCLK /512 WDCLK Overflow
Prescaler Watchdog delay
Counter
SYSRSn
Clear
Count
WDWCR(MIN(7:0))
WDKEY(7:0) Watchdog
In Window
Watchdog Window
Good Key Out of Window
Key Detector Detector
Bad Key
55 + AA
Generate
WDRSn
512-OSCCLK
WDINTn Watchdog Time-out
Output Pulse
SCSR(WDENINT)
Figure 6-4. Windowed Watchdog
6.14 Configurable Logic Block (CLB)

TI uses the CLB to offer additional interfacing and control features for select C2000 devices. Functions
that would otherwise be accomplished using external logic devices are now provided by on-chip TI
solutions. For example, absolute encoder master protocol interfaces such as EnDat and BiSS are now
provided as Position Manager solutions. Configuration files, application programmer’s interface (API), and
use examples for such solutions are provided with the C2000 controlSUITE software package. In some
solutions, the TI-configured CLB is used with other on-chip resources, such as the SPI port or the C28x
CPU, to perform more complex functionality. In some cases, external communications transceivers may
need to be added. See Table 3-1 for the devices that support the CLB feature.

TMS320F28379S, TMS320F28377S
7 Applications, Implementation, and Layout
NOTE
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 TI Design or Reference Design

TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download designs at TIDesigns.
Industrial Servo Drive and AC Inverter Drive Reference Design
The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly
connecting to a three-phase ACI or PMSM motor. Many drive topologies can be created from the
combined control, power, and communications technologies included on this single platform. This platform
includes multiple position sensor interfaces, diverse current sensing techniques, hot-side partitioning
options, and expansion for safety and industrial Ethernet.
Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for differential ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative
measurement circuit with external differential SAR ADCs as well as circuits for high-speed overcurrent and
earth fault detection. Proper differential signal conditioning improves noise immunity on critical current
measurements in motor drives. This reference design can help increase the effective resolution of the
analog-to-digital conversion, improving motor drive efficiency.
198 Applications, Implementation, and Layout Copyright © 2014–2016, Texas Instruments Incorporated
TMS320F28379S, TMS320F28377S
8 Device and Documentation Support

8.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28379S). Texas Instruments recommends two
of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PTP) and temperature range (for example, T). Figure 8-1 provides a legend
for reading the complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your
TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28379S,
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S Delfino Microcontrollers Silicon
Errata.
Copyright © 2014–2016, Texas Instruments Incorporated Device and Documentation Support 199
TMS320F28379S, TMS320F28377S
TMS 320 F 28379S PTP T
PREFIX TEMPERATURE RANGE

TMX = experimental device T = −40°C to 105°C (TJ)
TMP = prototype device
TMS = qualified device S = −40°C to 125°C (TJ)
Q = −40°C to 125°C (TA)
(Q refers to Q100 qualification for automotive applications.)
DEVICE FAMILY
320 = TMS320 MCU Family PACKAGE TYPE
337-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)
100-Pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP)
TECHNOLOGY
F = Flash
DEVICE
28379S
28377S
28376S
28375S
28374S
Figure 8-1. Device Nomenclature
8.2 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the
performance of the device, generate code, and develop solutions are listed below. To view all available
tools and software for C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Development Tools
F28379D controlCARD for C2000 Real time control development kits
The Delfino F28379D controlCARD from Texas Instruments is Position Manager-ready and an ideal
product for initial software development and short run builds for system prototypes, test stands, and many
other projects that require easy access to high-performance controllers. All C2000 controlCARDs are
complete board-level modules that utilize a HSEC180 or DIMM100 form factor to provide a low-profile
single-board controller solution. The host system needs to provide only a single 5V power rail to the
controlCARD for it to be fully functional.
F28379D Delfino Experimenter Kit
C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop
control development with Texas Instruments C2000 32-bit microcontroller family. This platform is a great
tool to customize and prove-out solutions for many common power electronics applications, including
motor control, digital power supplies, solar inverters, digital LED lighting, precision sensing, and more.
Software Tools
controlSUITE™ Software Suite
controlSUITE™ for C2000 microcontrollers is a cohesive set of software infrastructure and software tools
designed to minimize software development time.
Code Composer Studio (CCS) Integrated Development Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug
embedded applications. CCS includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin
multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
200 Device and Documentation Support Copyright © 2014–2016, Texas Instruments Incorporated
TMS320F28379S, TMS320F28377S
F021 Flash Application Programming Interface (API)

The F021 Flash Application Programming Interface (API) provides a software library of functions to
program, erase, and verify F021 on-chip Flash memory.
Training
C2000 Multi-Day Workshop
The C2000™ Microcontroller 3-Day Workshop will decrease the learning curve from months to days,
reduce development time, and accelerate product time to market! The workshop is perfect for both the
beginner and advanced users. Based on TI’s latest F28x7x devices, this workshop combines many of the
common features and peripherals found on the Piccolo™ and Delfino™ families, making it ideal for
anyone interested in learning about the C2000 MCU family of devices.
F2837xD Workshop
The F2837xD workshop is a hands-on technical course facilitated by qualified Texas Instruments'
instructors.
TMS320F28379S, TMS320F28377S
8.3 Documentation Support

To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (TMS320F28379S, TMS320F28377S, TMS320F28376S, TMS320F28375S,
TMS320F28374S). In the upper right-hand corner, click the "Alert me" button. This registers you to receive
a weekly digest of product information that has changed (if any). For change details, check the revision
history of any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
TMS320F28379S, TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S Delfino
Microcontrollers Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem
in the 2837xS microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This
Reference Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline,
and instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the
28x DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v15.12.0.LTS User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v15.12.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the
Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare
semiconductor devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful
lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at
general engineers who wish to determine if the reliability of the TI EP meets the end system reliability
requirement.
Getting Started With TMS320C28x Digital Signal Controllers provides tips on getting started with
TMS320C28x DSP software and hardware development to aid in initial design and debug efforts.
202 Device and Documentation Support Copyright © 2014–2016, Texas Instruments Incorporated
TMS320F28379S, TMS320F28377S
8.4 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TMS320F28379S Click here Click here Click here Click here Click here
8.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve
problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers
get started with Embedded Processors from Texas Instruments and to foster innovation and growth of
general knowledge about the hardware and software surrounding these devices.
8.6 Trademarks
PowerPAD, Delfino, C2000, TMS320C2000, Piccolo, controlSUITE, Code Composer Studio, TMS320,
E2E are trademarks of Texas Instruments.
Bosch is a registered trademark of Robert Bosch GmbH Corporation.
All other trademarks are the property of their respective owners.
8.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
TMS320F28379S, TMS320F28377S
9 Mechanical Packaging and Orderable Information

9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without
dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL
PAD MECHANICAL DATA figure.
204 Mechanical Packaging and Orderable Information Copyright © 2014–2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 21-Aug-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TMS320F28374SPTPS ACTIVE HLQFP PTP 176 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28374SPTPS
TMS320F28374SPTPT ACTIVE HLQFP PTP 176 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
& no Sb/Br) F28374SPTPT
TMS320F28374SPZPS ACTIVE HTQFP PZP 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28374SPZPS
TMS320F28374SPZPT ACTIVE HTQFP PZP 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 TMS320
& no Sb/Br) F28374SPZPT
TMS320F28374SZWTS ACTIVE NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28374SZWTS
TMS320F28374SZWTT ACTIVE NFBGA ZWT 337 1 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
& no Sb/Br) F28374SZWTT
TMS320F28375SPZPQ ACTIVE HTQFP PZP 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28375SPZPQ
TMS320F28375SPZPQR ACTIVE HTQFP PZP 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
TMS320F28375SZWTT ACTIVE NFBGA ZWT 337 90 TBD Call TI Call TI -40 to 105
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TMS320F28376SZWTT ACTIVE NFBGA ZWT 337 90 TBD Call TI Call TI -40 to 105
TMS320F28377SPTPQ ACTIVE HLQFP PTP 176 40 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28377SPTPQ
TMS320F28377SPZPQ ACTIVE HTQFP PZP 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS320
TMS320F28377SZWTQ ACTIVE NFBGA ZWT 337 90 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
& no Sb/Br) F28377SZWTQ
Addendum-Page 2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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TMS320F2837xS Delfino™ Microcontrollers

• Package Options: • Temperature Options:

2 Device Overview Copyright © 2014–2016, Texas Instruments Incorporated

Device Information (1)

Copyright © 2014–2016, Texas Instruments Incorporated Device Overview 3

1.4 Functional Block Diagram

CPU1.CLA1 to CPU1 Low-Power

CPU Timer 0 External Crystal or

D5:0 Nonsecure TCK

ePWM-1/../12 SCI- USB CAN- SPI- RAM

GPIO MUX, Input X-BAR, Output X-BAR

Copyright © 2016, Texas Instruments Incorporated

Figure 1-1. Functional Block Diagram

4 Device Overview Copyright © 2014–2016, Texas Instruments Incorporated

Copyright © 2014–2016, Texas Instruments Incorporated Table of Contents 5

• Global: Restructured document. ................................................................................................... 1

6 Revision History Copyright © 2014–2016, Texas Instruments Incorporated

Table 3-1. Device Comparison

FEATURE(1) 28379S 28377S 28376S 28375S 28374S

Conversion Time (ns)(2) 915 –

Conversion Time (ns)(2) 290

Copyright © 2014–2016, Texas Instruments Incorporated Device Comparison 7

Table 3-1. Device Comparison (continued)

Controller Area Network (CAN) – Type 0(4) 2

Inter-Integrated Circuit (I2C) – Type 0 2

Multichannel Buffered Serial Port (McBSP) –

Free-Air (5) No Yes No No Yes No

8 Device Comparison Copyright © 2014–2016, Texas Instruments Incorporated

3.1 Related Products

Copyright © 2014–2016, Texas Instruments Incorporated Device Comparison 9

4 Terminal Configuration and Functions

M VDDIO GPIO110 GPIO112 GPIO111 VDDIO VDDIO M VSS VSS VSS M

L GPIO27 GPIO106 GPIO107 GPIO108 VSS VSS L VSS VSS VSS L

K GPIO26 GPIO25 GPIO24 GPIO23 VDD VDD K VSS VSS VSS K

10 Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated

W GPIO29 FLT1 TDI TMS TDO GPIO121 GPIO39 GPIO132 VSS W

V GPIO28 GPIO115 FLT2 TRST TCK GPIO36 GPIO40 GPIO134 VDDIO V

U GPIO31 GPIO117 GPIO32 GPIO34 GPIO120 GPIO37 GPIO41 GPIO135 ERRORSTS U

T GPIO30 GPIO118 GPIO33 GPIO35 GPIO119 GPIO38 GPIO136 GPIO137 GPIO138 T

R VDD3VFL VDD3VFL VDD VSS VSS GPIO48 GPIO49 GPIO50 GPIO51 R

P VSS VSS VDD VSS VSS GPIO52 GPIO53 GPIO54 GPIO55 P

M VSS VSS M VSS VSS GPIO59 GPIO60 GPIO141 GPIO140 M

L VSS VSS L VDDIO VDDIO GPIO61 GPIO64 VSS GPIO142 L

K VSS VSS K VSS VSS GPIO65 GPIO66 GPIO44 GPIO45 K

Copyright © 2014–2016, Texas Instruments Incorporated Terminal Configuration and Functions 11

J VSS VSS J VDD VDD GPIO63 GPIO62 VREGENZ X2 J

H VSS VSS H VSS VSS VDDOSC VDDOSC VSSOSC VSSOSC H

G VDD VDD VSS VSS GPIO133 X1 G

F VDD VSS VDDIO VSS VSS VDDIO GPIO144 GPIO143 XRS F

E VDD VSS VDDIO VSS VSS VDDIO GPIO145 GPIO47 GPIO46 E

D GPIO87 GPIO156 GPIO152 GPIO148 GPIO80 GPIO75 GPIO147 GPIO146 GPIO42 D

C GPIO86 GPIO155 GPIO151 GPIO83 GPIO79 GPIO76 GPIO74 GPIO68 GPIO43 C

B GPIO85 GPIO154 GPIO150 GPIO82 GPIO78 GPIO72 GPIO71 GPIO69 GPIO67 B

A GPIO84 GPIO153 GPIO149 GPIO81 GPIO77 GPIO73 GPIO70 VDDIO VSS A

12 Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated

J GPIO103 GPIO104 GPIO105 GPIO22 VSS VSS J VSS VSS VSS J

H GPIO100 GPIO101 GPIO102 NC VDDIO VDDIO H VSS VSS VSS H