1

VLSI Design

Lab-02

“MOS Device Characteristics CMOS Layout Simulation and

Parametric Analysis”

1. Objectives

To become acquainted with MOS device characteristics and full custom design by using
Micro Wind tools. This lab consists of three parts. Part I is to analyse NMOS and PMOS
devices. Part II is to draw a layout of the gate for the logic function y=a. (b+c).Part III is
to simulate this layout and do its parametric analysis.

2.Theory

2.1 The MOS device

The n-channel MOS is built using polysilicon as the gate material and N+ diffusion to
make the source and drain. The p-channel MOS is built using polysilicon as the gate
material and P+ diffusion to make the source and drain.

Figure 3.1 NMOS and PMOS Symbols

2.2 The MOS Model

In this lab, the model 3 is employed. For the evaluation of the current Ids as a function of
Vd, Vg and Vs between Drain and Source, we use the equations on page 16 and 17 in the
manual of Micro Wind. The equations are derived from Model 1 and take into account a
set of physical limitations in a semi-empirical way.
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3. Labs

3.1 Part I: MOS Device Characteristics (30 minutes)

 Double click the icon “Micro Wind” The Micro Wind window pops up.

 File>Select foundry>

An “Open” window pops up. Select “cmos025.rul” and push “open” button.
In this lab, we use 0.25um CMOS technology.

 Simulate>MOS characteristics>

A “MOS Viewer” window pops up. In this window, we will analyse the characteristics
of MOS devices.

Select “NMOS” (lower right), “level3” (upper right), “W=10um L=10um”, “Id vs.Vd”.
Push the button “Draw Curve”, the display window displays several curves.
Find the Ids value with Vgs = 2V and Vds = 2V and fill it into table 1.

Select “NMOS” (lower right), “level3” (upper right), “W=0.60um L=10um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.
Find the Ids value with Vgs = 2V and Vds = 2V and fill it into table 1.

Select “NMOS” (lower right), “level3” (upper right), “W=10um L=0.30um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.
Find the Ids value with Vgs = 2V and Vds = 2V and fill it into table 1.

Select “NMOS” (lower right), “level3” (upper right), “W=0.60um L=0.30um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.
Find the Ids value with Vgs = 2V and Vds = 2V and fill it into table 1.
From this part, we can conclude that:

If W increases (L, Vds, Vgs are fixed), then Ids_________

If L increases (W, Vds, Vgs are fixed), then Ids__________
If Vds increases (W, L, Vgs are fixed), then Ids_________
If Vgs increases (W, L, Vds are fixed), then Ids__________
TABLE 1. NMOS
W L Vgs Vds Ids
10um 10um 2V 2V

0.6um 10um 2V 2V

10um 0.3um 2V 2V

0.6um 0.3um 2V 2V

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VLSI Design
Select “PMOS” (lower right), “level3” (upper right), “W=10um L=10um”, “Id vs.Vd”.
Push the button “Draw Curve”, the display window displays several curves. Find the
Ids value with Vgs = -2V and |Vds| = 2V and fill it into table 2.

Select “PMOS” (lower right), “level3” (upper right), “W=0.60um L=10um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.

Find the Ids value with Vgs = -2V and |Vds| = 2V and fill it into table 2.
Select “PMOS” (lower right), “level3” (upper right), “W=10um L=0.30um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.

Find the Ids value with Vgs = -2V and |Vds| = 2V and fill it into table 2.
Select “PMOS” (lower right), “level3” (upper right), “W=0.60um L=0.30um”, “Id
vs.Vd”. Push the button “Draw Curve”, the display window displays several curves.

Find the Ids value with Vgs = -2V and |Vds| = 2V and fill it into table 2.
From this part, we can conclude that

if W increases (L, Vds, Vgs are fixed), then |Ids|__________

if L increases (W, Vds, Vgs are fixed), then |Ids|__________
if |Vds| increases (W, L, Vgs are fixed), then |Ids|___________
if |Vgs| increases (W, L, Vds are fixed), then |Ids|____________

TABLE 2. PMOS

W L Vgs Vds Ids

10um 10um -2V 2V
0.6um 10um -2V 2V
10um 0.3um -2V 2V
0.6um 0.3um -2V 2V

Push”OK” to close the simulation window.

3.2 PART II: Layout and Design Rule Checker

Note: If you can finish the layout, please go ahead to PART III and use your layout
to do the simulation and parametric analysis in PART III.
Figure 1 gives a schematic of the gate for the logic function y=/a.(b+c).

Figure 3.2 Schematics of y=[a.(b+c)]’

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According to this schematic please work out your layout.

Begin to draw your layout with Micro wind layout editor.

When you finish the layout, please check your layout:

 Analysis > Design Rule Checker

If your layout is correct, then no messages will appear. If there are some errors, then the
warning messages will appear near the errors. Please modify your layout until no error
messages appear. Save your layout.

3.3 Part III: Simulation and Parametric Analysis (1.5 hours)

If your layout has been finished and no errors are found, then go ahead to step 2. If not,
follow the step1, which will show you how to generate a layout automatically.

Step1:

Using “cut” command, clear everything in the display window. Make sure that nothing
remains in the window. Go to main menu:

 Compile>Compile one line>

A “CMOS Cell Complier” window pops up. Input “y=/ (a. (b+c))”, push “Compile”,
a layout of y=a. (b+c) will appear in the window.

 Analysis>design rule checker

It is to check the layout. It should be correct. If any error appears, please let the assistant
know it. Save the layout.

Step2: Add properties to input signals for simulation

 click on the clock icon and then click the “a” node on the layout.

The clock window appears; make sure the properties on the window are below:

Low level 0.0V High level 2.5V Time low40 Rise time0.5 Time high40 Fall time0.5 ns

 Push “Assign”.

 click on the clock icon and click the “b” node on the layout.

The clock window appears; make sure the properties on the window are below:

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VLSI Design
low level 0.0V High 2.5V Time low 20 Rise time 0.5 Time high 20 Fall time 0.5 ns

 Push “Assign”.

 click on the clock icon and click the “c” node on the layout.
The clock window appears; make sure the properties on the window are below:

low level 0.0V High level 2.5V Time low 10Rise time 0.5 Time high 10Fall time 0.5 ns

 Push “Assign”.

 click on the node visible icon and then click the “y” node on the layout.

The node window appears. Make sure “visible in simulation” is active.

 Push “Assign”.

 Simulate>Simulate Option
An Extraction window pops up. Select” Purge and merge” for “database”, “generate a
SPICE file after extraction” for “Options”.

 Push button “Models, Parameters”

Make sure: “use MOS Model” is “Berkeley Spice level 3” “power Supply” is 2.5V
“Temperature” is 27.0

 Push “Extract” and then push “Quit”.

>Simulate>Start Simulate

A “simulation of example” window pops up. Select “Voltage vs. time”, and step is 2
ps,
time scale is 100ns. Check your simulation results. If you are sure that your simulation
results are correct, then draw the waves in figure 2.

Figure 3.3: Voltage vs. Time

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 Click “Back to Editor” to quit the simulation window.

>Analysis>Parametric Analysis
Click on the output node, and then a window “Start Analysis” pops up. Select “Power
Supply”, the range is from 0.0V to 5.0V, the step is 1.0V. The “measurement” is
“dissipation”, push “Start analysis”; curve (dissipation vs. Vdd supply) appears. Click
“Large” button to zoom in and draw the curve in figure 3.

Figure 3.4: Dissipation vs. power supply (Vdd= 0V to 5.0 V)

Select “Power Supply”, the range is from 0.0V to 5.0V, the step is 1.0V. The
“measurement” is “rise delay”, push “Start analysis”, a curve (rise delay vs. Vdd
supply) appears. Draw the curve in figure 4.

Figure 3.5: Rise Delay & Fall Delay vs. power supply

Select “Power Supply”, the range is from 0.0V to 5.0V, the step is 1.0 V. The
“measurement” is “fall delay”, push “Start analysis”, a curve (fall delay vs. Vdd
supply) appears. Draw the curve in figure 4.

Select “Node capacitance”, the range is from 0 to 100 fF, the step is 20 fF. The
“measurement” is “rise delay”, push “Start analysis”, a curve (rise delay vs. load
capacitance) appears. Draw the curve in figure5.

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VLSI Design

Figure 3.6: Rise Delay & Fall Delay vs. load capacitance

Select “Node capacitance”, the range is from 0 to 100 fF, the step is 20 fF. The
“measurement” is “fall delay”, push “Start analysis”, a curve (fall delay vs. load
capacitance) appears. Draw the curve in figure5.

Please check all of your results in the figures.

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Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

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VLSI Design

Lab-03 Layout

“MOSFET Inverter Characteristics and Layout in Micro wind”

1. Objective

In this lab students will design and implement a CMOS Inverter. Different design
Parameter’s effects like transistor sizing, supply voltages etc well be analyzed and delay,
area, power and currents will be observed. This lab assumed that students are familiar
with MicroWind and Lambda based design rules. The tool used in this lab is MicroWind.
The goals for this Lab are:
• Design of CMOS Inverter and transistor sizing.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of transistor sizing on these
parameters.

2. Theory

2.1 MOSFET

The Metal Oxide Semiconductor Field Effect Transistor is very important part of Digital
Integrated Circuits. It is mostly used as switch in digital design. MOSFET is a four
terminal device. The voltage applied to the gate terminal determine the current flow
between drain and source terminals. The body/substrate of the transistor is the fourth
terminal. Mostly the fourth terminal (body/substrate) of the device is connected to dc
supply that is identical for all devices of the same type (GND fro nMOS and Vdd for
pMOS). Usually this terminal is not shown on the schematics

2.2 nMOS

The nMOS transistor consists of n+ drain and source diffusion regions, which are
embedded in a p-type substrate. The electrons in the channel beneath the gate between
source and drain terminal are responsible for the current flow.

2.3 pMOS

The pMOS transistor consists of p+ drain and source diffusion regions, which are
embedded in an n-type substrate. The holes in the channel beneath the gate between
source and drain terminal are responsible for the current flow.

2.4 CMOS

CMOS Inverter/NOT gate is considered to be the heart of VLSI circuits, based on the
understanding of NOT gate we can extend it easily to NAND and NOR gates which are
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VLSI Design
the basic building blocks of more complex circuits e.g. multipliers and microprocessors.
As per discussion and design on white board in the Lab, a NOT gate can be implemented
using two FETs i.e. a pFET and an nFET both connected in series, in which Vdd is
supplied to pFET and nFET is grounded, input x is applied to the gate terminals of both
and the output is obtained at node y.

3. Design/ Diagram/Circuit

Symbol, Truth Table and CMOS circuit of NOT Gate

Figure 4.1 Inverter Symbol

4. Lab Instructions

a. Open MicroWind and select the foundry cmos025.

b. Save the design as “Save as” as “Lab04”, and save the design frequently during
the lab session.
c. Draw the layout of nMOS using MOS Generator
d. Draw the layout of pMOS using MOS Generator by setting the appropriate width
of pMOS
e. Connect the two transistors using Medal 1as per diagram.
f. Draw the rails of Vdd and Gnd above and below.
g. Connect the n well with Vdd.
h. Add input and output to your design.
i. Save the layout.
j. Apply design rule checker.
k. Simulate the design using run Command.
l. Analyze configuration delay, gate delay, current, power, and midpoint voltage.
m. Repeat the design for different values
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VLSI Design

Figure 4.2 Inverter Symbol in MicroWind

Figure 4.3 Running the Simulation 1

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VLSI Design

Figure 4.4 Running the Simulation 2

Figure 4.5 Running the Simulation 3

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VLSI Design

5. Lab Report

 Give a short description of the content of the Lab

 Include block Diagram of your design in the lab report.
 Include your name in the layout for evaluation purpose
 Include the results in timing waveform in your report.
 Only follow the cover page format.

Simulation Anlysis (Include in your Lab Report)

SR. Width of Drain term Input Propagation Output Current

# nMOS voltage Voltage Delay voltage
Level Level
1 10 2.5v 0 2.5 0
2 0.5v 0 2.5 0
3 1.5v 0 2.5 0
4 5.5v 0 2.5 0
5 2.5v 10p 2.45 1m
6 0.5v 0.4p 0.4 0.026m
7 1.5v 5p 1.4 .41m
8 5.5v 24p 4.46 2.21m
9 50 2.5v 0 2.5 0
10 0.5v 0 2.5 0
11 1.5v 0 2.5 0
12 5.5v 0 2.5 0
13 2.5v 11p 2.45 5.09m
14 0.5v 0.03p 0.4 0.13m
15 1.5v 5p 1.4 2.04m
16 5.5v 24p 5.4 11.09m

You can increase the table and also the entries for in depth analysis.

A properly presented in depth analysis with graph based on the table entries will be
highly appreciated.

Discuss the Effects of width design parameter of the MOS devices on their behavior.
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

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VLSI Design

Lab-05 Layout

“Layout of Basic Gates using 0.25 micron Technology in Microwind”

1. Objective

In this lab students will design and implement the layouts of different CMOS gates,
which includes NAND, NOR. The tool used in this lab is Microwind. The goals for
this Lab are:

 Design of CMOS NAND and NOR Gate.

 Layout Design using the tool.
 Gate delay, area, power and current analysis and the effects of transistor sizing
on these parameters.

2. Theory

2.1 NAND Gate

As per discussion and design on white board in the Lab, a NAND gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in parallel while nFETs are connected in series, Vdd is
supplied to the parallel combination of pFETs while the series combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these series and parallel combinations as
illustrated in NAND circuit under the heading of Design Diagram / Circuit.

2.2 NOR Gate

As per discussion and design on white board in the Lab, A NOR Gate can be
implemented using fours FETS i.e two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in series while nFETs are connected in parallel, Vdd is
supplied to the series combination of pFETs while the parallel combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these parallel and series combinations as
illustrated inNOR circuit under the heading of Design Diagram/Circuit.
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VLSI Design

3. Design Diagram / Circuit

a) Symbol, Truth Table and CMOS circuit of NAND Gate

b) Symbol, Truth Table and CMOS circuit of NOR Gate

Figure 5.1 NOR Gate, Symbols and Truth Table

4. Lab Instructions

1. Open Microwind and select the foundry cmos025

2. Save the design as “Save as” as “Lab05”, and save the design frequently
during the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate
width of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of and ground rails above and below.
7. Connect the nWell to
8. Check the design using DRC for any design rule violation and correct the
design in case of error, again run the DRC and check for errors. Or run the
DRC after each change in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add virtual capacitance at the output
in your design.
11. Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
12. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power,
current, VTC, and area carefully. Make a conclusion of your observations.
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VLSI Design

NAND Gate using Metal 3 for inputs, Metal 2 for Vdd and Gnd, and Metal 1 for
diffusion interconnection and CMOS 0.12 micron process

Figure 5.2 Simulating the NOR gate

5. Lab Report

 Give a short description of the contents of the lab

 Include block diagram/diagrams of your design in the lab report
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VLSI Design
 Describe your layout design approach parameters and explain the effects of each
the parameter
 Include layout of your design also add your name on the design for evaluation
purpose.
 Include the results in timing waveform format in your report. Only follow the
provided cover page format.

6. Simulation Analysis (Include in your Lab Report)

 A properly presented in depth analysis with graph based on the table entries will
be highly appreciated.
 Why the Low to High propagation delay is smaller than High to Low propagation
delay for NAND gate.
 Why the Low to High propagation delay is larger High to Low propagation delay
for NOR gate.
 How for NAND Gate the delay can be made symmetric. Explain, and what will be
its effects on power consumption.
 How for Complex Gate the delay can be made symmetric. Explain, and what will
be its effects on power consumption.
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

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VLSI Design

Lab 06 Layout

“Layout of a Complex gate using 0.25 micron Technology in

MicroWind”

1. Objective

In this lab students will design and implement the layouts of a complex CMOS
gate. The tool used in this lab is MicroWind. The goals for this Lab are:
 Design of CMOS Complex Gate.
 Layout Design using the tool.
 Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters.

2. Theory

2.1 Complex Gate

The expression for the complex gate is given as under

As per discussion and design on white board in the Lab, this complex gate can be
implemented as under

For pFETs Array

Group1: Two pFETs with inputs “c” & “d” at its gate terminals are connected in
parallel.
Group2: A pFET with input “a” at its gate terminal is in series with Group1.
Group3: A pFET with input “b” at its gate terminal is parallel to Group1-Group2.
Group4: Two pFETs with inputs “a” and “d” are in parallel and is connected in
series with Group1-Group2-Group3

For nFETs Array

Group1: Two nFETs with inputs “c” & “d” at its gate terminals are connected in
series.
Group2: An nFET with input “a” at its gate terminal is in parallel with Group1.
Group3: An nFET with input “b” at its gate terminal is in seies to Group1-
Group2.
Group4: Two nFETs with inputs “a” and “d” are in series and is connected in
parallel with Group1-Group2-Group3
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VLSI Design

3. Design Diagram / Circuit

Expression and CMOS circuit of a complex Gate

Figure 6.1 Schematics of

4. Lab Instructions

1. Open MicroWind and select the foundry cmos025

2. Save the design as “Save as” as “Lab04”, and save the design frequently
during the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate
width of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of and ground rails above and below.
7. Connect the nWell to
8. Check the design using DRC for any design rule violation and correct the
design in case of error, again run the DRC and check for errors. Or run the
DRC after each change in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add virtual capacitance at the output
in your design.
11. Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
12. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power,
current, VTC, and area carefully. Make a conclusion of your observations.

5. Lab Report
 Give a short description of the contents of the lab
 Include block diagram/diagrams of your design in the lab report
 Describe your layout design approach parameters and explain the effects of
each the parameter
 Include layout of your design also add your name on the design for evaluation
purpose.
 Include the results in timing waveform format in your report
 Only follow the provided cover page format.

6. Simulation Analysis (Include in your Lab Report)

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VLSI Design
 A properly presented in depth analysis with graph based on the table entries will
be highly appreciated.
 How for the Complex Gate the delay can be made symmetric. Explain and what
will be its effects on the power consumption.
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

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VLSI Design

Lab 08 Layout

“Design and Implementation of Full Adder at Layout Level in

Microwind”

1. Objective

In this lab students will design and implement the layout of a CMOS Full Adder.
Delay, area, power and currents of Full Adder will be observed. This lab assumed
that students are familiar with Microwind and Lambda based design rules. The
tool used in this lab is Microwind. The goals for this Lab are:
 Design of CMOS Full Adder Layout.
 Layout Design using the tool.
 Gate delay, area, power and current analysis

2. Theory

CMOS Full Adder

A Full Adder is an important building bock of arithmetic circuits in a system. Full

adder accepts three inputs and produces the outputs sum and carry by adding the
binary bits with the help of logic gates. The Full Adder can be optimized using
XOR and NAND Gates only in the following way.

3. Design Diagram / Circuit

Figure 8.1: Full Adder Gate Level Diagram

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VLSI Design
Schematic and Layout of the NAND Gate has been done in one or more of the
previous labs. There are many ways to construct the XOR schematic e.g. using
expression, using Transmission gate. We will construct the schematic in the following
way. From the table of XOR Gate.

Table 6.1: Truth Table for XOR

The XOR can be read from the Table as follows: IF B=0, OUT=A, IF B=1, OUT=Inv
(A). The principle of the circuit presented below is to enable the A signal to flow to
node W1 if B=1 and to enable Inv (A) the signal to flow to node W1 if B=0. The
output inverts the node W1 so that we can get the XOR operator.

Figure: Schematic of XOR Gate

Figure 8.2: Schematic of XOR Gate
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VLSI Design

Figure 8.3 : Layout of XOR Gate

4. Lab Instructions

1. Open Microwind and select the foundry cmos025

2. Save the design as “Save as” as “Lab05”, and save the design frequently
during the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate
width of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of and ground rails above and below.
7. Connect the nWell to
8. Check the design using DRC for any design rule violation and correct the
design in case of error, again run the DRC and check for errors. Or run the
DRC after each change in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add virtual capacitance at the output
in your design.
11. Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
12. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power,
current, VTC, and area carefully. Make a conclusion of your observations.
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VLSI Design

Figure 8.4: Simulating Full Adder

5. Lab Report
 Give a short description of the contents of the lab
 Include block diagram/diagrams of your design in the lab report
 Describe your layout design approach parameters and explain
the effects of each the parameter
 Include layout of your design also add your name on the design
for evaluation purpose.
 Include the results in timing waveform format in your report
 Only follow the provided cover page format.
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

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VLSI Design

Lab-09 Layout

“Design and Implementation of Static RAM Cell Layout using CMOS 0.12
micron Technology in Microwind”

1. Objective

In this lab students will design and implement the layout of a six-transistor static memory
cell.
The technology for this lab is cmos012 micron process. The tool used in this lab is
Microwind.
The goals for this Lab are:
 Design of Static RAM Cell schematic.
 Design of Static RAM Cell Layout using the tool.
 Gate delay, area, power and current analysis.

2. Theory (Static RAM Cell)

The basic cell for static memory design is based on 6 transistors, with two pass gates
instead of one. The circuit consists of two cross coupled inverters, but uses two pass
transistors instead of one. The cell has been designed to be duplicated in X and Y in order
to create a large arrays of cells. Usual sizes of Megabit SRAM memories are 256
columns x 256 rows or higher. The selection lines WL concern all the cells of one row.
The bit lines BL and ~BL concerns all the cells of one column.

3. Design/ Diagram/Circuit

Word Line (WL)

Bit Line (BL) ~Bit Line (~BL)
Figure 9.1 : Static Memory Cell
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VLSI Design

4. Lab Instructions

4.1. Manual Layout of Static memory Cell

1. Open Microwind and select the foundry cmos012.

2. Save the design as “Save as” as “Lab08”, and save the design frequently during
the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate width
of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of and ground horizontal rails with Metal 3.
7. Draw the layout of signals BL and ~BL using Metal 2.
8. Connect the nWell to
9. Check the design using DRC for any design rule violation and correct the design
in case of error, again run the DRC and check for errors. Or run the DRC after
each change in the layout.
10. Check for Electrical connections to be valid.
11. Add inputs and outputs to the design; also add virtual capacitance at the output in
your design.
12. Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
13. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power,
current, TC, and area carefully. Make a conclusion of your observations.

Figure 9.2: Layout of Static Memory Cell

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VLSI Design

Figure 9.3: Write Cycle of Static Memory Cell

Figure 9.4: Layout of 4x4 Array of Static RAM Cells

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VLSI Design

5. Lab Report

 Give a short description of the contents of the lab

 Include block diagram/diagrams of your design in the lab report
 Describe your layout design approach parameters and explain the effects of
each the parameter
 Include layout of your design also add your name on the design for evaluation
purpose.
 Include the results in timing waveform format in your report
 Only follow the provided cover page format.
 You can implement using any other optimized method.
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

34
VLSI Design

Lab-10 Layout

“Design and Implementation of Look Up Table (LUT) Layout using CMOS

0.25 micron Technology in Microwind”

1. Objective

In this lab students will design and implement the layout of 4 bit 2-input Look UP Table
(LUT).
The technology for this lab is cmos025 micron process. The tool used in this lab is
Microwind.
The goals for this Lab are:
 Design of Static D Register schematic.
 Design of Static D Register Layout using the tool.
 Design of 4-to-1 Multiplexer using Pass Transistor Logic
 Gate delay, area, power and current analysis.

2. Theory (Static RAM Cell)

Look-up Tables are almost invariably used in FPGAs to produce combinational

functions. A look-up table is composed of permanent memory (RAM) connected to a
multiplexer. All possible outputs of the desired function are stored in the ram cells. The
inputs of combinational function are the inputs of multiple
For this, students will design a 2-input look-up table. For that we will need 4 D-Registers
and one 4-1 multiplexer with 02 select inputs.
A 4-1Multiplexer can be constructed using pass transistor logic as shown in the Diagram
section.

3. Design/ Diagram/Circuit

4. Lab Instructions

 Open Microwind and select the foundry cmos012.

 Save the design as “Save as” as “Lab09”, and save the design frequently during
the lab session.
 Draw the layout of nMOS using MOS Generator
 Draw the layout of pMOS using MOS Generator by setting the appropriate width
of pMOS
 You are free to choose automated or manual method for your latch design.
 For your convenience schematics and Layout of D-latch and MUX are already
copied in your Labs folder. You are free to use them. But they are not optimized
and may not give the best results. So you are strongly advised to design your own
optimized layout.
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VLSI Design
 Connect the transistors using Metal 1 as per design.
 Draw the rails of and ground horizontal rails with Metal 3
 Connect the nWell to
 Check the design using DRC for any design rule violation and correct the design
in case of error, again run the DRC and check for errors. Or run the DRC after
each change in the layout.
 Check for Electrical connections to be valid.
 Add inputs and outputs to the design; also add virtual capacitance at the output in
your design.
 Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
 First stage of simulation will be configuration where you will give a positive
pulse to the clock of your RAM cells and load them with four possible
combinations of output.
 Second stage will be simulation of you configured XOR function where you will
give different combinations to sel inputs and observe the output.

Figure 10.1: Layout of 4-bit 2-Input Look UP Table (LUT)

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VLSI Design

Figure 10.2: Simulation of 4-bit 2-Input Look UP Table (LUT)

5. Lab Report

 Give a short description of the contents of the lab

 Include block diagram/diagrams of your design in the lab report
 Describe your layout design approach parameters and explain the effects of
each the parameter
 Include layout of your design also add your name on the design for evaluation
purpose.
 Include the results in timing waveform format in your report
 Only follow the provided cover page format.
 You can implement using any other optimized method.
 How much RAM and what kind of MUX will you need to construct an LUT
that has 05-inputs
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VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

38
VLSI Design

Lab-11

“Chip Design”
1. Objectives

This lab consists of designing a complete chip with a buffered 8-bit barrel shifter on
layout level (Lab4) and I/O pads. I/O pad ring consists of 32 pads which are 16 input
pads, 8 output pads, 4 VDD pads and 4 VSS pads, respectively. Each basic bonding pad
size is 100 x 100 m2.

Note: This lab is VERY time consuming and the only way to be able to finish the lab
in time is to prepare the homework tasks carefully.

2. Pre-study and preparation

You must carefully read Appendix to know how the chip can be generated. Meanwhile
you must finish the lab3 since the lab4 is based on the lab3. If you have not finished the
lab3, don’t do this lab4 first.

3. MicroWind manual

Study the MicroWind manual thoroughly, so that you are very familiar with the features
of the programme.

4. Lab instructions

Select the cmos0.25 foundry.

4.1 ESD pad protections

Electrostatic discharge (ESD) exists in input and output pads. In order to protect the chip,
ESD protections are required. One of the most simple ESD protection is made up of a set
of two diodes and a resistance (Appendix Fig.5). One diode handles the negative voltage
Vss flowing inside the circuit (N+/Psubstrate), the other diode (P+/N well) handles the
positive voltage Vdd. The layout of ESD protection pad with the N+/P substrate diode
and P+/N well) diode is shown in Fig1.
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VLSI Design

Figure 11.1.Create a diode for I/O pad protections

One simple way to add a diode in the layout is to click on the cell library icon, then click
on the Contacts menu and to assert the options: <Diff P + Metal1> and <Diff N+ on
Nwell>. This creates a P+/ Nwell diode with its appropriate contacts (Fig. 2). To select
<Diff N+ to Metal1> and <Diff P+ on Psubstrate> generate N+/P substrate diode.

Figure 11.2: Layout Generator.

Note that to change Rows and Columns with any more than 1 numbers can enlarge the
diode size. Save your design as ESDprotections.msk in your directory.

4.2 Design the I/O pad ring

To generate the pad ring: Edit -> Generate -> I/O Pads.
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VLSI Design
A windows similar to Fig. 3 pops up. The <Pad ring> option should be selected. The
values <Pads in X: 8>, <Pads in Y: 8>, <Ring Width: 15 µm> and <Vdd, Vss pairs: 4>
should be filled in.

Figure 11.3: Generate Pads Window

A pad ring similar (not exactly the same) to Fig. 4 in the lab instruction is generated.You
can now inspect the generated pad ring. It has four pairs of Vdd-Vss pads,correctly
connected. Make sure that the supply voltage is correct, 2.5 V. You can also see that the
ESD protection circuits already exist in the generated pad ring.

Figure 11.4: Overview of Chip

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VLSI Design
The pads and the inner ring (Vdd) have all six metal layers. We only need two in this lab.
Extra metal layers require more masks, resulting in a higher cost. Therefore, we remove
the unnecessary metal layers.

1. From Edit -> Protect all.

2. Select M 6, M 5, M 4 and M 3 on the Palette, and remove all these layers in the
layout (pads and pad ring).

3. Select M 2 on the Palette and remove the Metal 2 on the left side of the inner ring.

4. After removing the metal layers, make sure that the power supply pads are still
correctly connected, the 4 Vdd pads should be connected to the inner ring and the

4 Vss pads to the outer.

5. Just as in the lab instruction, besides that the power supply pads are now already
properly connected. You only need to distribute the pads to the signals (A0-A7, Sh0-Sh7
and the outputs s0-s7).

4.3 Assembling the chip

1. Open lab4.msk from File.

2. Click File -> Insert ->open your ESDprotections.msk file. It appears on the right corner
of the pad ring window. Put it in each I/O pad. The connection way can be referred Fig.1.

3. Click File -> Insert ->open your lab3 msk file. The barrel shifter is on the right corner
of the pad ring window. Moving it into the centre of the pad ring.

4. Connecting all I/O,Vdd and Vss of lab 3 cell to the relative pads with Metal 1 and
Metal 2. Please refer to Path between Pads and Cells in appendix. The Width Metal can
be filled in any more than 10 lamda in order to visible on the whole chip.
Note that the work need you careful and patient. It consumes lots of time.

Hint: repeating using <Zoom in>, <all> to enlarge the part of chip.

Steps for connection between Pads and Cells.

1. Click the stretch icon;

2. Stretch some path edge with mouse;

3. Hold down one of arrow keys or move Mouse to needed direction;

4. put the VIA to make M1/M2 contacted as need two metal wires;
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VLSI Design
5. Check node if identified between pads and cells;

6. Do Design Rule Check. If errors, correct them;

7. If right, save your design;

4.4 I/O stimuli

 Name Pad the same with Lab4.

 Name the inputs to the barrel shifter A7 through A0 in the order displayed in
figure 4. Use the Visible node in the palette for this and select the properties to
Vdd or Vss so that You set a clever selection of fixed input values to enable Your
investigation on how the output is depending on the control signals.

 Name the control inputs to the barrel shifter Sh0 through Sh7 in the order
displayed in figure 6. Use the Visible node in the palette for this and select the
property to pulse in order to apply interesting control signals. Let one and only
one control signal be high at each instant. The pulse should have a rise and fall
time of 0.5ns. The pulse width should stay high for at least 2ns

 Name Your buffer outputs s7 through s0 in such manner that the index
corresponds to that of the barrel shifters input signals. Use the Visible node in the
palette for this and select the property to variable. Apply Vdd and Vss voltages to
the buffer, using Vdd supply and Ground from the palette.

5. Simulate

5.1 Simulate functionality

Check that Your design is working properly.

Study maximum time delay.

Maximum time delay: ____________________

Check the average wire length, by doing:

File -> Statistics -> Interconnects.

Average length: _______________________

Check the capacitance on the following nodes:

A7: ______ F
A6: ______ F
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VLSI Design
A5: ______ F
A4: ______ F
A3: ______ F
A2: ______ F
A1: ______ F
A0: ______ F

Also check the capacitance, on the barrel shifters output before the buffer:

B7: ______ F
B6: ______ F
B5: ______ F
B4: ______ F
B3: ______ F
B2: ______ F
B1: ______ F
B0: ______ F

6. Discussion

Explain the difference between Lab4 and Lab5.

________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Explain the simulation You have carried out.

________________________________________________________________________
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Motivate Your time delay result.

________________________________________________________________________
________________________________________________________________________

Motivate why the obtained capacitance values on A7 through A0 are not equal.
________________________________________________________________________
________________________________________________________________________
________________________________________________________________________

Explain the obtained results regarding the capacitance values on B7 through B0.
________________________________________________________________________
________________________________________________________________________
You can now call an assistant and demonstrate results and discuss Your conclusions.
44
VLSI Design

Evaluation

Total Marks Obtained Marks

Lab Performance 15

Knowledge about the Lab 15

Values obtained (Accurate/Precise) 10

Lab participation 5

Behavior in the Lab 5

Total 50

Comments from the Instructor

Date Instructor’s Signature

45
VLSI Design

Appendix
ESD Protections

The input pad includes some voltage boosting and under voltage protections linked with
problems of electrostatic discharge (ESD). Such protections are required as the oxide of
the gate connected to the input could be destroyed by over voltage. One of the most
simple ESD protection is made up of a set of two diodes and a resistance (Fig. 5). One
diode handles the negative voltage flowing inside the circuit (N+/P substrate), the other
diode (P+/N well) handles the positive voltage. An example of ESD in a real case circuit
is shown in Fig. 6.

Figure 001: Diodes for electrostatic discharge protection

Figure 002: Supply network in a real case circuit