Introduction to Micro/Nano Electronics

David B. Janes
School of Electrical and Computer Engineering,
Birck Nanotechnology Center and Institute for Nanoelectronics and Computing
Purdue University, W. Lafayette, IN 47907
[email protected]
INAC
• A Brief Overview of Microelectronics

• Semiconductor Band Diagrams

• Basic Semiconductor Devices

• Introduction to Circuits

• Toward “Nanoelectronics”
 Enabling Technology: Microfabrication

1969: IBM System 360

Driving Technology:
Integrated Circuits
(“microchips”)

1981: IBM PC

2005: Mobile, Wireless

Photos from: Newcastle University Computing Service, IBM Archives, Dell/Palm/Motorola

Silicon Boule and Processed Wafers
 What’s a Nanometer?
Dimension
Human
1m 5 billion humans
Mouse 10 cm (close-packed)
1000 X
Fly 1 cm
2 m tall, each
Gnat 1 mm gets 1m x 1m
100 µm
70 km (45 miles)
1000 X
10 µm

Bacteria 1 µm 5 billion “nanos”

(close-packed)
100 nm
1000 X
10 nm 2 nm tall, each
(10-9 m) 1 nm gets 1nm x 1nm

0.1nm 0.07 mm (0.003”)

 Microns to Nanometers
100 µm
Dimension

Plant,
10 µm
Animal Cell

Bacteria
1 µm

100 nm
Virus

Protein 10 nm

DNA “turn”
Simple
1 nm Molecules
DNA base
Atoms
0.1nm
 Nanotechnology:
A Convergence of Enabling Technologies

Dimension (nm) Microelectronics

100 µm

10 µm “Top-Down”
Biological Cell
Device Dimension in CMOS
1 µm Optical Microscopy
“Bottom-Up” Gate Length in CMOS
100 nm

10 nm
Nanoclusters
Oxide Thickness in CMOS
Simple Molecules 1 nm Imaging/Manipulation
Electron Microscopy of Structures
Atoms 0.1nm Scanning Probes
VS (x, y)

Chemical/Biological Voltage Control

Synthesis
• A Brief Overview of Microelectronics

• Semiconductor Band Diagrams

• Basic Semiconductor Devices

• Introduction to Circuits

• Toward “Nanoelectronics”
 Semiconductor and Molecular States

EVAC EVAC

LUMO
E E

EC
EF Eg ~ 4 - 6 eV
Eg ~ 0.2 - 2.5 eV

EV EF
HOMO

Semiconductor Molecule
 N atoms/cm3
Total number of bonding electrons in crystal = 4N
(~ 1e23/cm3)
Conduction Band:
Mostly empty of 4N States
electrons
Count electrons EC
Density of electrons: n EG
Charge/electron: -q
EV

4N States
Valence Band: Mostly
filled with electrons – Semiconductor
Count empty states
(holes)
Density of holes: p
Charge/hole: +q
 Semiconductor Bands – Doping Dependence

EVAC

EVAC

E EC
Eg ~ 0.2 - 2.5 eV
EC
EF
EF EV
Eg ~ 0.2 - 2.5 eV

EV

N-type Semiconductor P-type Semiconductor

Fermi Level position can be changed by addition of dopants

(donors and acceptors)
States are extended states – electrons and holes can move freely
 Semiconductor Bands – Doping Dependence

EVAC

EVAC

EC
e- in C.B.
EC
EC
EF
Donor Levels EF EV Acceptor Levels

EV EV
h+ in V.B.
N-type Semiconductor P-type Semiconductor

Fermi Level position can be changed by addition of dopants

(donors and acceptors)
States are extended states – electrons and holes can move freely
 Energy Bands for Metals and Semiconductors

EVAC EVAC
χ
E qΦM

EC
EF EF

EV

Metal N-type
Semiconductor

Recall: Electrostatic Potential: qV = - EVAC

 Redox Processes in a Molecule
e-
LUMO LUMO

E E

Eg ~ 4 - 6 eV Eg ~ 4 - 6 eV

e- EF EF
HOMO HOMO

Molecule Molecule

Oxidation: give up an electron Reduction: accept an electron

(M0 => M+ + 1e- ) (M0 + e- => M- )
 Conduction Process in a Semiconductor Device
EVAC EVAC
-q VAppl

electrons electrons
EC Contact EC
EF Contact
EF

EV EV

Diffusion – motion due to Drift – motion in an electric

concentration gradient field
JN Diff JN Drift
• A Brief Overview of Microelectronics

• Semiconductor Band Diagrams

• Basic Semiconductor Devices

• Introduction to Circuits

• Toward “Nanoelectronics”
 PN Junctions
P-Type Semiconductor N-Type Semiconductor

p ~ NA n ~ ND
EC EC
EF

EG EG

EF
EV EV

pn Junction
EC

pp ~ NA qVbi
EG
EC
EF
EF
EV
EG nn ~ ND

EV
EE455 Spring 2000 Lecture 2
 PN Junction Electrostatics
pn Junction
EC

pp ~ NA qVbi
EG
EC
EF
EF
EV
EG nn ~ ND

EV

W (depletion width)

---- ++++
---- ++++
---- ++++
ρ = -q NA ρ = +q ND

Electric Field

EE455 Spring 2000 Lecture 2

 PN Junction Reverse Bias
EC

EG
pp ~ NA +
q(Vbi - VD)
EF VD < 0
EC
EF
EV EG nn ~ ND -

PN Junction W (depletion width) EV

Forward Bias
EC

pp ~ NA EC q(Vbi - VD)
EG +
EF
EF
VD > 0
EV EG
nn ~ ND -
EV
W (depletion width)
EE455 Spring 2000 Lecture 2
Diode Current ID
ID = IS (e q VD/ nkT -1)
q = electronic charge (1.6 x 10-19 C)
VD
n == ideality factor
k = Boltzmann’s constant = 8.62e-5 eV/K
T = temperature (K)
kT/q = 0.026 eV at room temperature

Reverse Junction Capacitance (Cj)

Cj = εSi A/Wdepl
εSi = Ksi ε0 = 11.8 x 8.854 x 10-14 f/cm
Wdepl = (2 εSi (Vbi - VD)/q (1/NA +1/ND) )1/2
Vbi = built-in potential = kT/q ln(NA ND/ni2)
EE455 Spring 2000 Lecture 2
The basic building block of microelectronics:
The transistor switch
 An Idealized Switch

Ideal: Open Circuit (I=0)

when open

Controlled by
Gate Voltage

Also need gain.

 An Idealized Switch

Ideal: Open Circuit (I=0)

when open

Controlled by
Gate Voltage
Ideal: Open Circuit (I=0) when Vgate
< Threshold Voltage

A controlled
VGATE current source When “on”: current increases with
gate voltage
Gain: small input level induces large
output response
MOSFET: small input current, large
output current (comparable voltages)
 MOS Transistor

NMOS Structure VG (> 0 in Active)

Gate ID
VS (= 0) VD (> 0)
D
Source Gate Oxide Drain

n++ n++ G
p- substrate
S
 NMOS Transistor -- Small VDS
Accumulation
VG (<< VT )
VS (= 0) Gate
VD (> 0)
Source Gate Oxide Drain ID
+++++++++++++++
n++ n++
p- substrate

Inversion
VG ( > VT ) VDS
VS (= 0) Gate
VD (> 0)
Source Drain ID
Gate Oxide
--------------------
n++ n++
p- substrate

VDS
EE 455 Spring 2000 Lecture 3
 NMOS Transistor -- VDS comparable to (VGS - VT)

VG ( > VT ) 0 < VD < (VGS - VT)

VS (= 0) Gate
ID
Source Gate Oxide Drain
-------------------
n++ n++
p- substrate

VDS
VG ( > VT ) VD = (VGS - VT)
VS (= 0) Gate
ID
Source Gate Oxide Drain
----------------
n++ n++
p- substrate

VDS
EE 455 Spring 2000 Lecture 3
 MOS Transistor – I-V Characteristics

ID
Triode ID = µn Cox/2 W/L (VGS - VTN)2
Region

Active Region

ID = µn CoxW/L [(VGS - VTN)VDS -VDS2 /2 ] VDS

 MOS Transistor -- Subthreshold Region

Subthreshold Region: (VGS - VTN) < 0 V

ID = ID0W/L exp(q VGS /n k T)

log ION log ID

n = (COX + Cdepl) / COX ≅ 1.5

Ideal: ~ 60
mV/decade

log IOFF

VT VGS
Need high ON/OFF ratio (~ 1 e6)
 MOS Transistor -- Short Channel Effects

Velocity Saturation:

Hot Carrier Effects:

Impact Ionization, Tunneling into Gate Oxide, Punch-Through
from Source to Drain:

Drain-Induced Barrier Lowering (DIBL):

VS (= 0) VG ( > VT ) Gate

Source Drain
Gate Oxide
----------------
n++ n++
p- substrate

EE 455 Spring 2000 Lecture 7

 CMOS = NMOS + PMOS
NMOS Structure VG (> 0 in Active)
Gate ID
VS (= 0) VD (> 0)
D
Source Gate Oxide Drain

n++ n++ G
p- substrate
S
“on” at positive gate voltages

PMOS Structure VG (< 0 in Active)

Gate
VS (= 0) VD (< 0) ID
Source Gate Oxide Drain D
p++ p++
n- substrate G
S
“on” at negative gate voltages
 MOS Transistor -- Subthreshold Region -
- PMOS

Subthreshold Region: (VGS - VTN) < 0 V

ID = ID0W/L exp(q VGS /n k T) log ID

n = (COX + Cdepl) / COX ≅ 1.5

Ideal: ~ 60
mV/decade

VGS VT
 Device Relevance of Metal-Semiconductor
Interfaces

1. Ohmic Contacts
Example: S/D contacts in MOSFET:

Good contacts: specific contact

VS (= 0) VG ( > VT ) G
resistance < 1x10-7 Ω cm2
S D
Gate Oxide
---------  Low barrier height, heavy
n++ n++ doping (tunneling or thermionic
p- substrate field emission).

Also relevant to most other semiconductor devices,

including optoelectronic devices.
 Device Relevance of Metal-Semiconductor
Interfaces

2. Schottky Barriers
Example: gate region in MESFET:

Gate in metal-semiconductor FET

(MESFET):
Good Schottky barrier for gate

VS (= 0) VG ( > VT )
G  Gate modulates depletion
S D width, open channel region
n++ n++
 Moderate barrier height,
moderate doping (small gate
n- channel
current).

Also relevant to Schottky diodes (used as high

frequency rectifiers).
• A Brief Overview of Microelectronics

• Semiconductor Band Diagrams

• Basic Semiconductor Devices

• Introduction to Circuits

• Toward “Nanoelectronics”
Silicon Wafer after Processing
 A Simple CMOS Circuit (Inverter)

VOUT
VDD

I ~ IOFF
S
PMOS NMOS “on”,
PMOS “off”
D

D V
G OUT PMOS “on”,
NMOS “off”
S NMOS
VIN I ~ IOFF

VIN
 Typical Cascade of Stages

VDD VDD

S S
PMOS PMOS
D D

D V D V
G OUT G OUT

S S
VIN NMOS NMOS

First Stage drives 2nd Stage (and so on)

Each stage must be able to drive a replica of itself
(or larger gate)
 Operating Speed and Power Dissipation

During switching transient from high to low:

Transition speed ~ ION – this sets operating
NMOS CG2
frequency ION
Dissipate power during switching
(dynamic)
VDD VDD

S S
PMOS PMOS
D D Therefore, want large ION for
high operating frequency
D V D V
G OUT G OUT (example: 3 GHz Pentium IV)
S S
VIN NMOS NMOS
 Static Power Dissipation

During times when circuit is not switching: VDD

Have leakage current IOFF

– power dissipation ~ IOFF VDD
This is static power, and is wasted
VDD NMOS IOFF

S
PMOS
D Therefore, want small IOFF for low power
dissipation
D V
G OUT Need very small power/device, since have
S ~ 100 million devices/chip
VIN NMOS
(example: ~100 Watts in Pentium IV)
 A Basic CMOS Logic Gate (AND)

VOUT
VDD

I ~ IOFF
PMOS S S
B Both “A” and “B”
A “high”
D D

D V
G OUT A or B “low”
A
S NMOS
I ~ IOFF
D
B G
S VIN
 A Basic CMOS Memory Cell (DRAM)

Enable Line
G A single bit (“0” or “1”) stored as
electronic charge on capacitor
High “1” D S
or Low “0”
Voltage Storage Transistor acts as switch –
Capacitor charges switch if enabled (gate)
and a high voltage applied to D

Readout is by sensing whether

capacitor is charged (generally
by trying to write another bit, and
monitoring the current)

Volatile – charge eventually leaks

out and must be refreshed
 A Basic CMOS Memory Cell (DRAM)
Large memory arrays (Gigabits) arranged in word and bit-line arrays

Word Line
G G

D S D S

CSTORE CSTORE

Bit Line

G G

D S D S

CSTORE CSTORE
 Ideal Metal - Semiconductor Junction
M-S Structure (Schottky)

Depletion Region
EVAC
(~ 5 - 1000 nm)

“Bulk”

Energy

EC
χ
qΦB

EF

Depth
N-Type
Metal
Semiconductor

Ideal M-S Junction: qΦB = qΦM - χ - (EC - EF)BULK

• A Brief Overview of Microelectronics

• Semiconductor Band Diagrams

• Basic Semiconductor Devices

• Introduction to Circuits

• Toward “Nanoelectronics”
 Microelectronic Device/Interconnect
Structures
Cross-Sectional View: Top View:

Si Substrate

Lithography, etching, implant

NMOS device PMOS device

6-Transistor SRAM Cell
Chiseling: Use lithography, etching,
etc. to define devices, interconnects
Yields well optimized device
structures, nearly arbitrary interconnect
configurations
 Trends in Miniaturization of ICs
Moore’s Law
# of Neurons in the

# of Transistors/ DRAM Chip

Human Brain
p
in 15cm3 Chi
R AM
10000 /D 1.E+12
Minimum Feature (nm)

Mi rs
n
Dim imu sisto 1.E+11
en m a n
sio DRA f Tr 1.E+10
n( o
1000 nm M # 1.E+09
) Time
16Mb 256 1.E+08
Mb 1.E+07
1Mb
100 1.E+06 2-3 years per
64Kb
1.E+05 generation
4Kb
1.E+04
10 1.E+03
1970 1980 1990 2000 2010 2020
Year
 “Conventional” Micro to Nano- electronics
Intel: August 2002
10
silicide

1.2nm
0.1 SiO2

Strained Si
0.01
1970 1980 1990 2000 2010 2020

www.intel.com/research/silicon/90nm_press_briefing-technical.htm
Interconnect
Technology Node: pitch/2
Lines
Pitch
 Nanoelectronics

Voltage
L
Voltage
Reed, Yale
Dai, Stanford and McEuen, Cornell

Purdue,
Hersam, Northwestern
Northwestern
Cost of Fabrication Facility for ICs
Moore’s 2nd Law

$100 B
Cost of Fab Facility ($)

2001:
$ 10 B
$5
billion

$1 B

$100 M
1970 1980 1990 2000 2010 2020
Year
 Fundamental Limits of Microelectronics
• Quantum mechanics
• Speed of light
• Material limitations
• atomic scale manufacturing
• Cost of a Silicon Fab: 100nm
1967: $ 2M
1997: $ 3B
2010: $10B

Individual
Atoms
From M. Lundstrom
 Acknowledgements
• Funding: NASA, NSF, ARO for funding

INAC
The NASA Institute for Nanoelectronics and Computing

• Thank you to Prof. Jerry Woodall, Dr. Saurabh

Lodha, Dr. Steven Howell and Prof. Supriyo
Datta for helpful discussions