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Assignment 2

1. The document describes a lab assignment to design a 16x9 multiplier using different modeling styles in Verilog. 2. It involves generating partial products, reducing partial products using carry save adders, and final addition using a carry propagate adder. 3. The multiplier is designed using behavioral modeling and mixed modeling, and the results are compared to ensure both methods yield the same outputs.

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lavish
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897 views

Assignment 2

1. The document describes a lab assignment to design a 16x9 multiplier using different modeling styles in Verilog. 2. It involves generating partial products, reducing partial products using carry save adders, and final addition using a carry propagate adder. 3. The multiplier is designed using behavioral modeling and mixed modeling, and the results are compared to ensure both methods yield the same outputs.

Uploaded by

lavish
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Architecture- MEL G642

Lab Assignment 2
Lavish Patidar
2019H1230528G

A 16x9 multiplier uses three component:


 Partial Product Generator (9 partial products to be generated)
 Partial Product Reduction using CSA (Carry Save Adder)
 Final Sum and Carry Generation using CPA (Carry Propagate Array)
1. Draw the architecture of the multiplier
2. Design the above specified 16x9 multiplier using Behavioural Modelling.
3. Design the above specified 16x9 multiplier using Mixed Style of Modelling
where individual component (Partial Product Generator, Partial Product
Reduction block and Final Sum and Carry Generation block) is designed using
behavioural modelling. However to make a 16x9 multiplier these block are
then interconnected using Structural Modelling.
4. Compare results of both these codes (Both code should give same output).
1. Architecture of Multiplier
2. Design of Multiplier using behavioural modelling:
2.1 Verilog Code for Multiplier:
`timescale 1ns / 1ps

module Multiplier_Behav (X,Y,Out);


input [15:0] X;
input [8:0] Y;
output reg [24:0] Out;
always @*

begin
Out=X*Y;
end
endmodule

2.2 Testbench for the Multiplier:


`timescale 1ns / 1ps
module testbench_behav;
reg [15:0] X;
reg [8:0] Y;
wire [24:0] Out;

Multiplier_Behav Mul_Behav (X,Y,Out);


initial
begin
X=16'b1010101010101010;

Y=9'b101101001;
#20
X=16'b1010010101010011;
Y=9'b101011010;
#20
X=16'd256;
Y=9'd84;
#20
X=16'd24618;

Y=9'd586;
#20 $finish;
end
endmodule

2.3 Simulation Result:


3. Design of Multiplier using Mixed modelling:
3.1 Verilog Code for Mix Modelling:
`timescale 1ns / 1ps

module multiplier(M,N,Result);
input [15:0] M;
input [8:0] N;
output [24:0] Result;
wire [15:0] PP0,PP1,PP2,PP3,PP4,PP5,PP6,PP7,PP8;

wire [24:0] S0,C0;


PPGeneration PPG (M,N,PP0,PP1,PP2,PP3,PP4,PP5,PP6,PP7,PP8);
PPReduction PPR (PP0,PP1,PP2,PP3,PP4,PP5,PP6,PP7,PP8,S0,C0);
CarryPAdder CPA (S0,C0,Result);
endmodule

module PPGeneration (A,B,P0,P1,P2,P3,P4,P5,P6,P7,P8);


input [15:0] A;
input [8:0] B;
output reg [15:0] P0,P1,P2,P3,P4,P5,P6,P7,P8;

always @*
begin
P0= A & {16{B[0]}};
P1= A & {16{B[1]}};
P2= A & {16{B[2]}};

P3= A & {16{B[3]}};


P4= A & {16{B[4]}};
P5= A & {16{B[5]}};
P6= A & {16{B[6]}};
P7= A & {16{B[7]}};
P8= A & {16{B[8]}};
end
endmodule

module PPReduction(
input [15:0] X0,
input [15:0] X1,
input [15:0] X2,
input [15:0] X3,

input [15:0] X4,


input [15:0] X5,
input [15:0] X6,
input [15:0] X7,
input [15:0] X8,

output [24:0] S,
output [24:0] C
);
reg [24:0]
pp0=25'd0,pp1=25'd0,pp2=25'd0,pp3=25'd0,pp4=25'd0,pp5=25'd0,pp6=25'd0,pp7=25'd
0,pp8=25'd0;
wire [24:0] S1,S2,S3,S4,S5,S6;
wire [24:0] C1,C2,C3,C4,C5,C6;

assign C1[0]=0,C2[0]=0,C3[0]=0,C4[0]=0,C5[0]=0,C6[0]=0,C[0]=0;
always @*
begin
pp0=X0;
pp1=X1<<1;

pp2=X2<<2;
pp3=X3<<3;
pp4=X4<<4;
pp5=X5<<5;
pp6=X6<<6;
pp7=X7<<7;
pp8=X8<<8;

end

genvar i;
generate
for (i=0;i<25;i=i+1)

begin: adder_inst
full_adder F1 (pp0[i],pp1[i],pp2[i],S1[i],C1[i+1]);
full_adder F2 (pp3[i],pp4[i],pp5[i],S2[i],C2[i+1]);
full_adder F3 (pp6[i],pp7[i],pp8[i],S3[i],C3[i+1]);
end

endgenerate

genvar j;
generate

for (j=0;j<25;j=j+1)
begin: adder_inst2
full_adder F4 (S1[j],C1[j],S2[j],S4[j],C4[j+1]);
full_adder F5 (C2[j],S3[j],C3[j],S5[j],C5[j+1]);
end

endgenerate

genvar k;
generate
for (k=0;k<25;k=k+1)
begin: adder_inst3
full_adder F6 (S4[k],C4[k],S5[k],S6[k],C6[k+1]);
end
endgenerate

genvar l;
generate
for (l=0;l<25;l=l+1)
begin: adder_inst4

full_adder F7 (S6[l],C6[l],C5[l],S[l],C[l+1]);
end
endgenerate
endmodule

module CarryPAdder (X,Y,Out);


input [24:0] X,Y;
output [24:0] Out;
wire [24:0] a;
assign a[0]=0;

genvar i;
generate
for (i=0;i<25;i=i+1)
begin:CPA

full_adder F1 (X[i],Y[i],a[i],Out[i],a[i+1]);
end
endgenerate
endmodule
module full_adder (A,B,C,Sum,Carry);
input A,B,C;
output reg Sum,Carry;

always @ (A,B,C)
begin
Sum=A ^ B ^ C;
Carry= (A&B) | (B&C) | (C&A);
end

endmodule

3.2 Testbench for the Multiplier:


`timescale 1ns / 1ps
module testbench;

reg [15:0] M;
reg [8:0]N;
wire [24:0] Result;
multiplier Mul_Mix (M,N,Result);
initial

begin
M=16'b1010101010101010;
N=9'b101101001;
#20 M=16'b1010010101010011; N=9'b101011010;
#20 M=16'd256; N=9'd84;

#20 M=16'd24618; N=9'd586;


#20 $finish;
end
endmodule
2.3 Simulation Result:

4. Comparison:
As per the simulation results both the multipliers are giving same results for same set of
inputs.

Below is the table mentioning the inputs and results of both multipliers:

Mixed
Inputs (M,N and X,Y) Behavioral Model
16'haaaa and 9'h169 25'hofoa9ba 25'hofoa9ba
16'ha553 and 9'h15a 25'h0df722e 25'h0df722e
16'h0100 and 9'h054 25'h0005400 25'h0005400
16'h602a and 9'h04a 25'h01bcc24 25'h01bcc24

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