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Verilog HDL MODEL QP (15ec53)

This document is a model question paper for a Verilog HDL course. It contains 10 questions across 5 modules. Questions can be answered from any module, with a maximum of 80 marks. The questions cover topics like Verilog design flow, levels of abstraction, comments and identifiers, module components, tasks, gates, ripple carry adder, multiplexer, ports, conditional statements, loops, synthesis process, and VHDL concepts. Students have to write code examples and explanations for Verilog and VHDL constructs.

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191 views2 pages

Verilog HDL MODEL QP (15ec53)

This document is a model question paper for a Verilog HDL course. It contains 10 questions across 5 modules. Questions can be answered from any module, with a maximum of 80 marks. The questions cover topics like Verilog design flow, levels of abstraction, comments and identifiers, module components, tasks, gates, ripple carry adder, multiplexer, ports, conditional statements, loops, synthesis process, and VHDL concepts. Students have to write code examples and explanations for Verilog and VHDL constructs.

Uploaded by

indu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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15EC53

Visvesvaraya Technological University, Belagavi


MODEL QUESTION PAPER
5th Semester, B.E (CBCS) EC
Course: 15EC53 - Verilog HDL

Note: (i) Answer Five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or 2nd question.

Time: 3 Hrs Max. Marks: 80

Module-1
1 a. Explain a typical design flow for designing VLSI IC circuits using the block 08
diagram.
b. Explain the different levels of Abstraction used for programming in Verilog. 08
OR
2 a. Explain a top-down design methodology and a bottom-up design methodology. 10
b. Explain the factors that have made Verilog HDL popular. 06
Module-2
3 a. Write a note on i) Comments ii) Number Specification iii) X and Z values and iv) 10
Identifiers and Keywords with suitable examples.
b. Explain a Components of a Verilog Module with a neat block diagram. 06
OR
4 a. Explain $display and $monitor tasks with examples. 10
b. A 4-bit parallel shift register has I/O pins as shown in the figure below. Write the 06
module definition for this shift register. Include the list of ports and port
declarations (no need to show the internals).

Module-3
5 a. Explain the instantiation of gates by writing a gate level module by name gates 04
in Verilog.
b. Explain regular assignment delay in dataflow level of abstraction in Verilog. 04
c. The input output expressions for 1-bit Full Adder are given as sum= a ^ b^ c; 08
co= (a &b)|(b&c)|(c&a). Write the gate level abstraction of 1-bit Full Adder by
instantiating and, or, xor gates only.
OR
6 a. Write the Verilog description of 4-bit Ripple carry Adder at Gate level 08
Abstraction.
b. Write a program for 4-to-1 Multiplexer, Using Conditional Operators in dataflow 08
level of abstraction in Verilog.
Module-4
7 a. Explain combined port declaration and combined ANSI C style port declaration 04
with examples in Verilog.
b. Explain the conditional statements in Verilog. 04
c. Write a behavioral 4 bit counter program in Verilog. 08
OR
8 a. Explain different Loop statements in Verilog. 08
b. Write a Verilog behavioral 4 to 1 Multiplexer program using CASE statement. 08
Module-5
9 a. Explain the synthesis process with a block diagram. 08
b. Write the VHDL entity declaration of 4- bit Ripple Carry Adder with the help of 08
lock diagram of 4- bit Ripple Carry adder.
OR
10 a. Explain the relationship between a design entity and its entity declaration and 08
architecture body in VHDL.
b. Explain the declaration of constant, variable and signal in VHDL with examples. 08

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