PCM 1867
PCM 1867
PCM 1867
IN DOUT DOUT
MIC
BCK
PCM186x TMS320C5535 PCM5121 TPA3116
LRCK
SW mix
IN
LINE
BCK
PCM5100 TPA3116
LRCK
USB
IN
1
Copyright © 2017, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1860, PCM1861, PCM1862
PCM1863, PCM1864, PCM1865
SLAS831D – MARCH 2014 – REVISED MARCH 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 10.1 Application Information.......................................... 70
2 Applications ........................................................... 1 10.2 Typical Applications .............................................. 75
3 Description ............................................................. 1 11 Power Supply Recommendations ..................... 79
4 Revision History..................................................... 2 11.1 Power-Supply Distribution and Requirements ...... 79
11.2 1.8-V Support ........................................................ 79
5 Device Comparison Table..................................... 7
11.3 Brownout Conditions ............................................. 79
6 Pin Configuration and Functions ......................... 8
11.4 Power-Up Sequence ............................................. 80
7 Specifications....................................................... 12
11.5 Lowest Power-Down Modes ................................. 80
7.1 Absolute Maximum Ratings .................................... 12
11.6 Power-On Reset Sequencing Timing Diagram .... 81
7.2 ESD Ratings............................................................ 12
11.7 Power Connection Examples................................ 82
7.3 Recommended Operating Conditions..................... 12
11.8 Fade In .................................................................. 83
7.4 Thermal Information ................................................ 12
12 Layout................................................................... 84
7.5 Electrical Characteristics: PGA and ADC AC
Performance............................................................. 13 12.1 Layout Guidelines ................................................. 84
7.6 Electrical Characteristics: DC ................................. 14 12.2 Layout Example .................................................... 85
7.7 Electrical Characteristics: Digital Filter.................... 16 13 Register Maps...................................................... 85
7.8 Timing Requirements: External Clock..................... 16 13.1 Register Map Description...................................... 85
7.9 Timing Requirements: I2C Control Interface .......... 17 13.2 Register Map Summary ........................................ 86
7.10 Timing Requirements: SPI Control Interface ....... 18 13.3 Page 0 Registers ................................................. 89
7.11 Timing Requirements: Audio Data Interface for 13.4 Page 1 Registers ............................................... 129
Slave Mode .............................................................. 19 13.5 Page 3 Registers ............................................... 132
7.12 Timing Requirements: Audio Data Interface for 13.6 Page 253 Registers ........................................... 133
Master Mode ............................................................ 20 14 Device and Documentation Support ............... 134
7.13 Typical Characteristics .......................................... 21 14.1 Documentation Support ...................................... 134
8 Parameter Measurement Information ................ 23 14.2 Related Links ...................................................... 134
9 Detailed Description ............................................ 25 14.3 Receiving Notification of Documentation
9.1 Overview ................................................................. 25 Updates.................................................................. 134
9.2 Functional Block Diagrams ..................................... 25 14.4 Community Resources........................................ 134
9.3 Features Description .............................................. 28 14.5 Trademarks ......................................................... 134
9.4 Device Functional Modes........................................ 60 14.6 Electrostatic Discharge Caution .......................... 134
9.5 Programming........................................................... 62 14.7 Glossary .............................................................. 134
10 Application and Implementation........................ 70 15 Mechanical, Packaging, and Orderable
Information ......................................................... 135
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added PCM1860, PCM1862, and PCM1864 and related content to this data sheet; these devices were previously in
a separate data sheet (SLASE55A) ....................................................................................................................................... 1
• Changed title for clarity........................................................................................................................................................... 1
• Changed Feature bullets to include new devices................................................................................................................... 1
• Added Feature bullets to clarify hardware- and software-controlled devices......................................................................... 1
• Changed Application from "Automotive Head Units" to "Voice Controlled Devices".............................................................. 1
• Changed Description section text to clarify 3.3-V supply, integrated PGA, and additional front-end features ...................... 1
• Changed Simplified Application Diagram to combine two previous figures into one figure ................................................... 1
• Deleted Typ Performance (3.3-V Supply, –1 dB-FS Input) table; redundant content ............................................................ 7
• Changed Device Comparison Table; updated for clarity........................................................................................................ 7
• Changed reference voltage output dcoupling point typical value from 0.5 VCC to 0.5 AVDD in VREF pin description........ 9
• Changed XO (pin 9) type from "—" to "Digital output" in both Pin Functions tables ............................................................. 9
• Changed "latch enable" to "word clock" in LRCK pin description ......................................................................................... 9
• Changed reference voltage output dcoupling point typical value from 0.5 VCC to 0.5 AVDD in VREF pin description ..... 11
VINL2/VIN1M 1 30 VINR3/VIN3P
VINR2/VIN2M 2 29 VINL3/VIN4P
VINL1/VIN1P 3 28 VINR4/VIN3M
VINR1/VIN2P 4 27 VINL4/VIN4M
VREF 6 25 MD1
AGND 7 24 MD3
AVDD 8 23 MD2
XO 9 22 MD4
XI 10 21 MD5
LDO 11 20 MD6
DGND 12 19 INT
DVDD 13 18 DOUT
IOVDD 14 17 BCK
SCKI 15 16 LRCK
Not to scale
(1) Schmitt trigger input with internal pull-down (50 kΩ, typically).
VINL2/VIN1M 1 30 VINR3/VIN3P
VINR2/VIN2M 2 29 VINL3/VIN4P
VINL1/VIN1P 3 28 VINR4/VIN3M
VINR1/VIN2P 4 27 VINL4/VIN4M
VREF 6 25 MS/AD
AGND 7 24 MC/SCL
AVDD 8 23 MOSI/SDA
XO 9 22 MISO/GPIO0/DMIN2
XI 10 21 GPIO1/INTA/DMIN
LDO 11 20 GPIO2/INTB/DMCLK
DGND 12 19 GPIO3/INTC
DVDD 13 18 DOUT
IOVDD 14 17 BCK
SCKI 15 16 LRCK
Not to scale
NOTE: The DMIN2 option for pin 22 is only available on the PCM1864 and PCM1865 devices.
(1) Schmitt trigger input with internal pull-down (50 kΩ, typically).
7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature (unless otherwise noted) (1)
MIN MAX UNIT
AVDD to AGND –0.3 3.9
Supply voltage DVDD to DGND –0.3 3.9 V
IOVDD to DGND –0.3 3.9
Ground voltage differences AGND to DGND –0.3 0.3 V
Digital input to DGND –0.3 IOVDD + 0.3
Digital input voltage V
XI to DGND –0.3 2.1
Analog input voltage VINxx to AGND –1.7 5.0 V
Operating ambient, TA –40 125
Temperature Junction, TJ –40 150 °C
Storage, Tstg –40 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) 32-dB gain when using differential mode inputs is only available in SW-controlled devices.
(2) Specified by design.
(1) IOVDD and LDO current consumption is negligible for software-controlled devices in standby mode.
14 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated
Repeated
START START STOP
SDA
SCL
MS
tMCH tMCL
tMSS tMSH tMHH
MC
tMCY
tMDS tMDH
(1) Timing measurement reference level is 1.4 V for input and 0.5VDD for output. Rise and fall times are measured from 10% to 90% of the
IN/OUT signals swing. Load capacitance of DOUT is 20 pF. tSCKI means SCKI period.
tLRCP
LRCK 1.4 V
BCK 1.4 V
Figure 3. Audio Data Interface Timing, Slave Mode: LRCK and BCK as Inputs
(1) Timing measurement reference level is 0.5 VDD. Rise and fall times are measured from 10% to 90% of the IN/OUT signals swing. Load
capacitance of all signals are 20 pF.
(2) Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing is applied
when SCKI frequency is less than 25 MHz.
tLRCP
Figure 4. Audio Data Interface Timing, Master Mode: LRCK and BCK as Outputs
SCKI 1.4 V
tSCKBCK tSCKBCK
0.5 VDD
BCK
0 0
Total Harmonic Distortion + Noise (dB)
-40 -40
-60 -60
-80 -80
-100 -100
-90 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Level (dBFS) D001
Input Level (dBFS) D002
PCM1861, PCM1863, and PCM1865 PCM1860, PCM1862, and PCM1864
Amplitude (dB)
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
-150 -150
-160 -160
0 4 8 12 16 20 0 4 8 12 16 20
Frequency (kHz) D003
Frequency (kHz) D004
PCM1861, PCM1863, and PCM1865 PCM1860, PCM1862, and PCM1864
Input = –60 dBFS at 1 kHz Input = –60 dBFS at 1 kHz
Figure 8. Main ADC Output FFT Figure 9. Main ADC Output FFT
0 0
-20 -20
-40 -40
Amplitude (dB)
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
0 4 8 12 16 20 0 4 8 12 16 20
Frequency (kHz) D005
Frequency (kHz) D006
PCM1861, PCM1863, and PCM1865 PCM1860, PCM1862, and PCM1864
Input = –1 dBFS at 1 kHz Input = –1 dBFS at 1 kHz
Figure 10. Main ADC Output FFT Figure 11. Main ADC Output FFT
-109 -102.7
-102.8
-109.25
Dynamic Range (dB)
-110 -103.2
-103.3
-110.25
-103.4
-110.5 -103.5
-110.75 -103.6
3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V) D007
Supply Voltage (V) D008
PCM1861, PCM1863, and PCM1865 PCM1860, PCM1862, and PCM1864
Figure 12. Dynamic Range vs Supply Voltage Figure 13. Dynamic Range vs Supply Voltage
-94.1 -91.5
Total Harmonic Distortion + Noise (dB)
-94.6 -91.7
-94.7 -91.75
-94.8
-91.8
-94.9
-95 -91.85
-95.1 -91.9
3 3.1 3.2 3.3 3.4 3.5 3.6 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V) D009
Supply Voltage (V) D010
PCM1861, PCM1863, and PCM1865 PCM1860, PCM1862, and PCM1864
Figure 14. THD+N vs Supply Voltage Figure 15. THD+N vs Supply Voltage
250 0
-5
200
Power Consumption (mW)
-10
Amplitude (dB)
150
-15
-20
100
-25
50
4ch -30
2ch
0 -35
48 96 144 192 20 200 2k 20k
Sample Rate (kHz) D011
Frequency (Hz) D012
At fS = 48 kHz, 96 kHz, and 192 kHz fS = 48 kHz
Figure 16. Power Consumption vs Sample Rate Figure 17. Secondary ADC Frequency Response
-20 -20
-40 -40
Amplitude (dB)
Amplitude (dB)
-60 -60
-80 -80
-100 -100
-120 -120
-140 -140
-160 -160
0 4 8 12 16 20 0 10 20 30 40 50 60
Frequency (kHz) D013
Frequency (kHz) D014
fS = 48 kHz fS = 192 kHz, BW = 60 kHz, Input = –1 dBFS
Figure 18. Secondary ADC FFT Figure 19. High Bandwidth FFT of THD Components
40 0
36
-10
32
28 -20
Output Amplitude (dB)
24 -30
20
16 -40
12 -50
8
4 -60
0 -70
-4
-80
-8
-12 -90
-12 -8 -4 0 4 8 12 16 20 24 28 32 36 40 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude (dB) D015
Input Amplitude (dB) D016
Figure 20. PGA ADC Gain Figure 21. Linearity, Input vs Output
ANALOG ANALOG
IN2L 1
J2 DNP
INPUTS GND
2
J4 1 IN3L INPUTS
IN2R 3 R4 R5 R6 R7 R8 R9 R10 R11 2
100LS 2.20K 2.20K 2.20K 2.20K 2.20K 2.20K 2.20K 2.20K GND
1 C1 VINL2/VIN1M 0603 0603 0603 0603 0603 0603 0603 0603 3 IN3R 1
L 10uF/16V 0805 X7R 100LS L
VIN2 2 C2 VINR2/VIN2M VINR3/VIN3P C15 2 VIN3
R 10uF/16V 0805 X7R 10uF/16V 0805 X7R R
Case R40 R41 IN1L 1 MICBIAS VINL3/VIN4P C16 R44 R45 Case
100K
0402
100K
0402
J3 MICBIAS 10uF/16V 0805 X7R 100K
0402
100K
0402
2 C14
GND GND Orange 1 IN4L GND
GND GND
IN1R 3
0.1ufd/50V
J5 GND GND
100LS 2
1 C3 VINL1/VIN1P
0603 X7R GND 1
L 10uF/16V 0805 X7R 3 IN4R L
VIN1 2 C4 VINR1/VIN2P
GND
VINR4/VIN3M C17 100LS
2 VIN4
R 10uF/16V 0805 X7R 1 10uF/16V 0805 X7R R
Case R42 R43 2 J6 VINL4/VIN4M C18 R46 R47 Case
100K 100K 2L 100LS 3R 10uF/16V 0805 X7R 100K 100K
0402 0402 Orange Orange 0402 0402
GND GND GND
2R 3L
GND GND Orange 1 Orange GND GND
1L 2 J9 4R
Orange 100LS Orange +3.3VA MD0
1
3 2
1R 4L
Orange Orange 4 0603
XO U1 +3.3VA
1 MD1/AD GND
C6 XO
1 30 3 2
GPIO
GND 4 0603
Y0 1 20pfd/50V 0603 COG 2 29
24.576MHz
HC-49USX GND
C7 XI 3 28
GND
+3.3VA I2C
2 20pfd/50V 0603 COG 1 MD3/MC/SCL
4 27 3 2 SCL-PCM
XI 1 J7
J11 5 26 MD0 4 0603 1 2
2 C5
100LS 6 25 MD1/AD +3.3VA 3 4
GND 1.0ufd/16V 0603 X7R DOUT2/MD2/MOSI/SDA GND
1
7 24 MD3/MC/SCL 3 2 SDA-PCM 5 6
GND GND
+3.3V +1.8V 8 23 DOUT2/MD2/MOSI/SDA 4 0603 7 8
9 22 MD4/MISO/GPIO +3.3VA 9 10
GND MD4/MISO/GPIO
C40 C19 10 21 MD5/GPIO1/INTA/DMIN 3
1
2 11 12
0.1ufd/16V 0.1ufd/16V
+3.3VA R1 11 20 MD6/GPIO2/INTB/DMCLK 4 0603 13 14
0402 X7R 0402 X7R
0.0
12 19 INT/GPIO3/INTC +3.3VA 15 16
+3.3V GND GND 0603 C8 C9 GND MD5/GPIO1/INTA/DMIN GND
1
13 18 3 2 GND
10ufd/10V 0.1ufd/16V DOUT
R13
+3.3V U4 +1.8V 0805 X7R 0402 X7R
14 17 Orange 4 0603
GND GND
XO-BUF
SCKI
SCKI
LRCK DOUT
LRCK DOUT
BCK
BCK
DIN
DIN SPDIF I2S
SDA-PCM
I2C BUS SCL-PCM
9 Detailed Description
9.1 Overview
The PCM186x family of audio, analog-to-digital converters (ADCs) features a highly flexible, audio front end that
supports input levels from small millivolt microphone inputs to 2.1-VRMS line inputs. The analog front end can be
configured to support either differential or single-ended inputs, providing optimal performance when using
differential inputs. Mixing single-ended and differential inputs is possible. A digital microphone interface is
available in the software-controlled devices.
These devices support advanced clocking with the aid of an integrated oscillator circuit and an on-chip analog
phase-locked loop (PLL). The integrated oscillator circuit allows for the use of an external crystal or an external
master clock as the clock source in master mode. In addition, the PLL can be used to generate an on-chip
master clock that can be shared with the rest of the system, all from a bit clock input. This feature is useful in
systems where the audio source has no master clock to drive digital-to-analog converters (DACs) and amplifiers.
The on-chip clock monitoring system can also be monitored by the system microcontroller, in case clocks are lost
and the device enters sleep or standby state.
The secondary analog-to-digital converter (ADC) is a low-power, non-audio ADC that is used in sleep mode to
monitor the analog inputs. The secondary ADC is also used in controlsense mode to measure dc voltages in a
system, such as battery voltage and control potentiometers. In addition, controlsense features offer an option to
generate interrupts after detected voltages cross specific thresholds, allowing the microcontroller to be in a lower-
power sleep mode while the control voltages being measured are stable.
Control registers in this data sheet are shown as REGISTER_BIT_or_BYTE_NAME (page.x hex_address).
PCM1860
VINL1/VIN1P PCM1861
VINL2/VIN1M MIX, Primary
PGA
VINL3/VIN4P MUX ADC
INT
VREF MD6
Reference
Mic Bias MD5
Control MD4
and
Interrupt MD3
MD2
Power Clocks, PLL
MD1
MD0
LDO
DGND
DVDD
IOVDD
AGND
AVDD
XI
XO
SCKI
PCM1862
VINL1/VIN1P PCM1863
VINL2/VIN1M MIX, Primary
PGA
VINL3/VIN4P MUX ADC
XI
XO
SCKI
PCM1864
Primary
PCM1865
PGA ADC
(CH1L)
VINL1/VIN1P
Primary
VINL2/VIN1M MIX,
PGA ADC
VINL3/VIN4P MUX
(CH2L)
VINL4/VIN4M Audio BCK
Mixer and
Secondary Serial
Energysense LRCK
ADC Port
DSPs
VINR1/VIN2P (LJ, I2S, TDM) DOUT
VINR2/VIN2M MIX, Primary
PGA ADC
VINR3/VIN3P MUX
(CH1R)
VINR4/VIN3M Primary DOUT2
PGA ADC
(CH2R)
DMIC/DIN
GPIO3/INTC
VREF GPIO2/INTB/DMCLK
Reference
Mic Bias GPIO1/INTA/DMIN
Control,
GPIO, MISO/GPIO0/DMIN2
Interrupt, MOSI/SDA
Digital Mic Interface
MC/SCL
Power Clocks, PLL
MS/AD
MD0
LDO
DGND
DVDD
IOVDD
AGND
AVDD
XI
XO
SCKI
SCKI
SCK0
XI (GPIO)
MUX
XO
Clock Generator
MUX PLL LRCK
Analog and Detector
BCK_IN
CTRL PGA BCK
Controller
Audio
ADC On-Chip
Oscillator
Analog PGAs
Audio
ADC
GPIO2/INTB/DMCLK
GPIO1/INTA/DMIN Digital Mic Inputs
MISO/GPIO0/DMIN2
PGA Zero
Cross
Detect
On-Chip
1/8
Oscillator
Mic I2C/SPI
Mic Bias
Bias Port
PCM186x
Mic Bias
Generator Digial Microphone PDM Input
(Software Controlled Devices Only)
VINL1/VIN1P
VINL2/VIN1M MIX, Audio
VINL3/VIN4P MUX ADC
DC blocking capacitors are required on the analog inputs to make sure that correct dc bias conditions are
established. Because the value of the output short-circuit protection resistor in the source product is typically
unknown, issues such as gain error and dc shift may occur if dc blocking capacitors are not used.
For systems where external amplifiers are used before the PCM186x, dc blocking capacitors are still
recommended because the input pins are designed to bias to AVDD / 2. The common mode voltage range is still
limited to the maximum input voltage of the device.
Do not connect unused analog input pins.
The analog gain steps within the analog PGA are shown in Figure 29. Again, from –12 dB to +12 dB, the steps
are 1 dB each. The digital PGA has granularity down to 0.5 dB.
PGA
0x74.0 0x0C.0 0x14.0 0x40.0
Value
±12 dB to +12 dB in 1-dB steps
±12 dB 0 dB 12 dB 20 dB 32 dB
The PGA in the PCM186x is a hybrid analog and digital programmable gain amplifier. The devices integrate a
lookup table with the optimal gain balance between analog and digital gain, allowing the gain to be set in a single
register per channel. For example, set 18 dB gain, and the system allocates 12 dB to the analog PGA, and 6 dB
to the digital PGA. This function is called auto gain mapping.
The PGA is a zero crossing detect type, and has the ability to set target gain, and have the device work towards
it (with a timeout if there is no zero crossing). Any changes in the Analog PGA and digital PGA are designed to
step towards the final level. However, any changes in the mixer PGA are immediate. Take care when changing
gain levels in the digital mixer PGA. Alternatively, multiple writes can be made of small enough values that do not
cause significant pops or clicks.
NOTE
Changing gain in the PGA requires the on-chip DSP to be clocked. The DSP is used to
calculate the steps to the target gain. This is not an issue in master mode, but can be a
challenge in slave mode, if the system master is not active yet.
For example, if the current level = 0 dB, then set the target as 3.5 dB. The PGA then increases gain in 0.5-dB
steps towards 3.5 dB.
The auto gain mapping function can by bypassed if required, using manual gain mapping. Manual gain mapping
is useful when using digital microphones, as the PDM input signal bypasses the analog PGA and must be
amplified using the digital PGA. (PGA_MODE (Page.0, 0x19). Digital PGA update is only available in the 4-
channel devices because the digital gain in 2-channel devices is fixed to 0 dB when manual gain mapping is
enabled.
NOTE
Using the device with a differential inputs increases the full-scale voltage to 4.2 VRMS
(that's 2.1 VRMS per pin, out of phase).
Zero
PGA
Cross
Controller
Detector
Auto
Digital PGA
Gain
Overflow Detector
Control
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Sampling Points Within the PCM186x for Auto Clipping Suppression
GPIO1
DATA_L
DATA DIGMIC_IN1
Wired-OR
GPIO1
L/R SEL
CLK
GND
VDD
DATA_R
DATA
L/R SEL
GPIO2
CLK DIGMIC_CLK (64 × fS)
GPIO2
GPIO2
(DIGMIC_CLK)
Hi -Z Hi -Z
DATA_L L(n) L(n+1) L(n+2)
Supported Digital Microphone clock frequency is as follows, and the frequency depends on required operating
sampling frequency as follows:
• 2.0480 MHz (32 kHz × 64)
• 2.8224 MHz (44.1 kHz × 64)
• 3.072 MHz (48 kHz × 64)
• 3.072 MHz (96 kHz × 32 )
The recommended operating conditions for the Digital MIC are:
• Sampling frequency is 32 kHz or 44.1 kHz
• SCK is 256 × fS.
• Enable Auto Clock Detector (Default)
9.3.9 Clocks
9.3.9.1 Description
The PCM186x family has an extremely flexible clocking architecture. All converters require a master clock
(typically, a 2n power of the sampling rate known as MCK), a bit clock (BCK) that is used to clock the data bit-by-
bit out of the device (typically running at 64-fS to allow up to 32 bits per channel output), and finally a wordclock
(left-right clock, LRCK) that is used to set the exact sampling point for the ADC.
The PCM186x family can be a clock master (where BCK and LRCK can be internally divided from a provided
master clock) or can be a clock slave, where all clocks (MCK, BCK and LRCK) must be provided by an external
source.
Unlike many competing devices, the PCM186x family can source its master clock from two different sources,
either an external crystal, or a CMOS level (3.3 V or 1.8 V) clock, eliminating the usual external crystal oscillator
circuit required to source a CMOS clock signal.
The PCM186x also differentiates itself by integrating an on-chip phase locked loop (PLL) that can generate real
audio-rate clocks from any clock source between 1 MHz and 50 MHz. The PCM1860 or PCM1861 hardware-
controlled devices have the ability to detect an absence of MCK in slave mode and automatically generate a
MCK signal. Software-controlled devices, such as the PCM1862, PCM1863, PCM1864 and PCM1865 can have
their PLL programmed to generate audio clocks based on any incoming clock rate. For example, a 12 MHz clock
in the system can be used to generate clocks for a 44.1-kHz system.
PCM186x
PLL_REF_SEL
(Page 0 Reg 0x28)
XO
SCK_XI_SEL[1:0] SCK
Clock
ADC_CLK_SRC
(Page 0 Reg 0x20) MUX Divider Audio ADC Clocks
(Page 0 Reg 0x20)
(0x23)
PLL Clock
XI
SCKI PLL
MUX SCK
Clock
K×R/P DSP1_CLK_SRC
MUX Divider DSP #1
BCK (Page 0 Reg 0x20)
(0x21)
PLL Clock
LRCK
K = J.D
J = 1,2,3, « ,62,63 SCK
DSP2_CLK_SRC Clock
D = 0000,0001, « ,9999
R = 1,2,3,4, « ,15,16 (Page 0 Reg 0x20) MUX Divider DSP #2
PLL Clock (0x22)
P = 1,2, « ,127,128
SCKI
MST_SCK_SRC SCK_OUT_TO_GPIO
MUX
(Page 0 Reg 0x20)
Clock
PLL Clock Divider
MUX Autoset by
Master/Slave mode
SCKI
CLK_DIV_PLL_SCK
(Page 0 Reg 0x25)
Autoset by format
Clock
Divider
BCK OUT IN
MUX MUX
MASTER MODE
BCK
CLK_DIV_SCK_BCK
(Page 0 Reg 0x26)
Clock
Divider
LRCK OUT IN
MUX
MASTER MODE
LRCK
CLK_DIV_BCK_LRCK
(Page 0 Reg 0x27)
Figure 33. PCM186x Main Audio Clock Tree and Clock Generation
Target Clock Rates for the ADC, DSP1 and DSP2 can be seen in Table 9 and Table 10. In manual clock
configuration modes, the dividers should be set to achieve these targets. In short, for 2-channel devices, DSP1
and DSP2 should be 256x the sampling rate; for 4-channel devices, DSP1 should be configured for 512x the
sampling rate, and DSP2 should be 256x.
The relation between the master mode configuration registers is shown in Table 7.
NOTE
Non audio related master clock sources can be used with the PCM186x software -
controlled devices providing the PLL is programmed manually. CLKDET_EN should be set
to 0.
The result of configurations can be checked by reading registers FS_INFO / CURRENT_BCK_RATIO (Page.0
0x73 and 0x74).
NOTE
In master mode on software-controlled devices, only the following BCK to LRCK ratios are
supported: 32x, 48x, 64x and 256x. 128x is not supported
PCM186x
PLL_REF_SEL
(Page 0 Reg 0x28)
XO
SCK_XI_SEL[1:0] SCK
Clock
ADC_CLK_SRC
(Page 0 Reg 0x20) MUX Divider Audio ADC Clocks
(Page 0 Reg 0x20)
(0x23)
PLL Clock
XI
SCKI PLL
MUX SCK
Clock
K×R/P DSP1_CLK_SRC
MUX Divider DSP #1
BCK (Page 0 Reg 0x20)
(0x21)
PLL Clock
LRCK
K = J.D
J = 1,2,3, « ,62,63 SCK
DSP2_CLK_SRC Clock
D = 0000,0001, « ,9999
R = 1,2,3,4, « ,15,16 (Page 0 Reg 0x20) MUX Divider DSP #2
PLL Clock (0x22)
P = 1,2, « ,127,128
SCKI
MST_SCK_SRC SCK_OUT_TO_GPIO
MUX
(Page 0 Reg 0x20)
Clock
PLL Clock Divider
MUX Autoset by
Master/Slave mode
SCKI
CLK_DIV_PLL_SCK
(Page 0 Reg 0x25)
Autoset by format
Clock
Divider
BCK OUT IN
MUX MUX
MASTER MODE
BCK
CLK_DIV_SCK_BCK
(Page 0 Reg 0x26)
Clock
Divider
LRCK OUT IN
MUX
MASTER MODE
LRCK
CLK_DIV_BCK_LRCK
(Page 0 Reg 0x27)
Table 8. Minimum Required Clock Ratios for ADC, DSP1 and DSP2
CORE 2-CHANNEL DEVICE RATIO 4-CHANNEL DEVICE RATIO
ADC 128x output sampling rate 128x output sampling rate
DSP #1 256x output sampling rate 512x output sampling rate
DSP #2 256x output sampling rate 256x output sampling rate
Table 9. PCM1862 and PCM1863 (2-Channel) Clock Divider and Source Control in the Presence of External SCK
SCK FREQ PLL FREQ DSP1 CLOCK DSP1 CLOCK DSP 2 DSP2 CLOCK ADC CLOCK ADC CLOCK
fS SCK RATIO PLL RATIO PLL CONFIG
(MHz) (MHz) (MHz) SOURCE DIVIDER CLOCK (MHz) SOURCE DIVIDER (MHz) SOURCE DIVIDER
P=1,R=2,
128 1.024 12288 98.304 2.048 PLL 48 2.048 PLL 48 1.024 PLL 96
J=48, D=0
P=1,R=2,
256 2.048 12288 98.304 2.048 SCK 1 2.048 SCK 1 1.024 SCK 2
J=24, D=0
8 kHz
P=1,R=2,
384 3.072 12288 98.304 2.048 SCK 1 2.048 SCK 1 1.024 SCK 3
J=16, D=0
512 4.096 Off 2.048 SCK 2 2.048 SCK 2 1.024 SCK 4
768 6.144 Off 3.072 SCK 2 3.072 SCK 2 1.024 SCK 6
P=1,R=2,
128 2.048 6144 98.304 4.096 PLL 24 4.096 PLL 24 2.048 PLL 48
J=24, D=0
P=1,R=2,
256 4.096 6144 98.304 4.096 SCK 1 4.096 SCK 1 2.048 SCK 2
J=12, D=0
16 kHz
P=1,R=2, J=8,
384 6.144 6144 98.304 6.144 SCK 1 6.144 SCK 1 2.048 SCK 3
D=0
512 8.192 Off 4.096 SCK 2 4.096 SCK 2 2.048 SCK 4
768 12.288 Off 6.144 SCK 2 6.144 SCK 2 2.048 SCK 6
P=1,R=2, J=8,
128 6.144 2048 98.304 12.288 PLL 8 12.288 PLL 8 6.144 PLL 16
D=0
P=2,R=2, J=8,
256 12.288 2048 98.304 12.288 SCK 1 12.288 SCK 1 6.144 SCK 2
D=0
48 kHz
P=3,R=2, J=8,
384 18.432 2048 98.304 18.432 SCK 1 18.432 SCK 1 6.144 SCK 3
D=0
512 24.576 Off 12.288 SCK 2 12.288 SCK 2 6.144 SCK 4
768 36.864 Off 18.432 SCK 2 18.432 SCK 2 6.144 SCK 6
P=4,R=2,
128 12.288 1024 98.304 24.756 PLL 4 24.756 PLL 4 6.144 SCK 2
J=16, D=0
P=8,R=2,
256 24.576 1024 98.304 24.756 SCK 1 24.756 SCK 1 6.144 SCK 4
96 kHz J=16, D=0
P=12,R=2,
384 36.864 1024 98.304 24.756 SCK 1 24.756 SCK 1 6.144 SCK 6
J=16, D=0
512 49.152 Off 24.756 SCK 2 24.756 SCK 2 6.144 SCK 8
P=4,R=2, J=8,
128 24.576 512 98.304 49.152 PLL 2 49.152 PLL 2 6.144 SCK 4
D=0
192 kHz
P=8,R=2, J=8,
256 49.152 512 98.304 49.152 SCK 1 49.152 SCK 1 6.144 SCK 8
D=0
Table 10. PCM1864 and PCM1865 (4-Channel) Clock Divider and Source Control With External SCK
SCK FREQ PLL FREQ DSP1 CLOCK DSP1 CLOCK DSP 2 DSP2 CLOCK ADC CLOCK ADC CLOCK
fS SCK RATIO PLL RATIO PLL CONFIG
(MHz) (MHz) (MHz) SOURCE DIVIDER CLOCK (MHz) SOURCE DIVIDER (MHz) SOURCE DIVIDER
P=1,R=2,
128 1.024 12288 98.304 4.096 PLL 24 2.048 PLL 48 1.024 PLL 96
J=48, D=0
P=1,R=2,
256 2.048 12288 98.304 4.096 PLL 24 2.048 SCK 1 1.024 SCK 2
J=24, D=0
8 kHz P=1,R=2,
384 3.072 12288 98.304 4.096 PLL 24 2.048 SCK 1 1.024 SCK 3
J=16, D=0
512 4.096 Off 4.096 SCK 1 2.048 SCK 2 1.024 SCK 4
P=1,R=2, J=8,
768 6.144 6144 98.304 4.096 PLL 24 3.072 SCK 2 1.024 SCK 6
D=0
P=1,R=2,
128 2.048 6144 98.304 8.192 PLL 12 4.096 PLL 24 2.048 PLL 48
J=24, D=0
P=1,R=2,
256 4.096 6144 98.304 8.192 PLL 12 4.096 SCK 1 2.048 SCK 2
J=12, D=0
16 kHz P=1,R=2, J=8,
384 6.144 6144 98.304 8.192 PLL 12 6.144 SCK 1 2.048 SCK 3
D=0
512 8.192 Off 8.192 SCK 1 4.096 SCK 2 2.048 SCK 4
P=4,R=2,
768 12.288 2048 98.304 8.192 PLL 12 6.144 SCK 2 2.048 SCK 6
J=16, D=0
P=1,R=2, J=8,
128 6.144 2048 98.304 24.576 PLL 4 12.288 PLL 8 6.144 PLL 16
D=0
P=4,R=2,
256 12.288 2048 98.304 24.576 PLL 4 12.288 SCK 1 6.144 SCK 2
J=16, D=0
48 kHz P=3,R=2, J=8,
384 18.432 2048 98.304 24.576 PLL 4 18.432 SCK 1 6.144 SCK 3
D=0
512 24.576 Off 24.576 SCK 1 12.288 SCK 2 6.144 SCK 4
P=3,R=2, J=4,
768 36.864 2048 98.304 24.576 PLL 4 18.432 SCK 2 6.144 SCK 6
D=0
P=4,R=2,
128 12.288 1024 98.304 49.152 PLL 2 24.756 PLL 4 6.144 SCK 2
J=16, D=0
P=4,R=2, J=8,
256 24.576 1024 98.304 49.152 PLL 2 24.756 SCK 1 6.144 SCK 4
96 kHz D=0
P=12,R=2,
384 36.864 1024 98.304 49.152 PLL 2 24.756 SCK 1 6.144 SCK 6
J=16, D=0
512 49.152 Off 49.152 SCK 1 24.756 SCK 2 6.144 SCK 8
P=4,R=2, J=8,
128 24.576 512 98.304 98.304 PLL 1 49.152 PLL 2 6.144 SCK 4
D=0
192 kHz
P=8,R=2, J=8,
256 49.152 512 98.304 98.304 PLL 1 49.152 SCK 1 6.144 SCK 8
D=0
In software SPI or I2C mode, a PCM186x software-controlled device can use the on-chip crystal oscillator, if a
CMOS clock source is not available. Audio clocks can be generated through the PLL from the non-audio
standard CMOS or crystal frequency (and then can be divided down as described previously). This function is not
available in hardware mode.
The 8-kHz sampling rate is only supported if an external MCK is provided. The autodetect and PLL system
support frequencies as low as 32 kHz. Analog performance is not tested in this mode.
The clock tree can also be programmed manually, with the settings shown in Table 12 and Table 13.
The PLL can be programmed using page 0, registers 0x28 thru 0x2D. Turn on the PLL using page 0, register
0x28, D(0). The variable P can be programmed using page 0, register 0x29, D(3:0). The variable R can be
programmed using page 0, register 0x2A, D(3:0). The variable J can be programmed using page 0, register
0x2B, D(5:0). The variable D is 14-bits and is programmed into two registers. The MSB portion is programmed
using page 0, register 0x2D, D(5:0), and the LSB portion is programmed using page 0, register 0x2C, D(7:0).
The variable D is set when the LSB portion is programmed.
Values are programmed in the registers in Table 14.
In addition, the device uses an on-chip oscillator to detect errors in the rate of present clocks. That logic is shown
in Table 16.
In an application with a non-audio standard SCK coming into the product, the clock error detection on the SCK
pin can be ignored by disabling the auto clock detector (CLKDET_EN Page.0 0x20).
NOTE
Hardware-controlled devices cannot switch from XTAL master mode to external slave
mode because the XTAL continues clocking the internal SCLK and not be in sync to the
new external clocks. However, this switch can be done in software mode.
SIGDET_CH_MODE
Scan All [7:0]
Channels
ADC
Master
Interrupt
Clock INTx
Controller
On-Chip
1/8
Oscillator
Sleep
Mode
The secondary ADC has two main purposes in the PCM186x family. The primary purpose is to act as a low
power signal detection system, to aid with system wakeup from sleep. TI calls this functionality energysense.
Other functionality includes the ability to use any spare analog inputs as generic ADC inputs, for connection to
simple analog sources, such as voltages from control potentiometers. TI calls this functionality controlsense or dc
control.
The secondary ADC is a one-bit, delta-sigma type ADC. The sampling rate is directly connected to the main ADC
audio sampling clocks during ACTIVE functionality. When the device is in sleep state, then the secondary ADC
switches the clock source to an on-chip oscillator (if there are no other clock sources).
In sleep mode, the inputs are all treated as single-ended inputs. Differential inputs are not supported in this mode
because the PGA must be powered up, and thus, consume more power.
In active mode, energysense audio signal detection on any channels other than the primary is not available;
however, other inputs can be read using the secondary ADC channel driven in controlsense mode.
In sleep mode, each input pin can be configured to perform either energysense or controlsense. Both functions
can generate interrupts when their thresholds are crossed. All inputs will be cycled through and converted
continuously, performing either an enerysense or a controlsense function.
In active mode, any dc based controls will either need to be polled continuously by the systems host, or
streamed out continuously in a 6ch TDM mode. In an application, this may mean that the main input is being
converted, while the system battery level, or analog volume control knob position is polled using controlsense.
To make the secondary ADC as flexible as possible in both energysense and controlsense modes, the following
controls and coefficients are available in the register map. More details on each are in the relevant following
sections.
• Coefficients for the secondary ADC low-pass filter
• Coefficients for the secondary ADC high-pass filter
• Reference voltage and interrupt voltage delta for each input in controlsense mode
• Signal loss conditions (time and threshold)
• Signal resume conditions (threshold)
• Interrupt behavior (for example, ping every x ms if host does not clear)
• Scan time for each single ended input
REF_LEVEL
Time
An interrupt is generated
Users set a reference point, and a difference point. If the voltage at the control point crosses the difference point
then an interrupt is driven from the device. This is useful for filtering out noise, as well as reducing the load on
the host processor for controls that tend to be set and forget (such as volume).
The data from the secondary ADC can also be streamed out of the device in TDM form and directly from the I2C
register map. AUXADC_DATA_CTRL (Page.0 0x58) is used to configure and check the status of the DC
detector.
This feature (thresholds and interrupts) is available in both active and sleep modes. In sleep mode, the device
automatically scans through each channel designated a controlsense input. In active mode, the scanning will
need to be done manually by a host microcontroller by modifying the SEC_ADC_INPUT_SEL (Page.0, 0x0A)
register.
Most applications requiring the use of a potentiometer for control can simply use the
SIGDET_DC_LEVEL_CHx_x registers to read the 8-bit value. To enable the SIGDET_DC_LEVEL_CHx_x
registers to work, then the DC_NOLATCH AUXADC_DATA_CTRL (Page.0, 0x58, B[7]) should be set to 1, and
the appropriate input pins should be set to controlsense inputs SIGDET_CH_MODE (Page.0, 0x30)
Direct 16-bit two's compliment reads from the secondary ADC can be done using AUXADC_DATA_CTRL
(Page.0, 0x58) includes a latch function that is used to read the data the secondary ADC on demand in 16-bit
two's compliment format from registers 0x59 and 0x5A.
9.3.11 Energysense
Energysense functionality has been added to the PCM186x to aid with auto-sleep and auto-wakeup for end
equipment systems that are expected to be sold within the European Union. The latest Ecodesign legislation in
Europe has demanded that products consume less than 500 mW in standby. Most off-the-shelf external power
adaptors can consume 300 mW when idling, leaving the system with only 200 mW available. In many systems
that require that almost everything be powered down in sleep mode after there is no more content to be played,
and then to be powered back up when signal enters the system again.
Energysense is designed to work in collaboration with a microcontroller to trigger interrupts notifying the
microcontroller to change the state of the PCM186x, and the rest of the board (for example, amplifiers, and so
on). The PCM186x does not automatically switch between sleep and wake modes.
Energysense is split into two functions: signal loss flag and signal resume flag. Both are available on the
PCM186x software-controlled devices. The PCM1860 and PCM1861 only support signal resume, as shown in
Table 17. By default, the signal resume threshold is set at –57 dBFS. Signal resume (autowakeup) only functions
when the device has been set to sleep.
Threshold
Level
INT
1 ms
In a typical application, the host MCU will note and reset this register multiple times until a system sleep number
is hit. For example, a 5-minute signal loss could be implemented by using the default 1-minute timeout on the
PCM186x, and counting five interrupts. An example is shown in Figure 38.
Time of Loss of Signal (Y minutes) Y minutes Y minutes
1 ms 1 ms 1 ms
Alternatively, the SIGDET_LOSS_TIME (Page.0, 0x33) register in the device can be changed from one minute
(default) to five minutes. This timeout is sample rate dependant. The expected sample rate is 48 kHz, but should
the system be running at 96 kHz, then the time will be halved. (192 kHz = quarter the register setting).
The duration of the interrupt can also be modified using INT_PLS (Page.0 0x62) to be pulses, or to be a sticky
flag, where sticky is defined as the interrupt is on until cleared.
1 ms
There is a balance between lowest frequency detectable, and time on that particular channel. There are three
options in register SIGDET_INT_INTVL (Page.0 0x36):
• 50-Hz detect (160 ms per channel)
• 100-Hz detect (80 ms per channel)
• 200-Hz detect (40 ms per channel)
9.3.11.2.1 Energysense Threshold Levels for Both Signal Loss and Signal Detect
There are two threshold levels used for Energysense, as shown in Figure 40. One is the loss of signal level,
another one is the resume of signal level.
RESUME Level
LOSS Level
As both thresholds are DSP based, their coefficients are stored in virtual coefficient space that is programmed
through the device register map.
For example, to change the resume threshold value to –30 dB (0x040C37):
Write 0x00 0x01 ; # change to register page 1
Write 0x02 0x2D ; # write the memory address of resume threshold
Write 0x04 0x04 ; # bit[23:15]
Write 0x05 0x0C ; # bit[15:8]
Write 0x06 0x37 ; # bit[7:0]
Write 0x01 0x01 ; # execute write operation
DSP #1 DSP #2
Decimation Energysense
Main ADC HPF Loss-of-Signal Flag
Filter
Signal Resume of
Present Flag
Secondary LPF HPF
ADC Control Voltage
Change Flag
SGIDET_CH_Mode[7:0]
To flatten out the response of the secondary ADC, so that all frequencies are detected evenly, write the biquads
shown in Table 18 to the virtual DSP memory, using the techniques discussed in the Programming DSP
Coefficients on Software-Controlled Devices section.
As the DSP coefficients are directly written, no soft ramping is available. Use of I2S receive sacrifices two digital
mic channels due to pin limitations.
Coefficients are written indirectly to virtual memory addresses using the registers on page 1. Details of the
registers are shown in the Register Maps section.
MIX1_CH1L
Ch1[L]
MIX1_CH1R
Mute
ADC Outputs
Ch1[R]
MIX1_CH2L
Ch2[L]
MIX1_CH2R
Ch2[R]
MIX1_I2SL
I2S[L]
SDIN
I2S[R]
Ch1[L]
Ch1[R] Mute
Ch2[L]
Mixer 2
Ch2[R]
I2S[L]
I2S[R]
Ch1[L]
Ch1[R] Mute
Ch2[L]
Mixer 3
Ch2[R]
I2S[L]
I2S[R]
Ch1[L]
Ch1[R] Mute
Ch2[L]
Mixer 4
Ch2[R]
I2S[L]
I2S[R]
Copyright © 2016, Texas Instruments Incorporated
DOUT
BPZ
(Contents)
PCM186x
Enable bits Software-Controlled Devices
Sticky Registers
DC Level Change
Interrupt Polarity
Generator Control
INT
Post PGA Clipping
Detection
DIN Toggle
Status
Clear Bits
Copyright © 2017, Texas Instruments Incorporated
The software-controlled devices have multiple signals that can be mapped to the interrupt outputs. These
include:
• Energysense (default)
• Secondary ADC controlsense interrupt
• Post PGA clip
• DIN toggle
The Interrupt controller has the following features
• The Interrupt sources can be filtered by the enable register (INT_EN).
• The Interrupt flags can be monitored by reading the status register (INT_STAT).
• The interrupt flags can be cleared by writing the status register.
• The polarity of the interrupt signal can be changed between active high, active low and Open Collector (High
Impedance is pulled to GND) (INT_PLS).
• The pulse width of the interrupt signal can be changed between 1ms, 2ms, 3ms and 4ms.
• The interrupt controlled cannot remain asserted, the status bits can be sticky, but the interrupt pin itself has
no hold function.
Using a combination of these features, as well as the interrupt sources, allows the PCM186x to alert a host
microcontroller of an event, using whichever polarity signal required (pull high, pull low, Hi-Z open collector). The
host controller can then communicate with the device to poll the interrupt flag register to find out what happened.
Additional registers can then be read for more details. (For instance, which input triggered an energysense
event.). From a register point of view, there is no difference between INT A, INT B and INT C logic, other than
their signaling (positive, negative or open drain).
BCK
DOUT 1 2 3 22 23 24 1 2 3 22 23 24
MSB LSB MSB LSB
BCK
DOUT 1 2 3 22 23 24 1 2 3 22 23 24 1
MSB LSB MSB LSB
In master mode, only a 50% duty cycle on the output is possible. This configuration is made by setting
TDM_LRCK_MODE (Page.0 0x0B) to 0.
Typically when interfacing to a DSP, only the rising edge on the first bit of data of the frame is required.
While the device is not transmitting data (but still being clocked), the DOUT pin will be Hi-Z (high impedance) to
allow other devices on the bus to transmit their data.
TDM mode is configured using I2S_FMT (Page.0 0x0B), TDM_LRCK_MODE (Page.0 0x0B), TDM_OSEL
(Page.0 0x0C)
The timing limits for the interface signals are defined by the Serial Audio Data Interface Configuration section
with the addition that the BCK period minimum must be at least 1 / (512 × fS) to make sure that data is clocked in
correctly.
The audio format is shown in Figure 46. The 24-bit data can fit up to 10 channels of data in a 256x bitclock
stream; however, the I2C-controlled devices only have two possible I2C addresses. The eight channels of audio
data should be no issue.
xx
LRCK / Frame Sync 50% Duty Cycle (Master Mode)
Example
24-Bit
TDM Mode LRCK / Frame Sync 1BCK or 50% Duty Cycle (Slave Mode)
xx
24-Bit Ch1 data Ch2 data Ch3 data Ch4 data Ch5 data Ch6 data Ch7 data Ch8 data Ch9 data Ch10 data EMPTY Ch1 data
DATA No Gaps (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (24 bits) (16 bits) (24 bits)
xx xx xx
LRCK / Frame Sync 50% Duty Cycle (Master Mode)
Example
32-Bit
Mode LRCK / Frame Sync 1BCK or 50% Duty Cycle (Slave Mode)
xx xx xx
24-Bit Ch1 data 8 Ch2 data 8 Ch3 data 8 Ch4 data 8 Ch5 data 8 Ch6 data 8 Ch7 data 8 Ch8 data 8
DATA 8-Bit Gaps (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits (24 bits) bits
x x x x x
NOTE
TDM mode can only function up to 96 kHz sampling rate when IOVDD is 1.8 V. This is
due to an I/O limitation of 25 MHz at 1.8 V.
NOTE
While the device is driving its interrupt high, any external voltage on the INT pin will be
ignored by the device, until the interrupt event (and pulse) is finished.
9.5 Programming
9.5.1 Control
MSB LSB
NOTE: B8 is used for selection of write or read. Setting = 0 indicates a write, while = 1 indicates a read. Bits 15–9 are used
for register address. Bits 7–0 are used for register data.
MS
MC
MOSI A6 A5 A4 A3 A2 A1 A0 W D7 D6 D5 D4 D3 D2 D1 D0
HI-z
MISO
MS
MC
MOSI A6 A5 A4 A3 A2 A1 A0 R D7 D6 D5 D4 D3 D2 D1 D0
HI-z HI-z
MISO D7 D6 D5 D4 D3 D2 D1 D0
SDA
write operation
Transmitter M M M S M S M S S M
Data Type St slave R/W ACK DATA ACK DATA ACK ------------ ACK Sp
address
read operation
Transmitter M M M S M S M S S M
Data Type St slave R/W ACK DATA ACK DATA ACK ------------ ACK Sp
address
M: Master Device MMM S: Slave Device
St: Start Condition MMM Sp: Stop Conditiion
PowerUp
Basic Device
Configuration
Stable System
Running in Active Mode
Manually (0x0A)
cycle for secondary
No Interrupt
ADC source
(control pot)
Interrupt!
INT_STAT
Energysense Signal Loss ControlSense
(0x61)
Update System
Clear E-Sense Move to Sleep Mode
Refresh Pot Value
Interrupt (0x70)
Reset Ref Level
No Interrupt
Interrupt!
Energysense INT_STAT
ControlSense
Audio Detect (0x61)
Change Primary
Audio Inputs?
WAKE?
WAKE (0x70) No
(0x70)
Yes
Memory Arbiter
Each 24-bit coefficient can be written once every audio sample. This allows a single sample update of a mixer
coefficient, however, biquad coefficients will require multiple audio samples for all of the coefficients to be written.
Under such conditions, the device should be muted until all coefficients are written. Otherwise, the biquad could
become unstable.
In addition, DSP Internal memory can only be written to when the DSP is provided a clock from either the PLL or
an external master clock source. Requesting a WREQ = 1 Register 0x01 of page 0x01 will have no effect, if the
DSP is not currently running. This is of relevance if the system is running as a clock slave, and the clocks stop.
For example, to write to these registers, change the energysense resume threshold value to –30 dB (0x040C37)
1. Write 0x00 0x01 ; # change to register bank 1
2. Write 0x00 0x01 ; # two dummy writes to update the status of the write busy bit
3. Write 0x00 0x01 ; # ^^^^
4. Read Register 0x01 # if value is 0x00 then continue (check if system is still writing/reading). Otherwise, do
another dummy write and check again.
5. Write 0x02 0x2D ; # write the memory address of resume threshold
6. Write 0x04 0x04 ; # bit[23:15]
7. Write 0x05 0x0C ; # bit[15:8]
8. Write 0x06 0x37 ; # bit[7:0]
9. Write 0x01 0x01 ; # execute write operation
See SLAC663 for more details.
The internal DSP coefficient memory space is mapped as shown in Table 24.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
The PCM186x family is extremely flexible, and this flexibility gives rise to a number of design questions that
define the design requirements for a given application.
IN DOUT DOUT
MIC
BCK
PCM186x TMS320C5535 PCM5121 TPA3116
LRCK
SW mix
IN
LINE
BCK
PCM5100 TPA3116
LRCK
USB
IN
MD0 26
Sample Rate and
Master/Slave Selection
MD1 25
MD2 22
MD6 20
INT 19 Interrupt
MS 25
MC 24
SPI
MOSI 23
MISO 22
SCL 24
I2C Bus
SDA 23
8 AVDD
13 DVDD
14 IOVDD
10 …F
2.2 …F
11 LDO
GND
2.2 …F
6 VREF
12 DGND
7 AGND
GND
Copyright © 2017, Texas Instruments Incorporated
PCM186x #1 PCM186x #2
(TDM Master) (TDM Slave)
SDA
SCL
10 µF 10 µF 100
Single-Ended Single-Ended
VINxx VINxx
Audio Source Audio Source
0.01 µF
PCM186x PCM186x
Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated
Figure 60. Analog Input Circuit for Single-Ended Figure 61. Analog Input Circuit With Additional
Input Applications Anti Aliasing Filter for Single-Ended Applications
10 µF 10 µF 47
Differential + Differential +
VINxP VINxP
Audio Source Audio Source
0.01 µF
Differential - Differential -
VINxM VINxM
Audio Source Audio Source
10 µF PCM186x 10 µF 47 PCM186x
Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated
Figure 62. Analog Input Circuit for Differential Figure 63. Differential Input Circuit With
Input Applications Additional AntiAliasing Filter
3.3 V 3.3 V
30 VINR3/VIN3P MD0 26
Stereo Sample Rate or Master/Slave
Left Mic Pair 3 Selection
29 VINL3/VIN4P MD1 25
15 pF 9 XO MD2 24
Figure 64. Stereo Recording Application for PCM186x Hardware-Controlled Devices in Master Mode
±20
±40
Amplitude (dB)
±60
±80
±100
±120
±140
±160
20 200 2000 20000
Frequency (Hz) C013
1.8 V 3.3 V
0.1 …F 10 …F 0.1 …F 10 …F
1 VINL2/VIN1M Mic Bias 5
Stereo
2.2 k 2.2 k
Pair 2
2 VINR2/VIN2M IOVDD 14
10 …F
3 VINL1/VIN1P DVDD 13 3.3 V
Right MIC Stereo
10 …F Pair 1
4 VINR1/VIN2P AVDD 8
0.1 …F 10 …F
30 VINR3/VIN3P MD0 26
Stereo
Left MIC Pair 3
29 VINL3/VIN4P MS/AD 25 I²C Address Select
28 VINR4/VIN3M MC/SCL 24
Stereo
I²C Bus
Pair 4
27 VINL4/VIN4M MOSI/SDA 23
9 XO MISO/GPIO0/DMIN2 22
1.8 V 10 XI GPIO1/INTA/DMIN 21
Interrupt or GPIO
11 LDO GPIO1/INTB/DMCLK 20
2.2 …F
6 VREF GPIO3/INTC 19
2.2 …F
7 AGND DOUT 18
PCM1862 System
12 DGND PCM1863 BCK 17
Processor
PCM1864
15 SCKI PCM1865 LRCK 16
Figure 66. Stereo Recording Application for PCM186x Software-Controlled Devices in Slave PLL Mode
with 1.8-V IOVDD
±20
±40
Amplitude (dB)
±60
±80
±100
±120
±140
±160
20 200 2000 20000
Frequency (Hz) C013
Mic Bias
PCM186x
The PCM186x uses a combination of 3.3-V functional blocks and 1.8-V functional blocks to achieve high analog
performance, combined with high levels of digital integration. As such, the device has three internal power rails.
AVDD provides the analog circuits with a clean 3.3-V rail. DVDD is used for 3.3-V digital clock circuits.
Externally, AVDD and DVDD can be connected together without significant impact to performance. The final rail,
IOVDD, is used for driving the input/output digital circuitry.
The PCM186x integrates an on-chip LDO to convert an external 3.3 V to the 1.8 V required by the digital core.
The LDO input is derived from IOVDD. Power-supply pin descriptions are listed in Table 25.
11.5.2 Lowest Power in Sleep or Energysense Mode (AVDD = DVDD = IOVDD = 3.3 V)
Consumption as low as 14 mW
Clocks must be running during this process
0x00=0x00 //select page0
0x70=0x72 //enter in sleep mode
0x00=0xfd //select page253
0x14=0x10 //change global bias current
0x00=0x00 //select page0
Now stop the clocks
11.5.3 Lower Power in Sleep or Energysense Mode (AVDD = DVDD 3.3 V and IOVDD = 1.8 V)
Consumption as low as 11.15 mW
Clocks must be running during this process
0x00=0x00 //select page0
0x70=0x72 //enter in sleep mode
0x00=0xfd //select page253
0x14=0x10 //change global bias current
0x00=0x00 //select page0
stop the clocks (note: make sure the clock IO is 1.8 V)
1.8V
1.5V
0V
LDO_GOOD
OSC Clock
Counts 16 clocks
OSC GOOD
Digital Reset
Wait
Device REF Clock PLL and
Config stable Detection Clock Divider Wait for the PLL
Config lock
2ms
DOUT
Fade -IN
NOTE
There is no disadvantage in separating the AVDD and DVDD, as the device waits until
both are present before powering up.
AVDD 3.3 V
DVDD
PCM186x
IOVDD
LDO 1.8-V
Output
AVDD 3.3 VA
DVDD 3.3 VD
PCM186x
IOVDD
LDO 1.8-V
Output
11.7.2 3.3-V AVDD, DVDD With 1.8-V IOVDD Example for Lower-Power Applications
The PCM186x also supports interfacing to lower power 1.8-V processors, as shown in Figure 72. In the presence
of an external 1.8 V connected to LDO, the internal LDO that takes DVDD (3.3 V) and converts it to the 1.8-V
core voltage is bypassed. Under such conditions, IOVDD will then be used as the 1.8-V source for the digital
core of the device. In such systems, it is still important to have 3.3 V for DVDD, as specific sections of the digital
core in the device run from 3.3 V.
AVDD 3.3 V
DVDD
PCM186x
IOVDD
LDO 1.8-V
External
Copyright © 2017, Texas Instruments Incorporated
Figure 72. 1.8-V IOVDD With 3.3 V for AVDD and DVDD
11.8 Fade In
This sequence is the final stage of the power up and is illustrated in Figure 73. After the PLL has locked, the
ADC starts running, and the data follows the fade-in sequence according to the following steps:
1. Detect a zero crossing audio input.
2. Increment the volume towards 0 dB with S-shaped volume.
3. Repeat from step 1 until the result is 0 dB. The number of steps from mute to 0 dB is 48 steps.
4. If zero crossing does not occur for 8192 sample times (= time out), change the volume-per-sample time.
0 dB (Unmute)
Mute Event
Time
12 Layout
1 30
2 29
Analog
3 Section 28
4 27
5 26
6 25
7 24
8 23
9 22
10 21
11 Digital 20
Section
12 19
13 18
14 17
15 16
Figure 74. Single Ground With Analog Pins Partitioned to the Top and Digital Pins at the Bottom
13 Register Maps
14.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc..
All other trademarks are the property of their respective owners.
14.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
14.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 2-Apr-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
PCM1860DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1860
& no Sb/Br)
PCM1860DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1860
& no Sb/Br)
PCM1861DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1861
& no Sb/Br)
PCM1861DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1861
& no Sb/Br)
PCM1862DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1862
& no Sb/Br)
PCM1862DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1862
& no Sb/Br)
PCM1863DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1863
& no Sb/Br)
PCM1863DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1863
& no Sb/Br)
PCM1864DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1864
& no Sb/Br)
PCM1864DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1864
& no Sb/Br)
PCM1865DBT ACTIVE TSSOP DBT 30 60 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1865
& no Sb/Br)
PCM1865DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PCM1865
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 2
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