CMOS DESIGN OF PULSE PROCESSING ASIC

FOR RADIATION DETECTION

Vatsala Sharma Kamal Nayanam
Department of Electronice & Communication Department of Electronics & Communication
College of Technology And Engineering, MPUAT Arya College of Engineering & Technology
Udaipur, Rajasthan, India Jaipur, Rajasthan, India
[email protected] [email protected]

Abstract—This paper presents the design & development of II. TECHNOLOGY OVERVIEW
an 36 channel Pulse Processing ASIC using 0.35µm mixed CMOS
technology for radiation detection in high energy physics Today, the prevailing technologies for ASIC designs are
experiments. The benefits of CMOS technology in nuclear bipolar and MOS technologies. Within each of these families
instrumentation has surpassed the expectation due to are various subgroups as illustrated in fig. 1 [3], which shows
advancement of technology, emerging detectors, readouts data a family tree of some of the more widely used silicon
rates and very important radiation hardness with benefits of low integrated-circuit technologies. Since few decades bipolar
power and high density of electronics. The Pulse Processing ASIC technology was dominant for silicon integrated circuit design.
intended to use with silicon pad detectors find application in high Mos technology came into existence after the invention of
energy physics experiments for detecting nuclear radiations and semiconductor MOS structures in the early 1970s. Later in the
converting the charge into electrical signals. The methodology of early 1980s CMOS technology became dominant in the VLSI
design includes circuit design and its optimization using public digital and mixed signal designs for ASICs and prevailing till
domain CAD tool. date.
Keywords— cmos technology; pulse processing asic; The CMOS technology is usually chosen for designing these
preamplifier; pulse shaper; radiation monitoring chips on the merits of low power, high impedance for handling
small charge, ability to build high gain voltage amplifiers,
I. INTRODUCTION capacitors, pass transistors, analog & digital memories. There
is a support of good standard cells and bipolar devices like
High energy physics deals with the study of the smallest diode & transistors are also possible, thus giving opportunity
particles of matter and their interaction. High energy physics for fabricating “detector mount electronics”. The choice of
experiments results in emission of tiny particles which are detector can also be a silicon detector in the form of strip,
invisible. Some of these emitted particles form harmful pixel, silicon drift detector SDD, DPFET, photodiode coupled
radiations which must be measured. To measure the harmful to scintillator, small proportional pad detectors, GEM (gas
radiations present in the working environment, high-energy electron multiplier detector) etc.
physicists use huge detectors with multiple layers of
semiconductor detector systems that wrap around the collision
point within the accelerator [1]. Silicon detector is
accompanied with a read out electronic ASIC which converts
the detected energy in measurable form and give the results.
This ASIC is an upgradation of the already existing 16
channel pulse processing readout ASIC [2] which is 16
channel readout electronics designed in 0.7µm CMOS
technology. The design challenges imposed during the design
of a pulse processing ASIC are signal to noise ratio, gain and
the stability of individual blocks. These design parameters
need to be optimized for individual blocks without
compromising the power consumption. So, the objective is to
identify the architecture of the 36 channel readout ASIC,
optimize it, design its layout and simulate it to find the effect
of silicon extracted parasitic on the output of the channel. This
will find application in high energy physics experiments for
detecting nuclear radiations and converting the charge into
electrical signals. The electronics can be also used for medical Figure 1: Categories of silicon technology [3]
imaging, e.g. mammography and tomography.
 III. ARCHITECTURE OF PULSE PROCESSING UNIT the signal charge generated by the detector is very small, 4-
250 fF, so the signal in the charge sensitive amplifier needs to
be amplified. The small charge signal is easily disturbed by
the statistical fluctuations and noise performance, which can
completely damage the signal detected. To avoid signal
damages, charge sensor must be carefully designed to
minimize electronically generated noise [5]. The equivalent
noise generated by the charge sensitive amplifier can be
Figure 2: Pulse Processing Unit [4]
determined by the input transistor, its bias current and
operating region. The noise in CMOS transistor is given by:
The proposed read out ASIC is basically a pulse processing
unit for detecting and measuring the charged particles Equivalent input noise voltage
produced as a result of collision in any high energy physics
Vn2= 8/3(kT/gm)+Kf/Cox2*W* L*f (1)
experiment. The radiation is first converted to charge with the
help of radiation detectors. The signal from each detector is Equivalent input noise current
then amplified and processed further for storage, which can be
analysed. The function of pulse processing unit is conversion i n2=(SCi)2*V n2 (2)
of charge signal to its equivalent voltage signal, its where s=j, gm=Trans-conductance of the input transistor,
amplification and conversion to digital signals. These digital Kf =Flicker Noise Coefficient, W = width of transistor, L =
signal can be used to display readable digital output. The length of the transistor, C ox =Constant depending on
block diagram of the single pulse processing unit is shown in technology , f= Frequency and Ci=Input capacitance of the
fig. 2 [4]. It includes a Detector, Charge Sensitive Amplifier transistor.
(CSA), Semi Gaussian Pulse Shaper and digital block (track &
hold) as its signal processing blocks. C. Pulse Shaper
A. Silicon Detector The signal-to-noise ratio depends proportionally on the
capacitance i.e. as the capacitance decreases, the signal-to-
The detector is silicon PIN pixel diode in any array of 6X6 noise ratio increases. The schematic design of the pulse shaper
of size 1 cm by 1cm. The detector is A. C. coupled to charge is critical to the effect of electronic noise. The importance of
sensitive amplifier and works in reverse biased conditions. pulse shaper, which is a semi gaussian pulse shaper in this case
The energy generated due to collision between particles (or is to remove the effect of electronic noise. This is achieved as a
photons) is converted to an electrical signal by the sensor and result of improved signal to noise ratio of the signal. The semi
is collected by a high voltage that is applied to the sensor. gaussian pulse shaper is basically a band pass filter. Although
Proportional to this absorbed energy, the electron-hole pairs we are dealing with charge signal pulses, which are the time
are generated by the silicon detector. The signal current can be varying signals. The power spectral density of the signal is
integrated to convert the signal current to signal charge. This distributed in space in the form of frequency spectrum that is
signal charge is again proportional to radiation energy. analyzed by the pulse’s Fourier transform.
Position sensing is an important function of the silicon
detector. The detector consists of multiple layers which results Signal to noise ratio has different frequency spectrum and
in space points which can easily reconstruct particle one can improve it with the help of a filter. The frequency
trajectories. A single detector unit comprises of a silicon pad response of the signal is customised by applying the filter to
detector, charge sensitive preamplifier, pulse shaper, analog to favour the signal. The noise which is present out of band is
digital converter and signal busses are combined in single attenuated. Any Change in the bandwidth results in varying
integrated unit. time response and varying pulse shape, so this process is
called pulse shaping. Generally, one is not concerned with
B. Charge Sensitive Amplifier(CSA) only one pulse rather there is a large no. of pulses
consequently at a very high rate. A large pulse width at such
rates can result in pile up problem which forms pile of
successive pulses. Due to pile up problem the measurement of
the peak amplitude by the system will not be accurate. To
solve the pile up problem the pulse width should be reduced
effectively.

Figure 3: Charge Sensitive Amplifier configuration

Charge sensitive amplifiers are used widely to sense the

collected charge from the radiation detectors. The charge
sensitive amplifiers are required to convert the charge signal to
its equivalent voltage output for high data rate applications in
pulse processing channels. For high resolution, the signal to Figure 4: Semi Gaussian Pulse Shaper [6]
noise ratio plays an important role in charge amplifiers. Since
 A N L G
P /S
M U X

T /H

D. Digital block
Measurement of charge impulses through a multichannel
T /H
detector is quite difficult. It is a major problem in scientific
instrumentation. To measure, the signal charge is converted to A D C
digital form using digitization methods. After the low-noise

...
preamplifier, Direct digitization is the most flexible method to C K
digitize the signal directly in a pulse processing unit. As an
outcome of direct digitization, the waveform is sampled as
digital samples and recorded for measurement. The recorded T /H

series of digital samples are of sufficient precision and

sampling frequency. The succeeding operations can be
performed very expeditiously by modern digital signal S A M P L E

processing hardware. The functional blocks of direct

digitization are as shown in fig. 5 [7].
This is the most flexible circuit for digitization and
requires many fast ADC’s (Analog Digital Circuit). A Figure 6: Track& hold with analog multiplexer [8]
complete digital signal processing for a multi channel detector E. Control blocks associated
system can be however impractical. Since allocating an ADC
for a channel requires high cost and power requirements, Control logic blocks are required for proper biasing of the
usually the events of interest are multiplexed into a more 36 channel digital block, synchronization of the inputs and
limited number of ADCs. An external trigger is quite necessary outputs of the 36 digital channel block and synchronization
to identify and execute the events to be digitized. This can be with other analog blocks associated with the pulse processing
done in two ways, either the channel trigger itself or an unit. The control logic blocks used in the design of 36 digital
auxiliary detector may generate the trigger. The trigger can also channel block are RC out block, Clock out block, Output
be global, which can easily identify the channels which are Switch, Level translator and Bias block.
occupied. Such a trigger signals the event in the detector only
RC out block is generating the clock which defines the
at its occurrence. The system respond to the trigger, as a
period in which the 36 channel digital reads all the channels &
consequence the analog waveform is sampled by the track &
gives the output. Clock out block is required in case when we
hold circuit for later digitization. The multiplexed output
use more than one 36 digital channel blocks. It generates the
waveform of the occupied
P /S channel is sent to ADC directly as
clock for the next 36 digital channel block to make it read the
shown in fig. 6 [8].
A D C next digital channel outputs. Using CMOS technology an
output switch is manufactured by connecting p-channel & n-
channel enhancement transistor in parallel [9]. When control
signal is low both transistors are off. As a result transistors
A D C will form open circuit. On the contrary when control signal is
high both the enhancement transistors are on entering into a
low impedance state. The development of complex circuits
with increased functionality while keeping the constraints is a
...

great challenge. Circuit designers have to fulfil the demanding

power and time-to-market constraints. Such systems mostly
A D C require devices with certain voltage level transitions for
interfacing between various integrated circuits manufactured
by different process technologies [10]. Most common methods
C K
for biasing MOSFET amplifiers in IC’s implement current
mirror circuits.
IV. METHODOLOGY IMPLEMENTED
The methodology used while carrying out the proposed
Figure 5: Direct digitization [7]
work is based on the standard ASIC design flow as shown in
As the name indicates it tracks the input signal from the fig. 7. Definition of the design is the first and most important
semi Gaussian pulse shaper which is an analog signal & hold step for designing a chip. In this step user must define the
its peak amplitude value for a period, therefore the output features and functionalities of the chip as per the requirement.
signal can be stored for measurement & analysis. All the track Speed, size & power consumption are the main considerations
& hold output signals are multiplexed i.e. there are 36 inputs whose required range of values must be specified. Choice of
among which the multiplexer selects the one for which the architecture includes selecting the appropriate design that
control signal is high and produces it as the output at that satisfies the target specifications. The macro level designs as
particular instance of time. well as the micro level designs are taken into consideration.
All the designs are derived from the required features and
 prescribed for the fabrication process. It is very important in
order to ensure a high probability of defect-free fabrication of
all features described in the layout. Physical verification step
is done prior to ensure proper functionality of the circuits
implemented. The layout is verified with the help of two basic
steps DRC (Design Rule Check) and LVS (Layout Versus
Schematic) After the layout is complete, silicon extracted
parasitics are generated using RC extraction tool. Post-layout
simulation is done to extract the physical information of the
design from the routed board. Post-layout simulation is
required to verify compliance with those constraints. If the
outcome of post-layout simulation is not satisfactory, the
circuit should be modified accordingly as per desired
characteristics while considering the performance in presence
of parasitics. The difference between the results of Prelayout
and post layout must not be greater than 15-20%. When the
design passed the logic verification check, it is now ready for
fabrication.
V. LAYOUT & SIMULATION RESULS
The 36 channel digital block that consists of track & hold,
analog multiplexer and control logic blocks is a mixed design
circuit i.e. it consists of both analog as well as digital design
so, the layout is carried out in two different ways for analog
Figure 7: ASIC Design Flow circuits and digital circuits. The layout of digital circuits that
consists of standard gates can be done automatically using
functionalities. Schematic entry is the most commonly used standard automatic layout design tool using the netlist
method of design entry for ASICs and is likely to be very generated from the gate level schematic that is why it is also
useful in terms of providing the maximum information about known as Schematic Driven layout. On the other hand layout
the circuit design in one form or another. The circuit schematic of the analog circuits which are at transistor level is done
shows how all the components are interconnected and the manually using layout editor of standard layout design tool.
connectivity of an ASIC as a whole. This type of design-entry This type of layout is also known as Full Custom layout [11].
process is also known as schematic capture. The layout of dual channel with its associated control blocks is
The description of an ASIC via circuit schematic is shown in fig. 8.
analogous to the description of a building by an architect. The
running simulations are often a hinge to the success in
electronic design. The simulation parameters like signal
integrity, power integrity, electromagnetic compatibility,
analog, or even thermal simulations, disclose information
about the feasibility of the design, margins and limitations.
Next, the pre-layout simulation requires that the circuit
schematic must include all the components of the simulation.
The signal integration includes discrete components, package
models, IC buffer models, trace models, vias and connector
cables. For power integration, this contains power sources,
plane shapes, stitching vias, capacitors and (IC’s) loads. The
goal of this pre-layout simulation step is to develop such
design constraints. Once the design constraints are recognized,
the layout of the schematic can be carried out. This is known
as back-end design or the physical definition of the design. Figure 8: Layout of dual channel with control blocks
The formation of layout is one of the crucial steps in the The digital channels were integrated with Semi Gaussian
design flow, here the circuit geometry and the relative pulse shaper and charge sensitive amplifier to form complete
positioning of each layer is described in detail that is to be 36 channel pulse processing readout at schematic as well as
used in actual fabrication, using a Layout Editor. Physical layout level. Pad Frame for integrated 36 pulse processing
layout design is very crucial to overall circuit performance in channels is designed with 64 bonding pads. Fig. 9 shows the
terms of area, speed and power dissipation. The physical integrated 36 pulse processing channels with the pad frame.
structure determines many of the factors such as
transconductances, parasitic capacitances, etc. above all, the
silicon area that is used to realize a certain function. The
layout design must not violate any of the Layout Design Rules
 VI. CONCLUSION
The research work presented in this paper is concerned with
the design of integrated readout electronic ASIC in 0.35µm
CMOS technology. The design has been carried out starting
from the scratch. It is a mixed signal design that consumes
standard library cells available in the commercial IC design
tool. Design of each block has been presented in detail in this
paper. Maximum 20% difference between the pre layout and
post layout simulation of the dual channel was observed which
is well within the acceptable limit. Front-end and Back-end
Design of complete 36 channel digital block & its
optimization is carried out successfully.
ACKNOWLEDGMENT
This work was successfully carried out at BARC, Mumbai.
I seize upon the opportunity of conferring my profound
regards towards my guides Dr. V. B. Chandratre (Scientific
Officer ‘H’, Electronics Division, BARC) and Mr. Sourav
Mukhopadhyay (Scientific Officer ‘D’, Electronics Division,
BARC) for their dedicated assistance, inspiring guidance, and
Figure 9: 36 channel pulse processing layout with pad frame taking interest in problems, for their concentrate and powerful
Simulation results of Charge sensitive amplifier (CSA), suggestions and simulation criticism throughout the training
Semi Gaussian pulse shaper and the digital block are shown in duration.
fig. 10. It includes input to CSA, output from CSA, output
from shaper, clock input and final digitized output from digital
block.
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