A3979 Datasheet

A3979
Microstepping DMOS Driver with Translator
FEATURES AND BENEFITS DESCRIPTION

▪ ±2.5 A, 35 V output rating The A3979 is a complete microstepping motor driver with
▪ Low RDS(On) outputs: 0.28 Ω source, 0.22 Ω sink, typical built-in translator, designed as a pin-compatible replacement for
▪ Automatic current decay mode detection/selection the successful A3977, with enhanced microstepping (1/16 step)
▪ 3.0 to 5.5 V logic supply voltage range precision. It is designed to operate bipolar stepper motors in
▪ Slow, Fast or Mixed current decay modes full-, half-, quarter-, and sixteenth-step modes, with an output
▪ Home output drive capacity of up to 35 V and ±2.5 A. The A3979 includes a
▪ Synchronous rectification for low power dissipation fixed off-time current regulator that has the ability to operate in
▪ Internal UVLO and thermal shutdown circuitry Slow, Fast, or Mixed decay modes. This current-decay control
▪ Crossover-current protection scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3979. It allows the simple input of one pulse on the STEP
pin to drive the motor one microstep, which can be either a full
step, half, quarter, or sixteenth, depending on the setting of the
PACKAGE: 28 lead TSSOP (suffix LP) with MS1 and MS2 logic inputs. There are no phase-sequence tables,
exposed thermal pad high-frequency control lines, or complex interfaces to program.
The A3979 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
Internal synchronous-rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
UVLO (undervoltage lockout), and crossover-current
protection. Special power-on sequencing is not required.
The A3979 is supplied in a low-profile (height ≤1.20 mm),
Not to scale 28‑pin TSSOP with exposed thermal pad. The package is lead
(Pb) free, with 100% matte tin leadframe plating.
Pinout Diagram
SENSE1 1 28 VBB1
HOME 2 27 SLEEP
DIR 3 26 ENABLE
OUT1A 4 25 OUT1B
PFD 5 PWM 24 CP2
Timer Charge
RC1 6 Pump
23 CP1
Translator
AGND 7 and 22 VCP
REF 8 ÷8 Control 21 PGND
Logic
RC2 9 Reg 20 VREG
VDD 10 19 STEP
OUT2A 11 18 OUT2B
MS2 12 17 RESET
MS1 13 16 SR
SENSE2 14 15 VBB2
agnd and pgnd must be

connected together externally
26184.23F, Rev. 7 November 1, 2019

MCO-0000730
A3979 DMOS Microstepping Driver with Translator
SELECTION GUIDE
Part Number Packing
A3979SLPTR-T 4000 pieces per reel
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
Output Current IOUT ±2.5 A
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
Logic Supply Voltage VDD 7.0 V
tW > 30 ns –0.3 to VDD + 0.3 V
Logic Input Voltage Range VIN
tW < 30 ns –1 to VDD + 1 V
Sense Voltage VSENSE 0.5 V
Reference Voltage VREF VDD V
Operating Ambient Temperature TA Range S –20 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram
0.22 µF
0.22 µF
VREG CP2 CP1

Logic
Supply 2V
VDD UVLO and Charge

Regulator
Fault Pump
Bandgap
VCP
Reference 0.22 µF
Supply Load
Supply
REF
DAC DMOS Full Bridge
VBB1
RC1 >47 µF
STEP 4 OUT1A
RT1 CT1 DIR OUT1B
RESET PWM Timer:

PWM Latch
MS1 Translator Blanking SENSE1
Mixed Decay
MS2 RS1 CS1
Gate
HOME Drive
4
SLEEP
Control DMOS Full Bridge
SR Logic VBB2
ENABLE
OUT2A
VPFD
OUT2B
PFD PWM Timer:
PWM Latch
0.1 µF
RC2 Blanking
Mixed Decay SENSE2
RT2 CT2
DAC RS2 CS2
Exposed Thermal Pad

AGND PGND
(Required)
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ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ.1 Max. Units
Output Drivers
Operating 8 – 35 V
Load Supply Voltage Range VBB
During Sleep mode 0 – 35 V
VOUT = VBB – <1.0 20 µA
Output Leakage Current2 IDSS
VOUT = 0 V – <1.0 –20 µA
Source driver, IOUT = –2.5 A – 0.28 0.335 Ω
Output On Resistance RDS(On)
Sink driver, IOUT = 2.5 A – 0.22 0.265 Ω
Source diode, IF = –2.5 A – – 1.4 V
Body Diode Forward Voltage VF
Sink diode, IF = 2.5 A – – 1.4 V
fPWM < 50 kHz – – 8.0 mA
Motor Supply Current IBB Operating, outputs disabled – – 6.0 mA
Sleep mode – – 20 μA
Control Logic
Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V
fPWM < 50 kHz – – 12 mA
Logic Supply Current IDD Outputs off – – 10 mA
Sleep mode – – 20 μA
VIN(1) 0.7× VDD – – V
Logic Input Voltage
VIN(0) – – 0.3 ×VDD V
IIN(1) VIN = 0.7 × VDD –20 <1.0 20 µA
Logic Input Current2
IIN(0) VIN = 0.3 × VDD –20 <1.0 20 µA
Reference Input Voltage Range VREF Operating 0 – VDD V
Reference Input Current IREF – 0 ±3 μA
VHOME(1) IHOME(1) = –200 µA 0.7× VDD – – V
HOME Output Voltage
VHOME(0) IHOME(0) = 200 µA – – 0.3× VDD V
VPFDH – 0.6 ×VDD – V
Mixed Decay Mode Trip Point
VPFDL – 0.21×VDD – V
VREF = 2 V, Phase Current = 38.27% – – ±10 %
Gain (Gm) Error3 EG VREF = 2 V, Phase Current = 70.71% – – ±5.0 %
VREF = 2 V, Phase Current = 100.00% – – ±5.0 %
STEP Pulse Width tW 1 – – µs
Blank Time tBLANK RT = 56 kΩ, CT = 680 pF 700 950 1200 ns
Fixed Off-Time tOFF RT = 56 kΩ, CT = 680 pF 30 38 46 μs
Crossover Dead Time tDT Synchronous rectification enabled 100 475 800 ns
Continued on the next page...
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ELECTRICAL CHARACTERISTICS, continued at TA = 25°C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ.1 Max. Units
Thermal Shutdown Temperature TJSD – 165 – °C
Thermal Shutdown Hysteresis TJSDHYS – 15 – °C
UVLO Enable Threshold VUVLO Increasing VDD 2.45 2.7 2.95 V
UVLO Hysteresis VUVLOHYS 0.05 0.10 – V
1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
2Negative current is defined as coming out of (sourcing from) the specified device pin.
3E = ( [ V
G REF / 8] – VSENSE ) / ( VREF / 8 ).
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Two-layer PCB with 3.8 in.2 of copper area on each side
32 ºC/W
connected with thermal vias and to device exposed pad
Package Thermal Resistance RθJA
High-K PCB (multilayer with significant copper areas,
28 ºC/W
based on JEDEC standard)
*Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.0
4.5
4.0 H
(R igh-
Power Dissipation, PD (W)
3.5 θJ K
A= PCB
2-
28
3.0 La ºC
ye /W
rP
)
(R CB w
2.5 θJ ith
A = 3
32 .8 in 2
2.0 ºC co
/W pp
) er
per
1.5 sid
e
1.0
0.5
0.0
20 40 60 80 100 120 140 160
Temperature (°C)
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Timing Requirements
(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)
STEP 50%
C D
A B
MS1/MS2/
DIR/RESET
SLEEP
Dwg. WP-042
A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns
B. Minimum Command Active Time
After Step Pulse (Data Hold Time) ............ 200 ns
C. Minimum STEP Pulse Width ...................... 1.0 µs
D. Minimum STEP Low Time ......................... 1.0 µs
E. Maximum Wake-Up Time ......................... 1.0 ms
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table

MS1 MS2 Microstep Resolution Excitation Mode
L L Full Step 2 Phase
H L Half Step 1-2 Phase
L H Quarter Step W1-2 Phase
H H Sixteenth Step 4W1-2 Phase
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FUNCTIONAL DESCRIPTION
Device Operation. The A3979 is a complete micro- Step Input (STEP). A low-to-high transition on the
stepping motor driver with a built-in translator for easy STEP input sequences the translator and advances the motor
operation with minimal control lines. It is designed to one increment. The translator controls the input to the DACs
operate bipolar stepper motors in full-, half-, quarter-, and and the direction of current flow in each winding. The size
sixteenth-step modes. The currents in each of the two output of the increment is determined by the combined state of
full-bridges (all of the N-channel MOSFETs) are regulated inputs MS1 and MS2 (see table 1).
with fixed off-time PMW (pulse width modulated) control
Microstep Select (MS1 and MS2). The input on
circuitry. At each step, the current for each full-bridge is
terminals MS1 and MS2 selects the microstepping format,
set by the value of its external current-sense resistor (RS1
as shown in table 1. Any changes made to these inputs do not
or RS2), a reference voltage (VREF), and the output voltage
take effect until the next rising edge of a step command signal
of its DAC (which in turn is controlled by the output of the
on the STEP input.
translator).
Direction Input (DIR). The state of the DIR input deter-
At power-on or reset, the translator sets the DACs and the
mines the direction of rotation of the motor. Any changes
phase current polarity to the initial Home state (shown in
made to this input does not take effect until the next rising
figures 2 through 5), and the current regulator to Mixed
edge of a step command signal on the STEP input.
decay mode for both phases. When a step command signal
occurs on the STEP input, the translator automatically Internal PWM Current Control. Each full bridge is
sequences the DACs to the next level and current polarity. controlled by a fixed–off-time PWM current-control circuit
(See table 2 for the current-level sequence.) The microstep that limits the load current to a desired value, ITRIP . Initially,
resolution is set by the combined effect of inputs MS1 and a diagonal pair of source and sink MOS outputs are enabled
MS2, as shown in table 1. and current flows through the motor winding and the current
sense resistor, RSx. When the voltage across RSx equals the
While stepping is occurring, if the next output level of the
DAC output voltage, the current-sense comparator resets the
DACs is lower than the immediately preceeding output
PWM latch. The latch then turns off either the source MOS-
level, then the decay mode (Fast, Slow, or Mixed) for the
FETs (when in Slow decay mode) or the sink and source
active full bridge is set by the PFD input. If the next DAC
MOSFETs (when in Fast or Mixed decay mode).
output level is higher than or equal to the preceeding level,
then the decay mode for that full bridge will be Slow decay. The maximum value of current limiting is set by the selec-
This automatic current-decay selection improves microstep- tion of RS and the voltage at the VREF input with a transcon-
ping performance by reducing the distortion of the current ductance function approximated by:
waveform due to back EMF of the motor.
ITRIPmax = VREF/8RS
RESET Input ( R̄¯
Ē¯
S̄¯
Ē¯
T̄¯ ). The R̄¯Ē¯S̄¯Ē¯T̄¯ input (active The DAC output reduces the VREF output to the cur-
low) sets the translator to a predefined Home state (shown rent-sense comparator in precise steps (see table 2 for
in figures 2 through 5), and turns off all of the DMOS out- % ITRIPmax at each step).
puts. The HOME output goes low and all STEP inputs are
ITRIP = (% ITRIPmax/100) ITRIPmax
ignored until the R̄¯Ē
¯S̄¯Ē
¯T̄¯ input is set to high.
It is critical that the maximum rating (0.5 V) on either the
Home Output (HOME). The HOME output is a logic SENSE1 and SENSE2 pins is not exceeded. For full step-
output indicator of the initial state of the translator. At ping, VREF can be applied up to the maximum rating of VDD
power-on, the translator is reset to the Home state (shown in because the peak sense value is 0.707 × VREF / 8. In all other
figures 2 through 5). modes, VREF should not exceed 4 V.
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Fixed Off-Time. The internal PWM current-control cir- age on VCP, the outputs of the device are disabled until the
cuitry uses a one-shot timer to control the duration of time fault condition is removed.
that the MOSFETs remain off. The one shot off-time, tOFF,
At power up, and in the event of low VDD, the undervoltage
is determined by the selection of external resistors, RTx , and
lockout (UVLO) circuit disables the drivers and resets the
capacitors, CTx , connected from each RCx timing terminal to
translator to the Home state.
ground. The off-time, over a range of values of CT = 470 pF
to 1500 pF and RT = 12 kΩ to 100 kΩ is approximated by:
Sleep Mode ( S̄¯
L̄¯
Ē¯
Ē¯
P̄¯ ). This active-low control input
tOFF = RTCT is used to minimize power consumption when the motor is
not in use. It disables much of the internal circuitry includ-
RC Blanking. In addition to the fixed off-time of the
ing the output DMOS FETs, current regulator, and charge
PWM control circuit, the CTx component sets the compara-
pump. Setting this to a logic high allows normal operation,
tor blanking time. This function blanks the output of the
as well as start-up (at which time the A3979 drives the
current-sense comparators when the outputs are switched
motor to the Home microstep position). When bringing the
by the internal current-control circuitry. The comparator
device out of Sleep mode, in order to allow the charge pump
outputs are blanked to prevent false overcurrent detection
(gate drive) to stabilize, provide a delay of 1 ms before issu-
due to reverse recovery currents of the clamp diodes, or to
ing a step command signal on the STEP input.
switching transients related to the capacitance of the load.
The blank time tBLANK can be approximated by: Percent Fast Decay Input (PFD). When a STEP
tBLANK = 1400CT input signal commands a lower output current than the
previous step, it switches the output current decay to either
Charge Pump (CP1 and CP2). The charge pump is Slow, Fast, or Mixed decay mode, depending on the voltage
used to generate a gate supply greater than that of VBB for level at the PFD input. If the voltage at the PFD input is
driving the source-side DMOS gates. A 0.22 µF ceramic greater than 0.6 × VDD , then Slow decay mode is selected.
capacitor should be connected between CP1 and CP2 for If the voltage on the PFD input is less than 0.21 × VDD , then
pumping purposes. In addition, a 0.22 µF ceramic capacitor Fast decay mode is selected. Mixed decay mode is selected
is required between VCP and VBB, to act as a reservoir for when VPFD is between these two levels, as described in
operating the high‑side DMOS gates. the next section. This terminal should be decoupled with a
VREG (VREG). This internally-generated voltage is used to 0.1 μF capacitor.
operate the sink-side DMOS outputs. The VREG pin must Mixed Decay Operation. If the voltage on the PFD input
be decoupled with a 0.22 µF capacitor to ground. VREG is is between 0.6 × VDD and 0.21 × VDD , the bridge operates
internally monitored, and in the case of a fault condition, the in Mixed decay mode, as determined by the step sequence
DMOS outputs of the device are disabled. (shown in figures 2 through 5). As the trip point is reached,
the device goes into Fast decay mode until the voltage
Enable Input ( Ē¯
N̄¯
Ā¯
B̄¯
L̄¯
Ē¯ ). This active-low input
enables all of the DMOS outputs. When set to a logic high, on the RCx terminal decays to the same level as voltage
the outputs are disabled. The inputs to the translator (STEP, applied to the PFD terminal. The time that the device oper-
DIR, MS1, and MS2), all remain active, independent of the ates in fast decay is approximated by:
Ē¯N̄
¯Ā

¯
B̄¯L̄¯
Ē¯ input state. tFD = RTCTln (0.6VDD/VPFD)
Shutdown. During normal operation, in the event of a After this Fast decay portion, the device switches to Slow
fault, such as overtemperature (excess TJ) or an undervolt- decay mode for the remainder of the fixed off-time period.
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Synchronous Rectification. When a PWM off- • Active Mode. When the SR input is logic low, Active
cycle is triggered by an internal fixed–off-time cycle, load mode is enabled and synchronous rectification can occur.
current recirculates according to the decay mode selected This mode prevents reversal of the load current by turning
off synchronous rectification when a zero current level is
by the control logic. The A3979 synchronous rectification
detected. This prevents the motor winding from conduct-
feature turns on the appropriate MOSFETs during the decay ing in the reverse direction.
of the current, and effectively shorts out the body diodes
• Disabled Mode. When the SR input is logic high, syn-
with the low RDS(On) driver. This reduces power dissipation chronous rectification is disabled. This mode is typi-
significantly and eliminates the need for external Schottky cally used when external diodes are required to transfer
diodes for most applications. The synchronous rectification power dissipation from the A3979 package to the external
can be set to either Active mode or Disabled mode: diodes.
APPLICATIONS INFORMATION
Layout. The printed circuit board on which the device is Current Sensing. To minimize inaccuracies caused by
mounted should have a heavy ground plane. For optimum ground-trace IR drops in sensing the output current level,
electrical and thermal performance, the A3979 should be the current-sense resistors, RSx, should have an independent
soldered directly onto the board. ground return to the star ground of the device. This path
The load supply terminals, VBBx, should be decoupled with should be as short as possible.
an electrolytic capacitor (>47 µF is recommended), placed
as close to the device as possible. For low-value sense resistors, the IR drops in the printed cir-
cuit board sense resistor traces can be significant and should
To avoid problems due to capacitive coupling of the high be taken into account.
dv / dt switching transients, route the bridge-output traces
away from the sensitive logic-input traces. The use of sockets should be avoided as they can introduce
Always drive the logic inputs with a low source impedance variation in RSx due to their contact resistance.
to increase noise immunity.
Allegro MicroSystems recommends a value of RS given by
Grounding. The AGND (analog ground) terminal and the
PGND (power ground) terminal must be connected together RS = 0.5/ITRIPmax
externally.
Thermal Protection. This internal circuitry turns off
All ground lines should be connected together and be as all drivers when the junction temperature reaches 165°C,
short as possible. A star ground system, centered under the typical. It is intended only to protect the device from failures
device, is an optimum design. due to excessive junction temperatures and should not imply
The copper ground plane located under the exposed thermal that output short circuits are permitted. Thermal shutdown
pad is typically used as the star ground. has a hysteresis of approximately 15°C.
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STEP Input STEP Input
HOME Output HOME Output

100.00 100.00
70.71 70.71
Slow Slow Slow
Phase 1 Slow Mixed Mixed Mixed
Phase 1
IOUT1A 0.00
IOUT1A 0.00
Direction = H Direction = H
Home Microstep Position


(%) (%)
–70.71 –70.71
–100.00 –100.00
100.00 100.00
70.71 70.71
Slow Slow Slow Slow
Phase 2 Phase 2 Mixed Mixed Mixed
IOUT2A IOUT2A
0.00 0.00
Direction = H Direction = H
(%) Slow (%)
–70.71 –70.71
–100.00 –100.00
Figure 2. Decay Mode for Full-Step Increments Figure 3. Decay Modes for Half-Step Increments
STEP Input
HOME Output
100.00
92.39
70.71
38.27
Phase 1
Slow Mixed Slow Mixed Slow
IOUT1A
0.00
Direction = H
(%) –38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
38.27 Slow
Phase 2
Mixed Slow Mixed Slow Mixed
IOUT2A
0.00
Direction = H
(%) –38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments
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STEP Input
HOME Output
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Phase 1 9.8
IOUT1A Slow Mixed Slow Mixed
0.00
Direction = H –9.8
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
Slow
Phase 2 9.8
IOUT2A Mixed Slow Mixed Slow
0.00
Direction = H
–9.8
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
Figure 5. Decay Modes for Sixteenth-Step Increments
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Table 2. Step Sequencing Settings

Home microstep position at Step Angle 45º; DIR = H; 360° = 4 full steps
Phase 1 Phase 2 Phase 1 Phase 2

Full Half 1/4 1/16 Current Current Step Full Half 1/4 1/16 Current Current Step
Step Step Step Step [% ItripMax] [% ItripMax] Angle Step Step Step Step [% ItripMax] [% ItripMax] Angle
# # # # (%) (%) (º) # # # # (%) (%) (º)
1 1 1 100.00 0.00 0.0 5 9 33 –100.00 0.00 180.0
2 99.52 9.80 5.6 34 –99.52 –9.80 185.6
3 98.08 19.51 11.3 35 –98.08 –19.51 191.3
4 95.69 29.03 16.9 36 –95.69 –29.03 196.9
2 5 92.39 38.27 22.5 10 37 –92.39 –38.27 202.5
6 88.19 47.14 28.1 38 –88.19 –47.14 208.1
7 83.15 55.56 33.8 39 –83.15 –55.56 213.8
8 77.30 63.44 39.4 40 –77.30 –63.44 219.4
1 2 3 9 70.71 70.71 45.0 3 6 11 41 –70.71 –70.71 225.0
10 63.44 77.30 50.6 42 –63.44 –77.30 230.6
11 55.56 83.15 56.3 43 –55.56 –83.15 236.3
12 47.14 88.19 61.9 44 –47.14 –88.19 241.9
4 13 38.27 92.39 67.5 12 45 –38.27 –92.39 247.5
14 29.03 95.69 73.1 46 –29.03 –95.69 253.1
15 19.51 98.08 78.8 47 –19.51 –98.08 258.8
16 9.80 99.52 84.4 48 –9.80 –99.52 264.4
3 5 17 0.00 100.00 90.0 7 13 49 0.00 –100.00 270.0
18 –9.80 99.52 95.6 50 9.80 –99.52 275.6
19 –19.51 98.08 101.3 51 19.51 –98.08 281.3
20 –29.03 95.69 106.9 52 29.03 –95.69 286.9
6 21 –38.27 92.39 112.5 14 53 38.27 –92.39 292.5
22 –47.14 88.19 118.1 54 47.14 –88.19 298.1
23 –55.56 83.15 123.8 55 55.56 –83.15 303.8
24 –63.44 77.30 129.4 56 63.44 –77.30 309.4
2 4 7 25 –70.71 70.71 135.0 4 8 15 57 70.71 –70.71 315.0
26 –77.30 63.44 140.6 58 77.30 –63.44 320.6
27 –83.15 55.56 146.3 59 83.15 –55.56 326.3
28 –88.19 47.14 151.9 60 88.19 –47.14 331.9
8 29 –92.39 38.27 157.5 16 61 92.39 –38.27 337.5
30 –95.69 29.03 163.1 62 95.69 –29.03 343.1
31 –98.08 19.51 168.8 63 98.08 –19.51 348.8
32 –99.52 9.80 174.4 64 99.52 –9.80 354.4
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Terminal List Table
Number Name Description

1 SENSE1 Sense resistor for Bridge 1
2 HOME Logic Output
3 DIR Logic input
4 OUT1A Output A for Bridge 1
5 PFD Mixed decay setting
6 RC1 Analog input for fixed off-time for Bridge 1
7 AGND Analog Ground
8 REF Current trip reference voltage input
9 RC2 Analog input for fixed off-time for Bridge 2
10 VDD Logic supply
11 OUT2A Output A for Bridge 2
12 MS2 Logic input
13 MS1 Logic input
14 SENSE2 Sense resistor for Bridge 2
15 VBB2 Load supply for Bridge 2
16 SR Logic input
17 R̄¯ Ē¯ S̄¯ Ē¯ T̄¯ Logic input
18 OUT2B Output B for Bridge 2
19 STEP Logic input
20 VREG Regulator decoupling
21 PGND Power Ground
22 VCP Reservoir capacitor
23 CP1 Charge pump capacitor 1
24 CP2 Charge pump capacitor 2
25 1OUT1B Output B for Bridge 1
26 Ē¯ N̄¯ Ā¯ B̄¯ L̄¯ Ē¯ Logic input
27 S̄¯ L̄¯ Ē¯ Ē¯ P̄¯ Logic input
28 VBB1 Load supply for Bridge 1
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LP Package, 28-pin TSSOP
9.70 ±0.10 0.45

0.65
4° ±4 28
28
+0.05 1.65
0.15 –0.06
3.00 4.40 ±0.10 6.40 ±0.20 3.00 6.10

0.60 ±0.15
A
(1.00)
1 2
5.00
0.25 1 2
5.00
28X C SEATING PLANE
SEATING
0.10 C PLANE GAUGE PLANE C PCB Layout Reference View
+0.05 1.20 MAX
0.25 –0.06 0.65
0.10 MAX
For reference only

(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
14
955 Perimeter Road
REVISION HISTORY
Number Date Description
6 (was Rev. F) June 21, 2013 Update decay charts
7 November 1, 2019 Minor editorial updates
Copyright 2019, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

15
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A3979 Datasheet

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A3979

Microstepping DMOS Driver with Translator

FEATURES AND BENEFITS DESCRIPTION

agnd and pgnd must be

26184.23F, Rev. 7 November 1, 2019

ABSOLUTE MAXIMUM RATINGS

Functional Block Diagram

VREG CP2 CP1

VDD UVLO and Charge

RT1 CT1 DIR OUT1B

RESET PWM Timer:

Exposed Thermal Pad

Continued on the next page...

Maximum Power Dissipation, PD(max)

A. Minimum Command Active Time

Figure 1. Logic Interface Timing Diagram

Table 1. Microstep Resolution Truth Table

STEP Input STEP Input

HOME Output HOME Output

Home Microstep Position

Home Microstep Position

Home Microstep Position

Figure 4. Decay Modes for Quarter-Step Increments

Figure 5. Decay Modes for Sixteenth-Step Increments

Table 2. Step Sequencing Settings

Phase 1 Phase 2 Phase 1 Phase 2

Terminal List Table

Number Name Description

LP Package, 28-pin TSSOP

9.70 ±0.10 0.45

3.00 4.40 ±0.10 6.40 ±0.20 3.00 6.10

For reference only

Copyright 2019, Allegro MicroSystems.

For the latest version of this document, visit our website:

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