Notes On WL Ratio
Notes On WL Ratio
1. The transconductance (gm) increases generally but can start to limit at very low current density.
This would be for analog circuits. A more relevant term in digital circuits is Idsat which also
increases. That is the drive strength increases. Capacitance terms also increase.
2. Resistance of MOSFET would decrease.
Ion and Ioff both will increase. Would be making the MOSFET both faster in On mode and noisy
in OFF mode.
Capacitance would also increase that would result in increase in delay.
Due to increase in Ioff, lots of power loss is expected and thus the system made of v. large W/L
would also have lots of power loss.
𝐾𝑛′ = 𝜇𝑛 𝐶𝑜𝑥
μn is the mobility of the electrons in the inversion layer and Cox is the oxide capacitance per unit area.
According to Neamen the 𝐾𝑛′ parameter is called the "process conduction parameter" and is considered to
𝑊
be a constant for a fabrication technology. Therefore the ratio is the transistor design variable.
𝐿
Neamen goes on to say that the design variable is used to design MOSFETS to produce specific current-
voltage characteristics in MOSFET circuits.
Note: W refers to width and L to length. It relates to the geometry of the semiconductor.
Just as note: usually in integrated circuits, L is limited by the technology (as small as possible) and
the conductivity is increased with bigger W; in this way, though, also the gate capacitance is
increased, so often it doesn't bring any advantage.
First Opinion
a. The gate length specified for a MOSFET technology means the MINIMUM length. In
design it can be larger than the minimum length.
b. The W/L ratio is linked to the trans-conductance and the current capability, together with
the multiplicity factor m. A higher w/l ratio increases the current gain and subsequently a
higher current for a given Vg. The same is for a higher m that means m·W/L.
c. In practice, for the gain stages are useful large transistors, i.e. large W/L ratios or/and
large m. As example, the differential input stage of OpAmps needs high gain. However,
the good matching of the input differential stage has to be considered as well.
d. In the current mirrors, a higher transistor gate length is beneficial, for a better matching
of the mirror’s currents. You can play with these parameters in simulations to observe the
impact of the length on the mirrors current matching.
e. In general, a larger transistor ensures a better matching because it minimizes the edge
effects, but this is paid with a significant area price.
Second Opinion
You need to understand the geometrical sensitivity of your circuit. So if it is a biasing circuit, i.e.
current mirror, or a current source that needs to match to another source on the die, then you
need to increase the length and make the width a nominal say 5um and then use multiple legs to
accomplish the sizing. Make sure all transistors that are to match have the same orientation and
layout and only differ in the multiplier. Minimum length and width devices have poor matching!