Model Question Paper with solution

Class: B.E.(ECT) Subject: Advanced Embedded Systems Design

Time: Three Hours Max Marks: 80

N.B: i) Question No.1 from section A and Question No.6 from section B are compulsory.

ii) From remaining, solve any two questions from each section.

Section A

Q1 a)Define & Classify Embedded Systems. 05

Definition: An Embedded System is one that has computer hardware with software embedded
in it as one of its important components.

CLASSIFICATIONS OF EMBEDDED SYSTEM

1. Small Scale Embedded System

2. Medium Scale Embedded System
3. Sophisticated Embedded System

SMALL SCALE EMBEDDED SYSTEM

• Single 8 bit or 16bit Microcontroller.
• Little hardware and software complexity.
• They May even be battery operated.
• Usually “C” is used for developing these system.
• The need to limit power dissipation when system is running continuously.
• Programming tools: Editor, Assembler and Cross Assembler

MEDIUM SCALE EMBEDDED SYSTEM

• Single or few 16 or 32 bit microcontrollers or Digital Signal Processors (DSP) or Reduced
Instructions Set Computers (RISC).
• Both hardware and software complexity.
• Programming tools: RTOS, Source code Engineering Tool, Simulator, Debugger and
Integrated Development Environment (IDE).

SOPHISTICATED EMBEDDED SYSTEM

• Enormous hardware and software complexity
• Which may need scalable processor or configurable processor and programming logic
arrays.
• Constrained by the processing speed available in their hardware units.
Q1 b) Give the outline of the following Embedded Systems. 05
 1. Software defined radio 2.Navigation system

Q2 a) Compare General purpose computer system with Embedded system 07

Q2. b) List out different categories for core of the Embedded System.Explian any one. 08
Q3 a). Explain the Features of ARM processor 05

Features of ARM processor.

• 32 bit RISC processor. „
• High Code density.( Less memory) „
• Hardware Debug Technology. „
• Load store architecture. „
• Variable cycle execution for certain instructions. „
• Inline barrel shifter. „
• Thumb 16 bit instruction set. „
• Conditional execution : An instruction is only executed when a specific condition has
been satisfied
• Enhanced Instructions: DSP „
• Orthogonal instruction Set „
• Large 16 x 32 register file. „
• Fixed op code width of 32 bits to ease decoding and pipelining. „
• Powerful indexed addressing modes. „
• Simple, but fast, 2-priority-level interrupt subsystem with switched register banks

Q3 b) With the help of neat diagram explain the ARM7 core architecture. 10

A programmer can think of an ARM core as functional units connected by data buses, as
shown in Figure where, the arrows represent the flow of data, the lines represent the buses,
and the boxes represent either an operation unit or a storage area. The figure shows not only
the flow of data but also the abstract components that make up an ARM core. Data enters the
processor core through the Data bus. The data may be a ninstruction to execute or a data item.
Figure shows a Von Neumann implementation of the ARM— data items and instructions share
the same bus. In contrast, Harvard implementations of the ARM use two different buses. The
instruction decoder translates instructions before they are executed. Each instruction executed
belongs to a particular instruction set.

The ARM processor, like all RISC processors, uses a load-store architecture. This means it has
two instruction types for transferring data in and out of the processor: load instructions copy
data from memory to registers in the core, and conversely the store instructions copy data from
registers to memory. There are no data processing instructions that directly manipulate data in
memory. Thus, data processing is carried out solely in registers. Data items are placed in the
register file—a storage bank made up of 32-bit registers. Since the ARM core is a 32-bit
processor, most instructions treat the registers as holding signedorunsigned32-bitvalues. use
the ALU to generate an address to be held in the address register and broadcast on the Address
bus.
A unique and powerful feature of the ARM processor is the ability to shift the32-bit binary
pattern in one of the source registers left or right or rotate by a specific number of positions
before it enters the ALU by Barrel shifter

The sign extend hardware convert ssigned8-bit and 16-bit numbers to 32-bit values as they are
read from memory and placed in a register. ARM instructions typically have two source
registers, Rn and Rm, and a single result or destination register, Rd. Source operands are read
from the register file using the internal buses A and B, respectively. The ALU (arithmetic logic
unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A and B
buses and computes a result. Data processing instructions write the result in Rd directly to the
register file. Load and store instructions

Q4 a) Explain the ARM core instructions for 10

a.) Arithmetic Group b.) Logical Group

ARM core instructions for Arithmetic Group:

• ADD operand1 + operand2

• ADC operand1 + operand2 + carry

• SUB operand1 - operand2

• SBC operand1 - operand2 + carry -1

• RSB operand2 - operand1

 • RSC operand2 - operand1 + carry - 1

* Syntax:

• <Operation>{<cond>}{S} Rd, Rn, Operand2

* Examples

• ADD r0, r1, r2

• SUBGT r3, r3, #1

• RSBLES r4, r5, #5

* ARM core instructions for Logical Group:

• AND operand1 AND operand2

• EOR operand1 EOR operand2

• ORR operand1 OR operand2

• BIC operand1 AND NOT operand2 [ie bit clear]

* Syntax:

• <Operation>{<cond>}{S} Rd, Rn, Operand2

* Examples:

• AND r0, r1, r2

• BICEQ r2, r3, #7

• EORS r1,r3,r0

Q4 b) Write a assembly language program for ARM core to add two 32 bit numbers stored in
memory & save the result in memory . 05

ADDITION OF TWO 32 BIT NUMBERS

Source & Destination: MEMORY LOCATIONS

Let the 32 bit operands be :

[0X40000000] = 0X12345678
[0X40000018] = 0X56789ABC
and
Result: [0X40000030] = 0X68ACF134

PROGRAM:
 AREA |.text|, CODE, READONLY

EXPORT _main

_main b start

start
ldr r1,=0x40000000 ;LOAD r1 WITH 0X40000000.

ldr r2,=0x40000018 ;LOAD r2 WITH 0X40000018.

ldr r3,=0x40000030 ;LOAD r3 WITH 0X40000030.

ldr r4,[r1] ;LOAD r4 WITH MEMORY OCATION

; CONTENTS WHOSE ADDRESS IS IN r1.

ldr r5,[r2] ;LOAD r5 WITH MEMORY LOCATION

: CONTENTS WHOSE ADDRESS IS IN r2.

add r6,r5,r4 ;ADD r4, r5 CONTENTS AND STORE THE

; RESULT IN r6

str r6,[r3] ;STORE r6 CONTENTS IN MEMEMORY

; LOCATION WHOSE ADDSRESS IS IN r3.
lp b lp ;BE IN THE INFINITE LOOP

END

Q5. Write sfort notes on 5+5+5

Q5 1 Load / Store Single register Instructions in ARM processor

* The ARM is a Load / Store Architecture:

• Does not support memory to memory data processing operations.

• Must move data values into registers before using them.

* This might sound inefficient, but in practice isn’t:

• Load data values from memory into registers.

• Process data in registers using a number of data processing instructions which

are not slowed down by memory access.
 • Store results from registers out to memory.

* The ARM has three sets of instructions which interact with main memory. These are:

• Single register data transfer (LDR / STR).

• Block data transfer (LDM/STM).

• Single Data Swap (SWP).

* The basic load and store instructions are:

• Load and Store Word or Byte

* LDR / STR / LDRB / STRB

* All of these instructions can be conditionally executed by inserting the appropriate

condition code after STR / LDR.

* Syntax:

• <LDR|STR>{<cond>}{<size>} Rd, <address>

* The memory location to be accessed is held in a base register

• STR r0, [r1] ; Store contents of r0 to location pointed to

; by contents of r1.

• LDR r2, [r1] ; Load r2 with contents of memory location

; pointed to by contents of r1.

Q5 2 ) Three stage pipeline employed ARM7 core.

The 3-stage ARM pipeline

A pipeline is the mechanism a RISC processor uses to execute instructions.Using a pipeline
speeds up execution by fetching the next instruction while other instructions are being decoded
and executed. One way to view the pipeline is to think of it as an automobile assembly line,
with each stage carrying out a particular task to manufacture the vehicle

A simple 3-stage pipeline consists of fetch, decode and execute.

fetch - to fetch the instruction from the code memory indicated by the program counter.
decode - interpret the opcode from the instruction.
execute - based on the opcode, perform required operation on the operand(s).

--------------------------------------------------------------
Time Fetch Decode Execute
--------------------------------------------------------------
time 0: Fetch 1 ---- -- --
time 1: Fetch 2 Decode 1 ----
time 2: Fetch 3 Decode 2 Execute 1
time 3: Fetch 4 Decode 3 Execute 2
---------------------------------------------------------------

3-stage pipeline working

The pipeline allows the core to execute an instruction every cycle. As the pipeline length
increases, the amount of work done at each stage is reduced, which allows the processor to
attain a higher operating frequency. This in turn increases the performance. The system latency
also increases because it takes more cycles to fill the peline before the core can execute an
instruction.The increased pipeline length also means there can be data dependency between
certain stages. You can write code to reduce this dependency by using instruction scheduling

Q5 3 ) Thumb state

ARM cores start up, after reset, executing ARM instructions. The normal way they switch to
execute Thumb instructions is by executing a Branch and Exchange instruction . This instruction
sets the T bit if the bottom bit of the specified register was set, and switches the program
counter to the address given in the remainder of the register. Note that since the instruction
causes a branch it flushes the instruction pipeline, removing any ambiguity over the inter-
pretation of any instructions already in the pipeline (they are simply not executed).

Versions 4T and 4TxM of the ARM architecture define a 16-bit instruction set called the Thumb
instruction set. The functionality of the Thumb instruction set is a subset of the functionality of
the 32-bit ARM instruction set.
Thumb state
• Imposes some limitations on register access
• Does not allow conditional execution except for branch instructions
• Does not allow access to the barrel shifter except as a separate instruction.
• Uptown 70% code size reduction
• 40% more instructions.
• 45% faster code with 16-bit memory
• Preferred If cost and power consumption are critical:
• Requires about 30% less external memory
• Many Thumb data processing instructions use a 2-address format (the destination
register is the same as one of the source registers).

Section-B
Q 6 a) How ARM7 differs from cortexM3 ? 5
The ARM Cortex-M3 is an implementation of the ARM7v architecture, the latest evolution of ARM’s
embedded cores. It is a Harvard architecture, using separate buses for instructions and data (rather than
a von Neumann architecture, where data and instructions share a bus. The Cortex-M3 is aimed by ARM
at the deeply embedded market. It is designed to be low cost and low power and to provide good
performance for the cost and power.

ARM sees it as particularly suited to automotive and wireless communications applications. As with all
ARM designs, the company licenses the design to manufacturers that produce their own
implementation

Integrated with the core are system peripherals, such as the interrupt controller, bus matrix, and debug
functionality, which would normally be added by the microcontroller implementer.

It has an integrated sleep mode and the option of an integral eight-region Memory Protection Unit. It is
designed for the THUMB-2 Instruction set .

While the ARM7 implements both the ARM and Thumb instruction sets, the Cortex-M3 supports only
the Thumb-2 instruction set.
The Thumb-2 instruction set does not require the system to switch state between Thumb and ARM
code, which reduces performance with earlier processors.
Thumb-2 is designed specifically to implement C and includes an If/Then construct (predicating
conditional execution of the next four instructions), hardware division, and native bitfield manipulation.
Thumb-2 allows designers to maintained and modified applications at the level of the C code; it includes
functionality that would normally require calling assembler level code (Luminary Micro claims that there
is no need ever to drop into assembly language). These advantages add up to easier implementation and
possibly faster time to market for new products.
Another innovation on the Cortex-M3 is the Nested Vector Interrupt Controller (NVIC). Unlike external
interrupt controllers, as are used in ARM7TDMI implementations, this is integrated into the Cortex M3
core and can be configured by the silicon implementer to provide from a basic 32 physical interrupts
with eight levels of pre-emption priority up to 240 physical interrupts and 256 levels of priority.
The design is deterministic with low latency, making it particularly applicable to automotive applications.
The NVIC uses a stack-based exception model. Program counter, program status register, link register,
and general-purpose registers are all pushed on to the stack to handle the interrupt, and once interrupt
processing is completed, the registers are restored.
Stack handling is in hardware, so there is no longer a need to create assembler wrappers for stack
manipulation for interrupt service routines.
Interrupts can be nested. An interrupt can exert a higher priority for earlier servicing, and priority levels
can be changed during run time.

The memory protection unit is an implementation option. When implemented it allows areas of
memory to be associated with specific processes in the application with rules governing access by other
processes. For example, some memory can be totally blocked for all other processes, while other areas
can be read-only for specific other processes. Another rule could halt execution if a process attempts to
enter a memory area. This provides a significant improvement in reliability, particularly in real- time
code.

Q6 b) Explain the operating system architecture with the help of a neat diagram. 5
Q7 a.) Explain the Watch Dog Timer in ARM processor based LPC 2148 microcontroller. 08

Watch Dog Timer:

Consider a pet dog. If you feed the dog at regular intervals, it will be happy. What happens if
you do not feed it? Well, it will start barking and might even bite you. Similarly, if you do not
feed the watchdog at regular intervals before its timeout, it will cause a system reset.

Registers associated with WDT

1. WDMOD (Watchdog Mode Register)

It is an 8-bit read-write register used to set Mode of the WDT

2. WDTC (Watchdog Timer Constant Register)

Every time a sequence feed occurs, the WDTC content is loaded into the watchdog timer.

3. WDFEED (Watchdog Feed Register)

It is an 8-bit write only register. Writing a 0xAA followed by 0x55 to this register will reload the
watchdog timer with the WDTC value. This operation will also start the watchdog if it is enabled
via the WDMOD register.

4. WDTV (Watchdog Timer Value Register)

It is a 32-bit read only register.It is used to read the current value of watchdog timer.

Registers associated with WDT Internal operation

Steps to use the Watchdog

• Set the watchdog timer constant reload value in the WDTC register

• Select the mode using the WDMOD register

• Start the watchdog by feeding it with 0xAA followed by 0x55 in the WDFEED register

• Make sure to feed the watchdog again before the timer counter underflows in order to
prevent reset/interrupt
Q7. b.)Explain the operating modes in cortex m3. 07
 Operating modes:

Q8 a) Explain the GPIO ports in LPC 2148 ARM7 based controller. 10

LPC2148 has two IO ports namely PORT0 (P0) and PORT1 (P1). These two IO ports are of 32-bit
wide and are provided by the 64 pins of the microcontroller.

PORT0 is a 32-bit wide input/output port with dedicated direction control bits for each physical
pin. Out of the 32 pins, 28 pins can be used as general purpose bidirectional I/O pins. Pin P0.31 is an
output only pin. Pins P0.24, P0.26 and P0.27 of PORT0 are not available.
 PORT1 is also a 32-bit wide input/output port. In PORT1, pins P1.0 to P1.15 are not available and
pins P1.16 to P1.31 are the available general purpose input/output pins.

Most of the pins in both the I/O ports of the LPC2148 have more than one function i.e. they are
multiplexed with different functions. For example, Pin 19 of the LPC2148 has three functions namely
P0.0, a general purpose I/O pin, TXD0, the transmitter O/P for UART0 and PWM1, the pulse width
modulator O/P 1. The default function of all the Pins is GPIO

GPIO function is the most frequently used functionality of the microcontroller. The GPIO
function in both the Ports is controlled by a set of 4 registers: IOPIN, IODIR, IOSET and IOCLR.

IODIR: It is a GPIO Port Direction Control register and is used to set the direction i.e. either input
or output of individual pins.

When a bit in this register is set to ‘0’, the corresponding pin in the microcontroller is configured
as Input. Similarly, when a bit is set as ‘1’, the corresponding pin is configured as Output.

IOSET: It is a GPIO Port Output Set Register and can be used to set the value of a GPIO pin that is
configured as output to High (Logic 1).

When a bit in the IOSET register is set to ‘1’, the corresponding pin is set to Logic 1. Setting a bit
‘0’ in this register has no effect on the pin.

The syntax for this register is IOxSET, where ‘x’ is the port number i.e. IO0SET for PORT0 and
IO1SET for PORT1.

IOCLR: It is a GPIO Port Output Clear Register and can be used to set the value of a GPIO pin that
is configured as output to Low (Logic 0).

When a bit in the IOCLR register is set to ‘1’, the corresponding pin in the respective Port is set
to Logic 0 and at the same time clears the corresponding bit in the IOSET register. Setting ‘0’ in the
IOCLR has no effect on the pin.

The syntax for this register is IOxCLR, where ‘x’ is the port number i.e. IO0CLR for PORT0 and
IO1CLR for PORT1.

IOPIN: It is a GPIO Port Pin Value register and can be used to read or write values directly to the
pin.

The status of the Pins that are configured as GPIO can always be read from this register
irrespective of the direction set on the pin (Input or Output).

Q8 b) Write a a program in embedded C to toggle the status of (to generate a square wave on
) port0.0 pin 5

PROGRAM:
#include <LPC21xx.H> /* File for LPC21xx definitions */

void wait (void) /* wait function */

int d;

for (d = 0; d < 1000000; d++); /* To generate delay for LED flash */

int main (void)

unsigned int i =0x001;

IODIR0 = i; /* P0.0 defined as Output */

while (1 ) /* Be in the following infinite loop */

IOSET0 = i; /* Turn on LED connected to P0.0 pin*/

wait (); /* call wait function */

IOCLR0 = i; /* Turn off LED connected to P0.0 pin*/

wait (); /* call wait function */

Q9 What do you mean by preemptive type of scheduling .Explain any one method. 08
Q9 a) Explain the concept of Bit banding in cortex M3 processor. 08
Q9 b) With the block diagram explain the cortex M3 processor. 07
 Q10 Write short notes on 5+5+5

Q10 1) Interfacing ADXL335 Accelerometer with LPC2148

Interfacing ADXL335 Accelerometer with LPC2148

ADXL335 is a 3-axis acceleration sensor with analog outputs for each axis. The analog outputs
are proportional to acceleration along each of the orthogonal axis. It has a minimum
measurement range of ±3g where g is acceleration due to gravity at the earth’s surface
(9.8m/s2). Most common applications include tilt, motion and shock sensing. The voltage supply
range for ADXL335 is 1.8V to 3.6V. ADXL335 is available in 16-lead LFCSP_LQ package.
Output Voltage:
The output voltage(hence sensitivity) for each of the axis is directly proportional(ratiometric)
with the supply voltage used. The Zero g bias output is also proportional to the supply voltage.
The Zero g output voltage is typically Vs/2 for any given valid supply voltage.
Sensitivity:
Sensitivity is also termed as scale factor for ADXL335 sensor is given in “milli-volts(or volts)
per g” i.e. mV/g(or V/g). For a given Supply Voltage Vs, the sensitivity is typically 0.1xVs
V/g or Vsx100 mV/g. Hence for a Vs = 3.3V the sensitivity will be
typically 330mV/g or 0.33V/g. We will use V/g as unit for sensitivity in the example shown later
on.
Converting ADC result to g:
Lets start with the basic formula to convert a 10-bit ADC result into voltage for a given VREF.
The sensor output can be computed as:
ADC_Volts = ADC_RESULT * VREF 1024 V

Lets, also keep units for all voltages in volts. We get the g from ADC result as follows:
g = ADC_Volts – Zero_G Sensitivity

Combining the above two equations, with VREF and Vs in Volts, we get,
g = ((ADC_Result*VREF)/1024) – (Vs/2) 0.1*Vs

For interfacing the Accelerometer we will use the ADC block of LPC2148. Since our sensor has 3
outputs we will use AD0.1, AD0.2, AD0.3 to read the output voltages. After fetching the ADC
result we can then convert it to g for each axis.
Schematic:
Q10 2) Interfacing HC-SR04 Ultrasonic Distance Sensor with LPC2148
Interfacing HC-SR04 Ultrasonic Distance Sensor with LPC2148
As the name suggests, the HC-SR04 Ultrasonic Distance/Ranging Sensor uses ultrasound to
measure distance from a object ahead of the sensor. Ultrasound is a sound wave with
frequency greater than the audible limit i.e. > 20Khz. HCSR-04 uses 40Khz ultrasound to
measure distance between itself and any object ahead of it with a sensing range of 2
centimeters to 4 meters.
Pinout: The module has got 4 pins viz. VCC(+5V), TRIG, ECHO, GND.

Working principle
Ultrasonic Distance/Ranging Sensors are based on similar working principle to what is used in
SONAR. It has got two transducers, one for transmitting ultrasound and second one for
receiving the echo. Based on the time it takes for echo to arrive we can compute the distance,
since we already know the speed of sound in air which is around 343 m/s or 1235 km/h (at
20°C).
Interfacing Steps:

1. To start distance measurement a short pulse of 10us is applied to Trigger pin.

2. After this the HC-SR04 Module will send a burst of 8 ultrasonic pulses at 40Khz.
3. It will then output a HIGH for the amount to time taken for the sound waves to reach
back.
4. The pulse HIGH time is measured and then used to calculate the distance.

Distance calculations:
We know speed of sound in air,
Vs = 343 m/s = 0.0343 cm/us

We also know the time it took to sound waves to emit and echo back, lets call it T. Now, by
using basic distance formula we can find the distance as:
Distance Traveled = Speed x Time taken

DT = 343 m/s x T seconds

Now, since we will be measuring ECHO ON-Time in microseconds and also to get distance in
centimeters we can change the units as follows:
DT in cm = 0.0343 cm/us x T us
After this we divide the computed value by 2 since the waves have traveled double distance.
D = DT 2 = 0.0343 x T 2 cm

Now, lets do a programming exercise. For the interfacing example given below, P0.2 is
configured as output and connected to TRIG pin and P0.3 is configured as input and connected
to ECHO pin of the Ultrasonic Distance sensor. Timer0 module is used for generating delays
with 1 us resolution. It is also used to measure time for ECHO pulse using two simple functions
viz. startTimer0() & stopTimer0().
Schematic:

10 c) Register organization of ARM Processor in User Mode.

General-purpose registers hold either data or an address. They are identified with the letter r
prefixed to the register number. For example, register 4 is given the label r4. Figure shows the
active registers available in user mode. All the registers shown are 32 bits in size.
There are upto 18activeregisters: 16 data registers and 2 processor status registers. The data
registers are visible to the programmer as r0 to r15. The ARM processor has three registers
assigned to a particular task or special function: r13, r14, and r15. They are frequently given
different labels to differentiate them from the other registers.
special-purpose registers:
■ Registerr 13 is traditionally used as the stack pointer(sp) and stores the head of the stack in
the current processor mode.
■ Register r14 is called the link register (lr) and is where the core puts the return address
whenever it calls a subroutine.
■ Registerr 15 is the program counter (pc) and contains the address of the next instruction to
be fetched by the processor.
Depending upon the context, registers r13 and r14 can also be used as general-purpose
registers , which can be particularly useful since these registers are banked during a processor
mode change. However, it is dangerous to use r13 as a general register when the processor is
running any form of operating system because operating systems often assume that r13 always
points to a valid stack frame. In ARM state the registers r0 to r13 are orthogonal—any
instruction that you can apply to r0 you can equally well apply to any of the other
registers.However,there are instructions that treat r14 and r15 in a special way. In addition to
the 16 data registers, there are two program status registers: cpsr and spsr (the current and
saved program status registers, respectively). The register file contains all the registers available
to a programmer.Which registersare visible to the programmer depend upon the current mode
of the processor.

CPSR Register

The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated
32-bit register and resides in the register file. Figure shows the basic layout of a generic
program status register. Note that the shaded parts are reserved for future expansion. The cpsr
is divided into four fields,each8bitswide:flags,status,extension,and control. In current designs
the extension and status fields are reserved for future use. The control field contains the
processor mode, state, and interrupt mask bits. The flags field contains the condition flags.
Some ARM processor cores have extra bits allocated. For example, the J bit, which can be found
in the flags field, is only available on Jazelle-enabled processors, which execute 8-bit
instructions.

N Negative flag, records bit 31 of the result of flag-setting operations.

Z Zero flag, records if the result of a flag-setting operation is zero.
C Carry flag, records unsigned overflow for addition, not-borrow for subtraction,
V Overflow flag, records signed overflows for flag-setting operations.
I =1 disables IRQ interrupts.F
F =1 disables FIQ interrupts.T
T =1 indicates Thumb state. T =0 indicates ARM state. Use the BX or BLX instructions to
change this bit (ARMv4T and above).
MMMMM mode bits ondicate the current processor mode