Verilog code Test bench code
ASYNCHRONOUS COUNTER
module asc(rst, clk, q,en);
input rst,en;
input clk;
output [3:0] q;
reg [3:0] q;
initial
begin
q=4'b0000;
end
always@ (posedge clk)
begin
if (rst==0)
q=4'b0000;
if (en==1)
q=q+1;
else
q=4'b1111;
end
endmodule
module asc11_v;
// Inputs
reg rst;
reg clk;
reg en;
// Outputs
wire [3:0] q;
Verilog code Test bench code
// Instantiate the Unit Under Test (UUT)
asc uut (
.rst(rst),
.clk(clk),
.q(q)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
en=0;
#10 rst=1; en=1;
forever #10 clk=~clk;
// Add stimulus here
end
Endmodule
D-FLIPFLOP
module dff(d, clk, rst, q, qb);
input d;
input clk;
input rst;
output q;
output qb;
reg q,qb;
always @(posedge clk)
begin
Verilog code Test bench code
if(rst==1)
q=1'b0;
else
q=d;
qb=~q;
end
endmodule
module dff1_v;
// Inputs
reg d;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
dff uut (
.d(d),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial begin
Verilog code Test bench code
// Initialize Inputs
d = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100 rst=0;
#100 d=1;
#100 d=0;
#100 rst=0;
#100 d=1;
#100 d=0;
// Add stimulus here
end
always
#50 clk=~clk;
endmodule
INVERTER
module inverter1(a, b);
input a;
output b;
Verilog code Test bench code
assign b=~a;
endmodule
module inverter11_v;
// Inputs
reg a;
// Outputs
wire b;
// Instantiate the Unit Under Test (UUT)
inverter1 uut (
.a(a),
.b(b)
);
initial begin
// Initialize Inputs
a = 0;
// Wait 100 ns for global reset to finish
#100;
a=1;
#100;
// Add stimulus here
Verilog code Test bench code
end
endmodule
JK FLIPFLOP
module jkff(j, k, clk, q, qb,rst);
input j;
input k,rst;
input clk;
output q;
output qb;
reg q,qb;
always @ (posedge clk)
begin
if(rst==0)
q=1'bz;
else begin
case({j,k})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
default:q=~q;
endcase
end
qb=~q;
end
Verilog code Test bench code
endmodule
module jknew_v;
// Inputs
reg j;
reg k;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
jkff uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qb(qb),
.rst(rst)
);
initial begin
// Initialize Inputs
j = 0;
k = 0;
Verilog code Test bench code
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100 j=0; k=1;
#100 j=1; k=0;
#100 j=1; k=1;
#100 rst=1;
#100 j=0; k=0;
#100 j=0; k=1;
#100 j=1; k=0;
#100 j=1; k=1;
// Add stimulus here
end
always #50 clk=~clk;
endmodule
PARALLEL ADDER
module parre(a, b, y);
input [2:0] a;
input [2:0] b;
output [3:0] y;
reg [3:0] y;
always @(a or b)begin
y=a+b;
end
Verilog code Test bench code
endmodule
module parr1_v;
// Inputs
reg [2:0] a;
reg [2:0] b;
// Outputs
wire [3:0] y;
// Instantiate the Unit Under Test (UUT)
parre uut (
.a(a),
.b(b),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
Verilog code Test bench code
initial begin
a=3'b001;b=3'b001;
#10
a=3'b011; b=3'b111;
#10 a=3'b101; b=3'b100;
#100 $stop;
end
endmodule
SERIAL ADDER
module sad(a, b, start, clk, ready, result);
input a;
input b;
input start;
input clk;
output ready;
output [7:0] result;
reg [7:0] result;
reg sum,carry,ready;
integer count;
initial count = 8;
always @ (negedge clk)
begin
if(start)
begin
count=0; carry=0; result =0;
end
else
Verilog code Test bench code
begin
if(count<8)
begin
count=count+1;
sum=a^b^carry;
carry=(a&b)|(a&carry)|(b&carry);
result={sum,result[7:1]};
end
end
if(count==8)
ready=1;
else
ready=0;
end
endmodule
module saaad_v;
// Inputs
reg a;
reg b;
reg start;
reg clk;
// Outputs
wire ready;
wire [7:0] result;
Verilog code Test bench code
// Instantiate the Unit Under Test (UUT)
sad uut (
.a(a),
.b(b),
.start(start),
.clk(clk),
.ready(ready),
.result(result)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
start = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100
start=0;
clk=1;
a=1;
b=1;
Verilog code Test bench code
end
always #50 clk = ~clk;
endmodule
RS FLIPFLOP
module srff(s, r, clk, q, qb);
input s;
input r;
input clk;
output q;
output qb;
reg q,qb;
always @(r,s,clk)
begin
if(clk==1)
begin
case({s,r})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
default: q=1'bz;
endcase
end
Verilog code Test bench code
qb=~q;
end
endmodule
module srff1_v;
// Inputs
reg s;
reg r;
reg clk;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
srff uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
clk=0;
Verilog code Test bench code
s=0;
r=0;
#100 clk=0; s=0; r=0;
#100 clk=0; s=1; r=0;
#100 clk=0; s=1; r=1;
#100 clk=1; s=0; r=0;
#100 clk=1; s=0; r=1;
#100 clk=1; s=1; r=0;
#100 clk=1; s=1; r=1;
// Add stimulus here
end
endmodule
module syuc(clk, rst, q);
input clk;
input rst;
output [3:0] q;
reg [3:0] q;
initial
begin
q=4'b0000;
end
always @ (posedge clk )
begin
if(rst==1)
Verilog code Test bench code
q=q+1;
else
q=4'b0000;
end
endmodule
module sync_v;
// Inputs
reg rst;
reg clk;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
asc uut (
.rst(rst),
.clk(clk),
.q(q)
);
initial begin
// Initialize Inputs
rst = 0;
clk = 0;
Verilog code Test bench code
// Wait 100 ns for global reset to finish
#10 rst=1;
forever #10 clk=~clk;
// Add stimulus here
end
endmodule
T FLIPFLOP
module tff11(t, clk, rst, q, qb);
input t;
input clk;
input rst;
output q;
output qb;
reg q,qb;
always @ (posedge clk )
begin
if(rst==0)
q=1'bz;
else
case(t)
1'b0:q=q;
default:q=~t;
endcase
Verilog code Test bench code
qb=~q;
end
endmodule
module tff111_v;
// Inputs
reg t;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
tff11 uut (
.t(t),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
Verilog code Test bench code
t = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100 rst=1;
#100 t=1;
t=0;
#100 t=1;
end
always #100 clk=~clk;
// Add stimulus here
endmodule
TRANSMISSION GATE
module tg(x, xb, i, o);
input x;
input xb;
input i;
output o;
reg o;
always @ (i or x)
begin
Verilog code Test bench code
if (x==1 && xb==0)
o=i;
else
o=1'bz;
end
endmodule
module tg11_v;
// Inputs
reg x;
reg xb;
reg i;
// Outputs
wire o;
// Instantiate the Unit Under Test (UUT)
tg uut (
.x(x),
.xb(xb),
.i(i),
.o(o)
);
initial begin
// Initialize Inputs
Verilog code Test bench code
x = 0;
xb = 0;
i = 0;
// Wait 100 ns for global reset to finish
#100 x=1; xb=0;
#100 i=0;
#100 x=1; xb=0;
#10 i=1;
// Add stimulus here
end
endmodule
TRI-STATE BUFFER
module tristate1(a, b, y);
input a;
input b;
output y;
reg y;
always@(a,b)
begin
if(b==1'b1)
y=a;
else
y=1'bz;
Verilog code Test bench code
end
endmodule
module buf_v;
// Inputs
reg a;
reg b;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
tristate1 uut (
.a(a),
.b(b),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100 a=0;
Verilog code Test bench code
#100 b=1;
#100 a=1;
#100 b=1;
// Add stimulus here
end
endmodule
module uni(a, b, not1, and1, nand1, or1, nor1, exor1, exnor1);
input a;
input b;
output not1;
output and1;
output nand1;
output or1;
output nor1;
output exor1;
output exnor1;
assign not1=~a;
assign and1=a&b;
assign nand1=~(a&b);
assign or1=a|b;
assign nor1=~(a|b);
assign exor1=a^b;
assign exnor1=~(a^b);
Verilog code Test bench code
endmodule
module uni1_v;
// Inputs
reg a;
reg b;
// Outputs
wire not1;
wire and1;
wire nand1;
wire or1;
wire nor1;
wire exor1;
wire exnor1;
// Instantiate the Unit Under Test (UUT)
uni uut (
.a(a),
.b(b),
.not1(not1),
.and1(and1),
.nand1(nand1),
.or1(or1),
.nor1(nor1),
.exor1(exor1),
.exnor1(exnor1)
);
Verilog code Test bench code
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
// Add stimulus here
end
endmodule
module msjk1(j, k, clk, q, qb);
input j;
input k;
input clk;
output q;
output qb;
reg tq,q,qb;
always @ (clk)
begin
if(!clk)
Verilog code Test bench code
begin
if(j==1'b0 && k==1'b1)
tq=1'b0;
else if (j==1'b1 && k==1'b0)
tq=1'b1;
else if(j==1'b1 && k==1'b1)
tq=~tq;
end
if(clk)
begin
q=tq;
qb=~tq;
end
end
endmodule
module msjkff1_v;
// Inputs
reg j;
reg k;
reg clk;
// Outputs
wire q;
wire qb;
Verilog code Test bench code
// Instantiate the Unit Under Test (UUT)
msjk1 uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qb(qb)
);
initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100 j=0; k=1;
#100 j=1; k=0;
#100 j=1; k=1;
// Add stimulus here
end
always #50 clk=~clk;
endmodule
