Chapter

01. Ans: (d)

1 Number Systems
(Solutions for Vol‐1_Classroom Practice Questions)

03. Ans: (c)

Sol: 135x + 144x = 323x Sol: In 2’s complement representation the sign
2 1 0
(1×x + 3 × x + 5 × x )+(1×x +4×x + 4×x ) 2 1 0 bit can be extended towards left any number
= 3x2 + 2x1 + 3x0 of times without changing the value. In
given number the sign bit is ‘X3’, hence it
 x2+3x+5+x2+4x+4 = 3x2+ 2x + 3 can be extended left any number of times.
x2  5x  6 = 0
04. Ans: (c)
(x6) (x+ 1) = 0 (Base cannot be negative)
Sol: Binary representation of +(539)10:
Hence x = 6.
(OR) 2 539
2 269 –1
As per the given number x must be greater 2 134 –1
than 5. Let consider x = 6 2 67 –0
(135)6 = (59)10 2 33 –1
2 16 –1
(144)6 = (64)10 2 8 –0
(323)6 = (123)10 2 4 –0
2 2 –0
(59)10 + (64)10 = (123)10
1 –0
So that x = 6
(+539)10 =(10000 11 0 11)2= (00100 0011011)2
2’S complement  110111100101
02. Ans: (a)
Hexadecimal equivalent (DE5)H
Sol: 8-bit representation of
+12710 = 01111111(2)
05. Ans: 5
1’s complement representation of Sol: Symbols used in this equation are 0,1,2,3
 127 = 10000000. Hence base or radix can be 4 or higher
(312)x = (20)x (13.1)x
2’s complement representation of
3x2 + 1x +2x0 = (2x+0) (x+3x0+x-1)
 127 = 10000001.
 1
3x2+x+2 = (2x)  x  3  
No. of 1’s in 2’s complement of  x
 127 = m = 2 3x2 + x + 2 = 2x2 + 6x + 2
No. of 1’s in 1’s complement of x2 – 5x = 0
x(x –5) = 0
 127 = n = 1
x = 0(or) x = 5
 m: n = 2:1 x must be x > 3, So x = 5
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 :3: Digital & Microprocessors

06. Ans: 3 09. Ans: (b)

Sol: 1235 = x8y Sol: A.7 5 B.6 5
1  52 + 2  51 +3 50 = x.y1 + 8 y0
25 + 10 + 3 = xy+8 (111 101) (110 101)
 xy = 30
Possible solutions: C. 3 7 D. 2 6

i. x = 1, y = 30 (011 111) (010 110)

ii. x = 2, y = 15
iii. x = 3, y = 10
 3 possible solutions exists. 10. Ans: (a)
Sol: 2’s complement arithmetic is preferred in
digital computers because it is efficient and
07. Ans: 1 one representation for zero.
Sol: The range (or) distinct values
For 2’s complement  –(2n–1 )to +(2n–1–1) 11. Ans: (a)
Sol: (11X1Y)8 = (12C9)16
For sign magnitude
n–1 n–1
84 + 83 + 64X +8+Y
 –(2 –1) to +(2 –1)
= 163 + (2  162) + (12  16) + 9
Let n = 2  in 2’s complement
– (22–1) to + (22–1 –1) 4096 + 512 + 64X + 8 + Y
– 2 to +1  –2, –1, 0, +1  X = 4 = 4096 + 512 + 192 + 9
n = 2 in sign magnitude  –1 to +1 Y = 3
X–Y=1  4616 + 64X + Y = 4809
64X + Y = 193
08. Ans: (c) By verification option (a) is correct
Sol: (a) (68)16 = (001 101 000)2

= (1 5 0)8 12. Ans: (d)

(b) (8C)16 = ( 010 001 100)2 Sol: 2’s comp no: a3 a2 a1 a0

= (2 1 4 )8
2’s comp no. using 6 bits
(c) (4F)16 = (001 001 111 )2
 a3 a3 a3 a2 a1 a0
= (1 1 7)8
(2’s comp no) 2 + 1
(d) (5D)16 = (001 011 101 )2
 a3 a3 a2 a1 a0 1
= (1 3 5 )8

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Chapter

01. Ans: (c)

2 Logic Gates &
Boolean Algebra
Stage 2:
Sol: Given 2’s complement numbers of sign bits X X o/p
are x & y. z is the sign bit obtained by -----------------
adding above two numbers.  Overflow is 0 1 1
indicated by = x y z  x y z 1 0 1

Examples For second XOR gate o/p = 1.

1. A = +7 0111 Similarly for third XOR gate o/p = X & for
B = +7 0111 fourth o/p = 1
14 1110  x y z For Even number of XOR gates o/p = 1
2. A = +7 0111 For 20 XOR gates cascaded o/p = 1.
B = +5 0101 03. Ans: (b)
12 1100  x y z Sol:
3. A = –7 1001 w,x w,x
B = –7 1001 y,z y,z
–14 10010  x y z 1 1 1 1
4. A = –7 1001
1 1 1 1 1 1 1 1
B = –5 1011
–12 10100  x y z 1 1 1 1
yz
1 1 1 1
02. Ans: (b) v=0 v=1
Sol: Truth table of XOR
x
A B o/p
0 0 0 04. Ans: (c)
0 1 1 Sol:
1 0 1 f1 x
1 1 0 f2 f4
Stage 1:
f3
Given one i/p = 1 Always.
x  f1f 2
1 X o/p f4 = f1. f2 + f3
-----------------
1 0 1 = X
05. Ans: (d)
1 1 0 = X
Sol: A Q B
For First XOR gate o/p = X
P R
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08. Ans: 40
At A Sol: t(ns)
10 t=0 t = 20 t = 40 t = 60 t = 80
0 1 2 3 4 5 6 7 8 9
(A)

At P (C)
B(without delay)

At Q B (with delay)
A B (with delay)
At R
② Z(without delay)
③ ④
At B ①
Z (with delay)
40 n sec

06. Ans: (c)  Z is 1 for 40 nsec

Sol: x 1  x 3  x 1 x 3  x 1 x 3  y
09. Ans: (c)
x2  x4  x2 x4  x2 x4  z Sol: Logic gates X  Y  XY  XY1
x 1  
 x3  x2  x4  Where Y1  Y
 y  z  0 , when y = z It is a NAND gate and thus the gate is
 option (c) is true ‘Universal gate’.
For all cases option A, B, D not satisfy.
10. Ans: (d)
07. Ans: (b) Sol: A. X  A  B  AB
Sol: M(a,b,c) = ab + bc + ca
B. X  A  B
M(a , b, c) = b c  a b  a c
C. X  A  B  AB
M(a, b, c ) = ab + b c + c a
D. X  A B  A  B
M( M (a , b, c) , M(a,b, c ), c)
= b c  ab  a c (ab  bc  ac )
11. Ans: (a)
 (ab  b c  ca )c  b c  ab  a c c
Sol: XOR gate is not a universal gate, because it
 b c  ab  a c ( ab  b c  ac )
is not possible to realize any Boolean
function using only XOR gates.
b c  ab  a c (c)  abc
= ab c  abc  abc  abc 12. Ans: (b)
= c[ab  ab]  c[ab  ab ] Sol: (A) A  B = 0 only when A = B
=  m(1, 2, 4, 7) (B) A  B  A.B  0 only when A = 1 and
B=1
 M (x, y, z) = a  b  c
(C) A.B  0 only when A = 1 and B = 0
Where x = M(a , b, c) , y = M(a,b, c ), z = c (D) A  B = 1 only when A  B

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13. Ans: (b) 15. Ans: (a)

Sol: (A) ab + bc + ca + abc Sol: When all inputs of a NAND-gate are
shorted to get a one input, one output gate,
bc (1 + a) + ca + ab
it becomes an inverter.
bc + ca + ab When all inputs of a NAND – gate are at
logic ‘0’ level, the output is at logic ‘1’
Inverse function (ab  bc  ca ) level.
Both statements are true and statement-II is
= a b +b c +c a the correct explanation of statement-I
(B) ab + a b  c
16. Ans: (c)
Inverse function = ab  a b  c Sol: A NAND gate represents a universal logic
family.
= ( a + b ) (a + b) c Only two NAND gates are sufficient to
accomplish any of the basic gates.
= (a b + ab ) c Statement-I is true but statement-II is false.
= (a  b) c
(C) (a+bc)
Inverse function = a  bc
= a ( b  c)

(D) (a  b  c)(a  b  c ) (a  b  c)
Inverse function

(a  b  c)(a  b  c ) (a  b  c)

= abc + a bc + ab c

14. Ans: (c)

Sol: AND gate : Boolean multiplication
OR gate : Boolean addition
NOT gate : Boolean complementation

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Chapter 3 K ‐ Maps
01. Ans: (b) wz
SOP
Sol: wx xy 00 01 11 10
yz 00 01 11 10 00 0  0 0
1 1
00 01 0  1 1 wy

01  1 11 1 1 1 1

 1 10 0  0 0
11
xy
 = xy+yw
10 1 1
SOP: x y + y w
f  xz  xz POS: y(x + w)

02. Ans: (b) 04. Ans: (a)

Sol: Sol: For n-variable Boolean expression,
ab
cd 00 01 11 10 Maximum number of minterms = 2n
00 1   1 Maximum number of implicants = 2n
01  1 2n
 Maximum number of prime implicants =
11 bc 2
10 1  = 2 n 1

bd
05. Ans: (c)
f bdbc Sol:
AB
C 00 01 11 10
03. 0 1 1 0 0
Sol: 1 0 1 1 0
x+w
POS wz F(A, B, C) = A C  BC
xy 00 01 11 10
00 0  0 0
01 0  1 1
06. Ans: 1

11 1 1 1 1 Sol: After minimization = A  B  C  D  

10 0  0 0
= ABCD
y

= y(x+w)
 only one minterm.

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07. Ans: 3 The minimal form is

Sol: w z  w xy  x yz F = xyz
yz None of the options is correct
wx 00 01 11 10
00 1 1
01 1 1 1 10. Ans: (a)
Sol: Given K-map
11
10 1 3
AB
CD 00 01 11 10

08. Ans: (c) 00 1 1 0 1

01 0 0 0 1 2
Sol: Given K-map is
11 1 0 0 0 1
X1X2
0
X3X4 00 01 11 10 4 10 1 0 1
00 1 d d
01 1 d 1
11 d 1 No. of essential prime implicants = 4.
10 1 d d

Output = X 2 X 4  X 1 X 3  X 2 X 4

09. Ans: None

Sol: x
yz 0 1
1 1
00
01 1
11 1 1
10 1 1

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Chapter

01. Ans: (d)

4 Combinational Circuits
03. Ans: (a)
Sol: Let the output of first MUX is “F1” Sol: The given circuit is binary parallel
adder/subtractor circuit. It performs A+B,
F1 = AI0+AI1
A–B but not A + 1 operations.
Where A is selection line, I0, I1 = MUX
Inputs K C0 Operation
0 0 A+B (addition)
F1  S1 .W  S1 .W  S1  W
0 1 A+B+1(addition with carry)
Output of second MUX is 1 0 A+ B (1’s complement addition)
F  A.I 0  A.I1 1 1 A+ B +1(2’s complement subtraction)

F  S2 .F1  S 2 .F1
04. Ans: (d)
F  S 2  F1 Sol: It is expansion of 2:4 decoders to 1 : 8
But F1  S1  W demultiplexer A1, A0 must be connected to
S1, S0 i.e.., R = S0, S = S1
F  S 2  S1  W Q must be connected to S2 i.e., Q = S2
i.e., F  W  S1  S 2 P is serial input must be connected to Din

05. Ans: 6
02. Ans: 19.2 Sol: T = 0 → NOR → MUX 1 → MUX 2
Sol: One AND/OR gate delay = 1.2 s 2ns 1.5ns 1.5ns
One XOR gate delay = 2.4 s Delay = 2ns + 1.5ns + 1.5ns = 5ns
Full Adder with 2 Half Adder T = 1 → NOT → MUX 1→NOR→ MUX 2
HA1
1ns 1.5ns 2ns 1.5ns
A B HA2
Delay = 1ns + 1.5ns + 2ns + 1.5ns = 6ns
Sum
C Hence, the maximum delay of the circuit is
6ns
Carry

In one F.A; Sum delay = 4.8 s 06. Ans: –1

Carry delay = 2.4 + 1.2 + 1.2s = 4.8 s Sol: When all bits in ‘B’ register is ‘1’, then only
 RippleCarry waiting time it gives highest delay.
= 4.8  3 = 14.4 s
 ‘–1’ in 8 bit notation of 2’s complement
Final Result time = 14.4 + 4.8 = 19.2 sec is 1111 1111

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 : 10 : Digital & Microprocessors

07. Ans: (d)

Sol: The race hazard problem does not occur in Input
Output
combinational circuits.
The output of a combinational circuit
depends upon present inputs only.
Statement-I is false but Statement-II is true. 10. Ans: (b)
Sol: A 64 input MUX using 8-input MUX
08. Ans: (b)
Sol: A de-multiplexer can be used as a decoder. I0
A decoder with enable input acts as a de- I1 81
I0
mutiplexer, while using Enable input as a I2 MUX I1 81
data input line. De-multiplexer is realized
I3 I2 MUX
I4 I3
using AND gates. I5 I4
I6 I5
A B F I7 I6
I7
0 0 C
I0 81
0 1 C I1
I2
MUX
1 0 C I3
I4
1 1 C I5
I6
I7
09. Ans: (b) A 6-variable function can be
Sol: Half Adder implemented using 6-input MUX

11. Ans: 195

Input Output Sol: In a 16 bit parallel binary adder, the carry
has to propagate 15 stages plus the
maximum of time taken for producing sum
and carry worst case Delay, T = 15×12+15
D-Flipflop
T = 180+15
J Q T = 195ns
Input
Output
K Q 12. Ans: (b)
Sol: Any Boolean function can be realized by
using a suitable multiplexer.
T-Flipflop A multiplexer can be realized using NAND
J
and NOR gates, which are universal gates.
Input Q
Output Both statements are correct but statement-II
K Q is not a correct explanation for statement-I.
Exclusive - OR
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 Chapter

01. Ans: (c)

5 Sequential Circuits
As the clear input is given to be
Sol: Given Clk, X1, X2 synchronous so it waits upto the next clock
pulse to clear the counter & hence the
Output of First D-FF is Q1
counter get’s cleared during the 7th clock
Output of Second D-FF is Q2 pulse.
1 2 3 4
 mod of counter = 7
clk
04. Ans: (b)
Sol: The given circuit is a mod 4 ripple down
X1 counter. Q1 is coming to 1 after the delay of
2t.
CLK Q1 Q0
X2
0 0
1 1 1
Q1 2 1 0
3 0 1
Q2 4 0 0

Y=Q1Q2
05. Ans: (c)
Sol: Assume n = 2
02. Ans: 4 Q1 0
Sol: In the given first loop of states, zero has 2 4 1
repeated 3 times. So, minimum 4 number of clk 2-bit
counter decoder2
Flip-flops are needed.
3
Q0
03. Ans: 7
Sol: The counter is cleared when Outputs of counter is connected to inputs of
QDQCQBQA = 0110 decoder
Clk QD QC QB QA
0 0 0 0 0 Counter outputs Decoder inputs Decoder outputs
1 0 0 0 1 Q1 Q0 a b d3 d2 d1 d0
0 0 0 0 0 0 0 1
2 0 0 1 0 0 1 0 1 0 0 1 0
3 0 0 1 1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0
4 0 1 0 0
5 0 1 0 1 The overall circuit acts as 4-bit ring counter
6 0 1 1 0 n=2
7 0 0 0 0  k = 22 = 4, k-bit ring counter
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06. Ans: (b) 07. Ans: (b)

Sol: Sol:
CLK Serial in= A B C D
BC D J K Q Qn T  J  Q n  Qn+1
0
1 1
1
1
0
1
1
0
0
1
K  Q  n

0 0 0 1 0.1 = 0 0
2 0 0 1 1 0
0 0 1 0 1.0 = 0 1 Qn
3 0 0 0 1 1
4 0 0 0 0 1 0 1 0 1 0.1 = 0 0
5 1 1 0 0 0 0 1 1 0 1.1 = 1 0 0
6 0 0 1 0 0 1 0 0 1 1.1 = 1 1
7 1 1 0 1 0 1 0 1 0 1.0 = 0 1 1
1 1 0 1 1.1 = 1 1
1 1 1 0 1.1 = 1 0 Qn
 After 7 clock pulses content of shift
register become 1010 again KQn 00 01 11 10
J
0 1

1 1 1 1

T = J Q n +KQn = (J+Qn) (K + Q n )

08. Ans: 1.5

Sol:
Clk Q1 Q2 Q3 Q4 Q5 Y= Q3 + Q5
0 0 1 0 1 0 0
1 0 0 1 0 1 1
2 1 0 0 1 0 0
3 0 1 0 0 1 1
4 1 0 1 0 0 1
5 0 1 0 1 0 0

The waveform at OR gate output, Y is [A = +5V]

A

0 T 2T 3T 4T 5T

T1 = 5T
Average power
2
VAo 1 1  1  2T 2
A 2 dt 
T1 5T
P   TLt1  o  RT  T
  
2
y ( t ) dt A dt
R R T1 3T 
 1
2 2
A2
 (2T  T)  (5T  3T)  A .3T  5 .3  1.5 mw
RT1 R (5T ) 10  5
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 : 13 : Postal Coaching Solutions

09. Ans: (b)

Reducing state table
Sol:
Present Next State Output (Y) Present state Next state
State X=0 X=1 X=0 X=1 X=0 X=1
A A E 0 0
A A D
B C A 1 0
B B A
C B A 1 0
D A B
D A B 0 1
D A B
E A C 0 1
Finally reduced state table is
Step (1):
Reduced state table
By replacing state B as state C then state
Present state Next state
B, C are equal.
X=0 X=1
Reducing state table A A D
B B A
Present state Next state D A B
X=0 X=1
A A E  3 states are present in the reduced state
B B A table
B B A
D A B 10. Ans: (c)
E A B Sol: State table for the given state diagram

State Input Output

S0 0 1
Step (2): S0 1 0
Reducing state table S1 0 1

Present state Next state S1 1 0

X=0 X=1
Output is 1’s complement of input.
A A E
B B A
11. Ans: (c)
D A B
Sol: In state (C), when XYZ = 111, then
E A B
Ambiguity occurs
Because, from state (C)
 When X = 1, Z = 1
State D, E are equal, remove state E and
 N.S is (A)
replace E with D in next state. When Y = 1, Z = 1  N.S is (B)
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12. Ans: (c) 13. Ans: (d)

Sol: For Asynchronous sequential circuits clock Sol: Master slave JK flip flop is a edge triggered
is applied at one flip flop and the next stage flip flop.
receives clock from previous stage output.

14. Ans: (b)

Sol: Divider : Bi stable multivibrator
Clips input voltage at Two predetermined levels : Schmitt trigger
Square wave generator : Astable multivibrator
Narrow current pulse generator : Blocking oscillator

15. Ans: (a) 16. Ans: (a)

Sol: A flip-flop is a bistable multivibrator. Sol: The collection of all state variables (memory
A flip-flop remains in one stable state element stored values) at any time, contain
indefinitely until it is directed by an input all the information about the past, necessary
signal to switch over to the other stable to account for the circuit’s future behaviour.
state. A change in the stored values in memory
elements changes the sequential circuit from
Both statements are correct and one state to another.
statement - II is correct explanation of Both statements are correct and
statement-I statement - II is correct explanation of
statement-I.

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Chapter

01. Ans: (b)

6 Logic Gate Families
02. Ans: (b)
Sol: VOH(min):- Sol: Fan out is minimum in DTL
(High level output voltage) (High Fan-out = CMOS)
The minimum voltage level at a Logic
Power consumption is minimum in CMOS.
circuit output in the logic ‘1’ state under
Propagation delay is minimum in ECL
defined load conditions.
(fastest = ECL)
VOL(max):-
(Low level output voltage) 03. Ans: (b)
The maximum voltage level at a logic Sol: When Vi = 2.5V,
circuit output in the Logical ‘0’ state under Q1 is in reverse active region
defined load conditions. Q2 is in saturation region
Q3 is in saturation region
VIL(max):- (Low level input voltage) Q4 is in cut-off region
The maximum voltage level required for a
logic ‘0’ at an input. Any voltage above this 04. Ans: (d)
level will not be accepted as a Low by the Sol: The given circuit can be redrawn as below:
logic circuit.
Vdd

VIH(min) :- (High level Input voltage) P Q

The minimum voltage level required for OUT
logic ‘1’ at an input. Any voltage below this
level will not be accepted as a HIGH by the P
Logic circuit.
IOH
IIH Q
NOT gate
+ +

 
VOH VIH
- -
OUT  PQ  PQ
= P AND Q
High
05. Ans: (b)
IOL
IIL Sol: As per the description of the question, when
the transistor Q1 and diode both are OFF
+ + then only output z = 1.
VOL
- VIL
- X Y Z Remarks
0 0 0 Q1 is OFF, Diode is ON
0 1 1 Q1 is OFF, Diode is OFF
Low 1 0 0 Q1 is ON, Diode is OFF
1 1 0 Q1 is ON, Diode is OFF
Fig: currents and voltages in the two logic
states. Hence Z = XY
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06. Ans: (c) Both statements are true and statement-II is

Sol: Propagation delay time is less in Schottky the correct explanation of statement-I.
transistor because it is not entering in to
saturation region. Schottky transistors 09. Ans: (a)
operate in active region whenever it is ON. Sol: The TTL NAND gate in tri-state output
configuration can be used for a bus
07. Ans: (b) arrangement with more than one gate output
Sol: To obtain high Switching speed BJT connected to a common line.
operated in active region. In the active
The tri-state configuration has a control
region BJT works as a linear element.
input, which control the bus line.
08. Ans: (a) Both statements are true and statement-II is
Sol: When transistor switches are to be used in the correct explanation of statement-I.
an application where speed is a premium, it
is better to reduce the storage time.
It is comparatively easy to reduce storage
time rather than the rise time and fall time
of a transistor switch.

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Chapter

01. Ans: (b)

7 Semiconductor Memories
04. Ans: (c)
Sol: Square of a 4 - bit number can be at most Sol:
8 - bit number.
{ i.e (1111)2 = (15)10
[(15)10]2 = (225)10}. C A
Therefore ROM requires 8 data lines.
Data is with size of 4 bits
ROM must require 4 address lines and 8
1
data lines ROM
E
ROM = 2n  m
n = inputs (address lines),
m = output lines
n = 4, m = 8.
02. Ans: (a) C
Sol: ROM is used to design a combinational
circuit. The number of address lines of the
t1 t2 time
ROM is equal to the number of input
variables in the truth table. At the rising edge of the First clock pulse
ROM is represented as 2n × m where 2n the content of location (0110)2 = 6  1010
inputs and m output lines. appears on the data bus, at the rising of the
second clock pulse the content of location
[Where n = address bits]
(1010)2 = 102  1000 appears on the data
03. Ans: (b) bus.
Sol: 8 4 2 1 2 4 2 1 2421
05. Ans: (b)
i/p s o/p s Outputs
Sol: 1–bit SRAM memory cell is
X3 X2 X1 X0 Y3 Y2 Y1 Y0 WL
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 1 BL
0 0 1 0 0 0 1 0
BL
2
0 0 1 1 0 0 1 1 3
0 1 0 0 0 1 0 0 4
0 1 0 1 1 0 1 1 5
0 1 1 0 1 1 0 0 6
0 1 1 1 1 1 0 1 CMOS Inverters
7
1 0 0 0 1 1 1 0 8 In 2 Inverters, output of the 1st Inverter is
1 0 0 1 1 1 1 1
1 0 1 0    
9 connected to Gate Input of 2nd Inverter and
1 0 1 1     vice versa.
1 1 0 0    
1 1 0 1    
06. Ans: (c)
1 1 1 0     Sol: SRAM is relatively high speed memory that
1 1 1 1     stores the most recently used instructions
 It is preferred when the requirement is of
The outputs are in 2 4 2 1 BCD number lower access time.
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: 18 : Digital & Microprocessors

07. Ans: (b)

Sol: SRAM : This contains conventional storage like latches (BJT or MOSFET) and has both Read
and Write operation.
ROM : This contains conventional storage like latches (BJT or MOSFET) and it is non volatile.
PLA : This contains a set of AND, OR and INVERT logic gates and can be programmed.
DRAM : This contains only MOSFET’s and needs periodic refreshing.

08. Ans: (d) 09. Ans: (a)

Sol: SRAM is more expensive and less dense Sol: In DRAM the bit is stored as a charge in
than DRAM and is therefore not used for capacitor, and it is made up of MOS
high capacity, low - cost applications such transistors.
as main memory in personal computers.

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Chapter

01. Ans: (b)

8 A/D & D/A Converters

V0 = Ii R = 
5I
 10k 
Sol: 16
CLK Counter Decoder V0  5 110 3 10 10 3
Q2 Q1 Q0 D3 D2 D1 D0 = = 3.125V
16
1 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 1 1 04. Ans: (d)
3 0 1 0 0 0 1 0 2 3
4
5
0 1 1
1 0 0
0 0 1
1 0 0
1
0
3 Sol: Given that VDAC = 2 n 1
b n Volts
8 n 0
6 1 0 1 1 0 0 1 9 VDAC = 2 1 b 0  20 b1  21 b 2  2 2 b 3
7 1 1 0 1 0 1 0 10
8 1 1 1 1 0 1 1 11  VDAC = 0.5b0 + b1 + 2b2 + 4b3

Initially counter is in 0000 state

02. Ans: (b) Up VDAC(V) o/p of
Sol:
R R R 2R counter o/p comparator
VR
b3 b2 b1 b0
I/2 I/4 I/8 I/16
0 0 0 0 0 1
2R 2R 2R 2R 0 0 0 1 0.5 1
0 0 1 0 1 1
0 0 1 1 1.5 1
0 1 0 0 2 1
Requ = (((((2R||2R)+R)||2R)+R)||2R)+R)||2R) 0 1 0 1 2.5 1
0 1 1 0 3 1
Requ = R = 10k  . 0 1 1 1 3.5 1
1 0 0 0 4 1
VR 10V 1 0 0 1 4.5 1
I= = = 1mA.
R 10k 1 0 1 0 5 1
1 0 1 1 5.5 1
I 1 1 0 0 6 1
Current division at
16 1 1 0 1 6.5 0
110 3
= = 62.5  A
16 When VDAC = 6.5 V, the o/p of comparator
is ‘0’. At this instant, the clock pulses to
the counter are stopped and the counter
03. Ans: (c)
remains in 1101 state.
Sol: Net current at inverting terminal,
I I 5I  The stable reading of the LED display
Ii = + = is 13.
4 16 16
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05. Ans: (b) 08. Ans: (d)

Sol: The magnitude of error between VDAC & Vin Sol: Ex: fin = 1 kHz  fs = 2 kHz
at steady state is VDAC  Vin = 6.5  6.2 fin = 25 kHz  fs = 50 kHz

= 0.3 V 1. Max conversion time = 2N+1T = 211.1 s

= 2048 s
06. Ans: (a)
2. Sampling period = Ts  maximum
Sol: In Dual slope
conversion time
ADC  Vin T1  VR .T2
Ts  2048 s
VR T2 1 1
 Vin  3. Sampling rate fs = 
T1 Ts 2048 10 6
100 mV  370.2 ms fs  488 fs  500 Hz

300 ms
fs
DVM indicates  123.4 4. fin =  250 Hz
2

07. Ans: (d) 09. Ans: (b)

Sol: R
Sol: No. of bits = 8,
Vin
Reference voltage = 8V Vin1  T Vin V in1
RC eq Ceq

Counter
1
Vin1 has to settle down within LSB of full
2
1 1 1 1 0 0 0 0 scale value.
509 Vin .T
i.e Vin 
510 75  (255  8  10 12 )
4 bits are driven 4 bits are grounded 509
 T  (75  255  8  10 12 ) 
510
Maximum peak to peak amplitude of the
T  0.15 sec
waveform at the output of the digital to Thus sample period Ts  T
analog converter is Ts  0.15 m sec
1
f s max 
V
Vmax = ref
n
d n 2n   Ts ,min
2
8 1
=  240  Hz
256 0.15 10 6

 7 .5 V  6 Megasamples
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10. Ans: (a) 13. Ans: (a)

Sol: Dual-slope A/D converter is the most Sol: The output of an 8-bit A to D converter is
preferred A/D conversion approach in 40H for an input of 2.5V.
digital multimeters. ADC has an output range of 00 to FFH for
Dual-slope A/D converter provides high an input range of 5V to +5V.
accuracy in A/D conversion, while at the Both Statements are true and statement-II is
same time suppressing the hum effect on the the correct explanation of statement-I.
input signal.
Both Statements are true and statement-II is 14. Ans: (c)
the correct explanation of statement-I. Sol: Digital ramp converter is the slowest ADC.
Conversion time for digital ramp ADC is not
11. Ans: (d) N2T.
Sol: SAR type ADC : Settling time for n-bits is 15. Ans: (b)
(n+2) T clock pulses Sol: Resolution for n-bit A/D converter in
Flash ADC : (2n–1) comparators percentage.
required for n-bit dual 1
Dual slope ADC : Works well even in noisy  n 100
environment 2 1
Counter DAD : Settling time dependent 1
 12 100
on the input 2 1
12. Ans: (c)  2.443  104  100
Sol: Dual slope ADC Hum : rejection  0.02441
approximation
Counter-ramp ADC : Conversion time
dependent on
single amplitude
Successive ADC : Fixed conversion
time, depends on
the number of bits
Simultaneous ADC: High speed operation

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Chapter

01. Ans: (a)

9 Architecture, Pin Details of 8085
& Interfacing with 8085

A15 A14 A13 A12 A11 - - - - - A0

Sol: chip select is an active low signal for 1 1 1 0 0-------0 =E000H
chipselect  0 ; the inputs for NAND gate
must be let us see all possible cases for
chipselect  0 condition

A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 X X
0 0 1 1 0 0 X X 1 1 1 0 1 - - - - - - - - 1 =EFFFH
0 1 0 1 0 0 X X 02. Ans: (d)
0 1 1 0 0 0 X X  60H (A1A0=00) Sol:
1 0 0 1 0 0 X X  Both the chips have active high chip
1 0 1 0 0 0 X X select inputs.
0 0 0 0 1 1 X X  Chip 1 is selected when A8 = 1, A9 = 0
0 0 1 1 1 1 X X Chip 2 is selected when A8 = 0, A9 = 1
0 1 0 1 0 0 X X  Chips are not selected for combination
0 1 1 0 0 0 X X 63H(A1A0=11) of 00 & 11 of A8 & A9
1 0 0 1 0 0 X X  Upon observing A8 & A9 of given
1 0 0 0 0 0 X X address Ranges, F800 to F9FF is not
represented
The only option that suits hare is option(a)
03. Ans: (d)
Sol: The I/O device is interfaced using “Memory
A0 & A1 are used for line selection Mapped I/O” technique.
The address of the Input device is
A2 to A7 are used for chip selection A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A2 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 =F8F8H
1
The Instruction for correct data transfer is
A3 0
= LDA F8F8H
1
A4 0
0 04. Ans: (b)
1 1 Chip select  0
A5 Sol:
 Out put 2 of 38 Decoder is used for
A6 1 selecting the output port. Select code
0
0 is 010
A7 A15 A14 A13 A12 A11 A10 -- A0
0 1 0 1 0 0 --- - 0
 Address space is 60H to 63H
 5000H
Ao to A11 are used for line selection  This mapping is memory mapped I/O
A12 to A15 are used for chip selection
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05. Ans: (d)

Sol:
A15 A14 A13 A12 A11 A10 A9 - - - - A0
0 0 0 0 1 0 0----0 =0800H

0 0 0 0 1 0 1----1 =0BFFH

0 0 0 1 1 0 0----0 =1800H

0 0 0 1 1 0 1----1 =1BFFH

0 0 1 0 1 0 0----0 =2800H

0 0 1 0 1 0 1----1 =2BFFH

0 0 1 1 1 0 0----0 =3800H

0 0 1 1 1 0 1----1 =3BFFH

06. Ans: (a)

Sol: Address Range given is
cs

13 8 kB
ROM
A12  A0

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1000H  0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2FFFH  0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

To provide cs as low, The condition is

A15 = A14 = 0 and A13 A12 = 01 (or) (10)
i.e A15 = A14 = 0 and A13 A12 shouldn’t be 00, 11.
Thus it is A15 + A14 + [A13A12 + A13 , A12 ]

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07. Ans: (a)

Sol:
A15

A13
A12 3:8
A11 Decoder

A14
A15, A14 are used for chip selection
A13, A12, A11 are used for input of decoder

A15 A14 A13 A12 A11 A10 ------ A0

Enable of Input of decoder Address of
decoder chip

Size of each memory block = 211 = 2K

08. Ans: (a) 10. Ans: (a)

Sol: The data path contains all the circuits to Sol: A processor can reference a memory stack
process data within the CPU with the help of without specifying an address.
which data is suitably transformed. The address is always available and
It is the responsibility of the control path to automatically updated in the stack pointer.
generate control and timing signals as Both Statements are true and statement-II is
required by the opcode. the correct explanation of statement-I.
Both Statements are true and statement-II is
the correct explanation of statement-I. 11. Ans: (c)
Sol: The programmer has to initialize the stack
09. Ans: (b) pointer based on design requirements.
Sol: Program counter is a register that contains 12. Ans: (b)
the address of the next instruction to be Sol: The DMA technique is more efficient than
executed. the Interrupt-driven technique for high
volume I/O data transfer.
IR (Instruction Register) is not accessible to
programmer. The DMA technique does not make use of
the Interrupt mechanism.
Both Statements are true but statement-II is Both Statements are true but statement-II is
not correct explanation of statement-I. not correct explanation of statement-I.
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13. Ans: (c) 14. Ans: (d)

Sol: A microcontroller has onchip (inbuilt) Sol: INTR is a non vectored interrupt. As such
memory, where as a microprocessor has no external hardware is required to supply
such internal memory. vector address. SIM is not used with respect
The program to be run by microprocessor is to INTR. The SIM is used for selective local
to be store in separate memory (E2PROM) masking of three hardware maskable
chip and to be interfaced microprocessor. vectored interrupts (RST 7.5, RST 6.5,
RST 5.5)

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Chapter 10 Instruction set of 8085 &
Programming with 8085
01. Ans: (c) ORI 40H ; A  40H
Sol: A = 40H
6010H : LXI H,8A79H ; (HL) = 8A79H ADD M ; 40H + 20H = 60H
6013H : MOV A, L ; (A)(L) = 79
6014H : ADD H ; (A) = 0111 1001
+ 04. Ans: (c)
; (H) = 1000 1010 Sol: SUB1 : MVI A, 00H A← 00H
; (A) = 0000 0011 CALL SUB2  program will shifted to
CY = 1, AC = 1 SUB 2 address location
A
6015H : DAA ; 66 Added to (A) SUB 2 : INR A 
since CY=1 & 01H
AC =1
; (A) = 69H RET  returned to the main program
6016H : MOV H,A ; (H)(A) =69H  The contents of Accumulator after
6017H : PCHL ; (PC)(HL) = 6979H execution of the above SUB2 is 02H

02. Ans: (c) 05. Ans: (c)

Sol: 0100H : LXI SP, 00FFH ; (SP) = 00FFH Sol: The loop will be executed until the value in
register equals to zero, then,
0103H : LXI H, 0107 H ; (HL) = 0107H
Execution time
0106H : MVI A, 20H ; (A) = 20H
=9(7T+4T+4T+10T)+( 7T+4T+4T+7T)+7T
0108H : SUB M ; (A)(A)-(0107)
; (0107) = 20H = 254T
; (A) = 00H
The contents of Accumulator is 00H
06. Ans: (d)
Sol: H=255 : L = 255, 254, 253, ----0
03. Ans: (c)
Sol: LXI SP, 00FFH ; (SP) = 00FFH H=254 : L = 0, 255, 254, -------0
|
LXI H, 0107 H ; (HL) = 0107H
H=1 : L = 0,255,254,253,---0
MVI A, 20H ; (A) = 20H
H=0 :
SUB M ; (A)(A) – (0107)
 In first iteration (with H = 255), the value in
; (0107) = 20H = M L is decremented from 255 to 0 i.e., 255
; (A) = 00H times

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 : 27 : Postal Coaching Solutions

 In further remaining 254 iterations, the 09. Ans: (c)

value in L is decremented from 0 to 0 i.e., Sol: If the content in register B is to be
256 times multiplied with the content in register C, the
 ’DCRL’ instruction gets executed for contents of register B is added to the
 [255  (254  256)] accumulator (initial value of accumulator
is 0) for C times.
 65279 times
10. Ans: (c)
07. Ans: (a) Sol: Push takes 12T states due to pre decrement
Sol: “STA 1234H” is a 3-Byte Instruction and it and pop takes 10T states.
requires 4 Machine cycles (Opcode fetch,
Operand1 Read, Operand2 Read, Memory 11. Ans: (d)
write). The Higher order Address (A15 – A8) Sol:
sent in 4 machine cycles is as follows CY
Given A = A7H = 10100111 0
Given “STA 1234” is stored at 1FFEH
After executing RLC  A = 01001111 1
i.e., Address Instruction A = 4FH and cy = 1

1FFE, 1FFF, 2000 : STA 1234H

12. Ans: (b)
Machine Address Higher order Sol: OUT: output data from accumulator to a
cycle (A15-A0) address port with 8-bit addresses. The contents of
(A15-A8) the accumulator are copied into the I/O
1. Opcode 1FFEH 1FH ports specified by the operand.
fetch IN: Input data to accumulator from a port
2. Operand1 1FFFH 1FH with 8-bit address. The contents of the input
Read port designated in the operand are read and
3. Operand2 2000H 20H loaded into the accumulator.
Read
4. Memory 1234H 12H 13. Ans: (a)
Write Sol: When RET instruction is executed by any
i.e. Higher order Address sent on A15-A8 for subroutine then the top of the stack will be
popped out and assigned to the PC.
4 Machine Cycles are 1FH, 1FH, 20H, 12H.
14. Ans: (b)
08. Ans: (d) Sol:
PUSH PSW  1 Byte instruction
Sol: The operation SBI BEH indicates
A-BE  A where A indicates accumulator  OPFC + 2T + MW1C + MW2C
Thus the result of the subtraction operation  Special OPFC + MW1C + MW2C
is stored in the accumulator and the contents
of accumulator are changed.  3 Machine cycles
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15. Ans: (c) 20. Ans: (a)

Sol: Flags are not affected for execution of data Sol: Total no. of machine cycles in CALL
transfer instructions since there is no instruction is 18.
involvement of ALU 1. Opcode fetch=6T
2. Two memory READ machine cycles to
16. Ans: (a) read subroutine address = 3T + 3T = 6T
Sol: Immediate addressing : LXI H, 2050H 3. Two memory WRITE machine cycles on
Implied addressing : RRC the stack = 3T + 3T = 6T
Register addressing : MOV A,B  I/O was not used in CALL instruction
Direct addressing : LDA 30FF
21. Ans: (d)
17. Ans: (c) Sol: PCHL : Transfer the contents of HL to the
Sol: ‘DAD’ instruction adds contents of HL program counter.
register pair with specified register pair SPHL : Transfer the contents of HL to the
contents and stored in HL register pair. stack pointer
XTHL : Exchange the top of the stack with
18. Ans: (a) the contents of HL pair
Sol: Format of instruction Template:-
XCHG : Exchange the contains of HL with
Label Mnemonics operand comments those of DE pair

19. Ans: (b)

Sol: Implicit addressing mode
: RAL
Register-indirect addressing mode
: MOV A, M

Immediate addressing mode

: JMP 3FAOH
Direct addressing mode
: LDA 03FCH

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 11 8086 Microprocessor

Chapter

01. Ans: (c) 02. Ans: (c)

Sol: 16-bit microprocessor has more speed and Sol: In case of a 16-bit processor, a single
more data handling capability compared to instruction is enough to process a function.
8-bit microprocessor. For processing the same function a long
sequence of instructions will be required for
a 8-bit processor.
03. Ans: (c)
Sol:
 8086 p has 20 Address output lines. As such, a total of about 220 i.e., 1MB memory can be
directly addressed by 8086 P
 The programming model of 8086 P has the following registers
AX, BX, CX, DX
CS, DS, SS, ES
Flag registers: SP, IP, BP, SI, DI i.e., a total no. of 14 registers
 There are total 9 flags in 8086 p and the flag register is divided into two types.
(a) Status flags: The six status flags are
1. Sign flag (S)
2. Zero flag (Z)
3. Auxiliary carry flag (AC)
4. Parity flag (P)
5. Carry flag (CY)
6. Overflow flag (O)
(b) Control flags: The three control flags are
1. Directional flag (D)
2. Interrupt flag (I)
3. Trap flag (T)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
O D I T S Z AC P CY
Fig: Format of flag register

04. Ans: (c) 05. Ans: (b)

Sol: Setting Trap flag puts the processor into Sol: For 8086 µP, the jump distance in bytes for
single mode for debugging. In single short jump range is forward 127 and
stepping microprocessor executes an backward 128.
instruction and enters into single step ISR. If
TF = 1, the CPU automatically generates an 06. Ans: (a)
internal interrupt after each instruction, Sol: Number of address lines in 8086 is
allowing a program to be inspected as it 20.Address space is 220 = 1MB
executes instruction by instruction.
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 : 30 : Postal Coaching Solutions

07. Ans: (d) 14. Ans: (a)

Sol: The instruction queue length in 8086 is Sol: For a type 0 interrupt, the 8086 pushes the
6 bytes and in 8088 is 4 bytes. flag register on the stack, resets IF and TF
and pushes the return addresses on the stack.
08. Ans: (d)
Sol: 8086 microprocessor can be operated 15. Ans: (c)
in multiprocessor configuration when Sol: The interrupt vector table IVT of 8086
MN/ MX input connected to ground. contains the starting CS and IP values of the
interrupt service routine.
09. Ans: (d)
Sol: A 16 bit P completes access of a word 16. Ans: (d)
starting from even address in one bus cycle. Sol: The 8086 arithmetic instructions work on
Signed and unsigned numbers Unpacked
10. Ans: (b) BCD data
Sol: In relative base indexed Addressing mode,
the 20 bit physical address of Data segment 17. Ans: (c)
location is calculated as followed. Sol: LOOP and ROTATE instructions of an 8086
P.A = (D.S register)10H + (B register) p uses the contents of a CX register as a
+ (DI register) + 16 bit displacement counter.
= 2100H10H + 0158H + 1045H
18. Ans: (c)
+ 1B57H
Sol: In a multi-processor configuration, the two
= 21000H + 2CF4H
co-processor instruction sets must be
= 23CF4H
disjoint.
11. Ans: (a)
Sol: Effective Address = (C.S reg)10H 19. Ans: (b)
+ (IP reg) Sol: MOV [1234 H], AX
= 1FABH  10H + 10A1H Move the contests of register AX to memory
= 20B51H offset 1234 H and 1235 H.

12. Ans: (c)

Sol: SI is the source index, used as a pointer to
the current character being read in a string
instruction. It is also available as an offset to
add to BX or BP when doing indirect
addressing.
DI is the destination index, used as a pointer
to the current character being written or
compared in a string instruction. It is also
available as an offset.

13. Ans: (b)

Sol: The intermediate wait states are always,
inserted between the clock cycles T2 and T3.

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 12

Microcontroller
Chapter

01. Ans: (c) 06. Ans: (c)

Sol: Out of the 128-byte internal RAM of the Sol: RAM memory space allocation in the 8051
8051, only 16 bytes are bit-addressable. The
bit-addressable RAM locations are 20H to 7F
2FH
30 Scratch pad RAM
2F
02. Ans: (a)
Sol: The internal RAM size is 128 bytes and
internal ROM size is 4KB. 20 Bit addressable RAM
1F
03. Ans: (a)
18 Register Bank 3
Sol: In the 8051, the stack pointer points to the
last used location of the stack. As we push 17
data onto the stack, the stack pointer is Register Bank 2
incremented by one. 10
0F
04. Ans: (c)
08 Register Bank 1
Sol:
(A) = 9CH = 1001 1100 07
Register Bank 0
+64H = 0110 0100
00
0000 0000
AC = 1 since there is a carry from bit D3 to
bit D4 07. Ans: (d)
Sol: The given question is in incorrect format.
CY = 1since there is a carry from bit D7 The question is: On power UP, the 8051 uses
P = 0 since there are zero 1s in result i.e., RAM location _____ for register R0.
Even Parity. The answer is 08H.

05. Ans: (c)

Sol: ORG is a Assembler directive that directs the
assembler to store the program code from
2000H.
This will not be converted into machine
code.

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 13 Embedded Systems

Chapter

01. Ans: (b) 03. Ans: (d)

Sol: A real time embedded system is defined as, Sol: When selecting a processor in an embedded
a system which gives a required output in a system one should take instruction set,
particular time. These types of embedded processor ability and max bits in the operand
systems follow the time deadlines for into consideration.
completion of a task.
So, Microwave oven is a real time 04. Ans: (a)
embedded system. Sol: The Inter-integrated circuit (I2C) is a
protocol intended to allow multiple slave
02. Ans: (b) digital integrated circuits (chips) to
Sol: A system on chip (SOC) is an integrated communicate with one or more master
circuit commonly applied in the area of chips.
embedded system.

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