DFT

for
Embedded Memory
10/20/2010

Sangmin, Bae
Sangmin
DFX Group
IDC, System LSI,
Samsung Electronics Co,
Co Ltd

Samsung Property
 Contents
» Introduction
• Environments and Scopes

» Technical Items
• Integration complexity
• MBIST design consideration
• Design flow consideration
• Repair and ECC

» More Technical Items

» Summary

Samsung Property 2
 Introduction
» Status on eMemory Testing
• Driver
» Complex,
Complex advanced design flow with limited TAT
• Design capacity : Mega SOC, near NoC product
» Hierarchical, modular design flow
• Advanced
Ad anced low-power
lo po e design techniq
techniquee
• Design reuse : Heterogeneous IP integration

» Rapid
R id process migration
i i iinto nano-technology
h l
• Performance gain and yield goal is more challenging than before
• Reliability, test escape reduction
• Bit-cell engineering requires efficient channel for si. analysis

» Well tuned DFx technique

• Typically, DFT resources are re-purposed for DFx
» Productivity, Reliability, Debug, etc.

Samsung Property 3
 Introduction
» Scope and limitation on eMemory Testing
• Typically, memory is not fully controllable and we have
fewer knobs than logic dft (scan) technique.
technique

• Memory
y BIST
» MBIST is classical and well-defined technique, but most of
eMemory design and test issues are tightly coupled with DFT
logic
g ((MBIST).
) So,, re-visiting
g of MBIST is still occurred

» Not easy to maintain current through-put within the previous

DFT resource (test cost,
cost H/W area)
• Providing flexible MBIST automation tool is not sufficient

• SiP, TSV testing is still challenging area in the real action

» Evolution of existing technique is not sufficient

Samsung Property 4
 Integration Complexity
» Difficulty on SRAM Tests
• Layout is more crucial compare with logic std. cell
• Each 6 tr. has veryy strongg relationshipp:
» Trade-off exists between area, performance, yield
• Bit-cell array and peri. circuit is controlled by self-timed logic
• SRAM configuration widely varies on their usages
• Most SRAM are deeply embedded in a chip
• MBIST just do functional test on SRAMs

Ro
ow-Decoder

Column mux +
Sense Amp

Samsung Property 5
 Integration Complexity
» Who is DFT player?
• Example : test lvcc problem

Vector and screening condition Test eng’r

IO + package spec. IP or package eng’r
full-chip
full chip level DFT planning SoC DFT
power-clock network design’r

Design methodology +
FE/BE
Sign-off rules
eng’rr
eng MBIST
eng’r
SRAM core

6T bit-cell w/ Process
SNM DNM
SNM, eng’rr
eng

+ peri. design
w/ self-timing SRAM
margin designer

Samsung Property 6
 Integration Complexity
» Memory BIST Limitation
• Typically, MBIST is implemented on ASIC flow
» Test is based on functional test
» Without memory changes, very difficult to obtain useful knobs on test
• Example : Controlling clock skew between multi-port memories
» Each type could requires extra implementation overhead
• Sacrifice parallelism for area reduction
• Poor resolution
• Pattern development difficulties
» ROI pperspective
p : Trade-off b/w
/ implementation
p efforts and TAT

BIST BIST BIST BIST

A B

direct
mem. control
mem. 0 1 mem. clock
1 0 0 1
Port A
Port B 1 0

A Type B Type
C Type

Samsung Property 7
 Integration Complexity
» MBIST complexity
• Increased memory counts
» Hierarchical/multi-step generation and insertion capacity
» Redundancy strategy
• Multiple power-domain and various power-gating scheme
» Repair-information distribution
» Test
T condition
di i controll iin multiple
l i l voltage
l llevell
• Light-weight clock-domain crossing control is required
» JTAG is just simple std. SoC JTAG Top controller w/ repair
» Programmability control IP i/f
function block
IP i/f

» Redundancy information handling mbist mbist mbist

mbist

» Solution approaches mbist

mbist
mbist
Block A
• JTAG + IEEE1500 interface IP i/f
mbist
with tricky interface blocks mbist
Block C

• MBIST insertion variation IP i/f

» GL vs. RTL insertion Big hard-macro IP

inc. memories
Block B
• Hierarchical test-bus
Typical SoC MBIST Architecture

Samsung Property 8
 Memory BIST Design
» Memory BIST Design
• MBIST using HDL based ASIC flow
» Common features :
• Programmable, at-speed fail-bit map
• High-speed option : PLL, data-path pipelining, FSM design

• MBIST generator : easily adapted and deployed in industry

» Script or GUI based input form : memory and MBIST lib. format
» Based
ased on
o configurable
co gu ab e and
a d parameterized
pa a e e ed template
e pa e
» IDE fasten DK iteration : planning, insertion, verification

• Several consideration : mainly automation and flow issues

» Customization can not be avoidable
• Different DFT budgets and targets by different customer
• Clock scheme,
scheme and scan mode isolation
» Seamless automation flow requires continuous efforts
• Hard to be properly hidden during implementation flow
» Timing closure,
closure STA,
STA Verification

Samsung Property 9
 Design Flow Consideration
» RTL vs. GL MBIST Flow
• TAT is a main driving factor : IP and tools status
• Selection could different depends on design-flow and tool-chain
• It mainly depends on other constraints, not by MBIST
» HDL interface capability is mandatory
» No leading/full
g/ standards exists
• JTAG + IEEE1500 style is very popular but, loose standards

RTL design planning

Top-level
l l integration
IP integration
Logic- synthesis

Scan Synthesis ECO & verification

Timing closure
flow automation
Boundary Scan

EDA tool integration

Simple Concept
Complex Execution

Samsung Property 10
 Si. Diagnosis of SRAM
» eMemory Si. Diagnosis
• eMemory Si. diagnosis motivation
» Low yield, poor device characteristics, test escape, etc.

• Several approaches
pp
» Initial statistical analysis
» Extract exact fail bit-map
» Parametric analysis using memory operation mode
» MBIST logic fails
• Typically, detected by design verification review and
work-around
work around can be exists

» Test escape
• Re producing fail on DFT@ATE test is technical goal
Re-producing
• Main barrier : lacks of fail modeling and MBIST flexibilities
• Diagnosis time is most important

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 Programmable MBIST
» Programmable MBIST
• Flexibility depends on structures
» FSM-based
FSM based
» ALPG like (micro-code based)
» Extension of general micro-controller ISA w/ custom module

• Needs of programmable MBIST

» Control of complex memory IP : eDRAM, KGD(SiP, TSV)
» Si.
Si diagnosis
diagnosis, repair analysis : diagnostic pattern,
pattern repair analysis

• Pattern level programmability seems to be not sufficient

» ALPG ((mini.
i i memory ATE) approaches
h iis popular
l
» Pattern development costs
» Well defined flexible ISA

• ATE or on-chip control interface is one of issues

» JTAG or AMBA-bus based
» Vector and simulation flow is required

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 Repair and ECC
» General Memory Redundancy Scheme
1D Redundancy 2D (Row/Column) Hier. Redundancy
Redundancy
Redundancy

1D Redundancy 2D Redundancy 2.5D Redundancy

Red. Type Single (Row / Column / IO) Row + Column (Row + Column) * M
# of Red. N 2N 2N * M
BIRA Simple Medium Complex

Samsung Property 13
 Repair and ECC
» Typical MBIST structure on SOC
• Top DFT controller inc. JTAG interface
• Local Memory BISTs
• Fuse related logic for repair

» Features on MBIST design

• Memory isolation and clocking scheme
• Interface between Top DFT controller and Local BIST logics
• Repair policy and repair
repair-bus
bus structure

Wrapper Wrapper Wrapper

IEEE 1500
JTAG or custom control
Top DFT
JTAG Controller BIST SRAM SRAM
...
Repair Analysis
SRAM
Fuse
Related Serial or Parallel Bus
Controller Repair Address Repair Address

General MBIST Structure

Samsung Property 14
 Repair and ECC
» ECC
• Typically, SRAM ECC regarded as having big-overhead technique
» Area, timing overhead
» Increase complexities of test condition and repair flow
• Popular ECC code : SEC-DED, SEC-SED
• Architectural approaches are trends for eMemory ECC
» Combined with redundancy and other design constraints/techniques

Samsung Property 15
 Memory Test Bus
» Memory Test Bus Motivation
i i
• Traditional memory isolation and MBIST insertion are can be
performance, implementation TAT intrusive
• Well-defined
W ll d fi d and d fi
find-grain
d i ttest-bus
t b protocol
t l will
ill catch
t h both
b th performance
f
and DFT productivity goals
• Current MBIST solution is not suitable for this kind of approaches
• Early stage of its adaption on several IPs
Pre-designed Re-configurable IP

repair interconnection Serial F/F

epair-
us
Bu
Re

Instance
Memory
Memory
Instance
Configurable

stance
stance

emory
emory
Memory
BIST Instance

Ins
Ins

Me
Me
Instance
e
or

Memory
Memory
BIRA Instance
est-Bus

w/o

Memory F/F normal memory bus normal memory bus

Memory Te

normal memory bus F/F F/F

BIST vs. Memory Interconnection

Samsung Property 16
 MBIST Planning and Test Scheduling
» Backgrounds
•For multiple MBISTs in a chip, how to merge/split MBIST(s)?
• Trades-off is exists (
(accuracy
y or q
q&d solution))
» Approaches Candidates
• Memory BIST grouping/scheduling automation
» Both,, spec.
p and run-time level required
q
» Should consider BIST generation, pattern, repair
• Run-time scheduling flow should reflect other constraints
» ATE interface overhead
» Diagnosis
» Flow Considerations
• Accuracies
Peak
Power
Run #1 Run #2 Run
u Run
» Average vs. peak power based #3 #4

» Clock skew and timing dependency

» P&R floor-planning back-annotation
» Memory operations
• Capacities Test
Time
» MILP or graph-based solver
» Graph
Graph-based
based : bin
bin-packing
packing problem

Samsung Property 17
 More Technical Items
» Several topics on eMemory DFT
• Bit-cell related
» Reliability and manufacturability issues
• NBTI, Hot-carrier, TDDB

• Memory related
» Multi-port
Multi port memory related
» Parametric diagnosis structure
» Memory test-assist function support
g
» Design-assist function using
g BIST/BIRA
/ resource

• BIST-BIRA related
» BISR(self-repair)
• Repair analysis algorithm
• fuse-compress and repair-bus structure
» BIST/BIRA planning and scheduling
• Shared BIST or hierarchical BIST architecture
• BIST/BIRA planning w/ design constraints
» TSV, SiP memory test support

Samsung Property 18
 Summary
» DFT for Memories
• Memory BIST for eSRAM
» On
On-product
product diagnostic features in mass volume
» Fluent and flexible design flow
• Memory BIST for SiP, TSV
» KGD test is still challenging on real execution
• Memory BIST for DFx
» Basic infra structure for eSRAM DFT

» Technical requirements on current MBIST

• Well-designed
g memory y test-bus
• Matured programmable MBIST for SiP, TSV
• Latest full-chip DFT architecture compliance

Samsung Property 19