Module-2 Combinational Logic Circuits

Module-2
Chapter 1: The Basic Gates

1.1 Review of Basic Logic gates

1.2 Positive and Negative Logic

1.3 Introduction to HDL

Chapter 2: Combinational Logic Circuits

2.1 Sum of products Method

2.2 Truth table to Karnaugh Map

2.3 Pairs, Quads, and Octets

2.4 Karnaugh Simplifications

2.5 Product of Sums Method

2.6 Product of sums Simplifications

2.7 Simplification by Quine-Mc Clusky Method

2.8 Hazards and Hazard Covers

2.9 HDL Implementation Models

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1.1 Review of Basic Gates:

Logic Gate:

A digital circuit having one or more input signals but only one output signal is called gate

Basic Logic gates:

1. NOT gate

2. OR gate

3. AND gate

OR Gate:

• It has two or more input signals but only one output signal

• Output is high if any or all the inputs are high.

Symbol:

Y=A+B

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Truth Table: Pin-out Diagram:

Three- input OR gate:

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Universal Logic Gate:

• A gate which can implement any Boolean function is called Universal gate
• Universal gate can be used to construct all other logic gates
1. NOR

2. NAND

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De Morgan’s Theorem:

1. A + B = A B

2. AB = A + B

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1.2 Positive and Negative Logic:

Positive Logic: Use Binary 0 for Low voltage and binary 1 for High Voltage

LOW 0
HIGH 1

Negative Logic: Use Binary 0 for High voltage and binary 1 for Low voltage

LOW 1
HIGH 0

Problem: Prove Positive OR is equal to Negative AND

OR gate Truth table: OR gate truth table in Positive Logic:

A B Y
A B Y
LOW LOW LOW 0 0 0
LOW HIGH HIGH 0 1 1
HIGH LOW HIGH 1 0 1
HIGH HIGH HIGH 1 1 1

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AND gate Truth Table: AND Gate in Negative Logic

A B Y A B Y
LOW LOW LOW 1 1 1
LOW HIGH LOW 1 0 1
HIGH LOW LOW 0 1 1
HIGH HIGH HIGH 0 0 0

OR gate in Positive Logic ↔ AND gate in negative Logic

LIST of equivalences between gates:

Positive OR ↔ Negative AND

Positive AND ↔ Negative OR
Positive NOR ↔ Negative NAND
Positive NAND ↔ Negative NOR

1.3 Introduction to HDL

HDL (Hardware description Language): it is computer language used to describe Hardware

Advantages of HDL:

• Describes large complex hardware in a convenient manner, in a smaller space.

• Use Software tool to detect functional errors, if any errors, correct the errors, this is
process is called Simulation.
• Get hardware implementation details, this is called synthesis
There are two HDLs

1. Verilog HDL
2. VHDL (very high speed integrated circuit HDL)
Verilog HDL:
• Verilog HDL is more popular
• Ii was introduced in 1980, as a simulation tool by Gateway Design Automation.
Describing Input/ Output:
• Any digital circuit, there are set of inputs and set of outputs.
• Inputs and outputs are called as ports.

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Structure of Verilog HDL:

Module: it is a keyword used to describe module name and input output port list
Input : keyword used to declare the input ports
Output : keyword used to declare output ports
Endmodule: keyword to end the module, semicolon is not used for endmodule
//  single line comments
/* */  multi-line comments
Writing Module Body:
• Module body describes the logic of the circuit
• There are three different models to write the module body
1. Structural Model
2. Data flow Model
3. Behavioral Model
Keywords used to define gates in Structural model:
1. and
2. or
3. not
4. nand
5. nor
6. xor
7. xnor

Syntax for 2 input OR gate: or (output, input1, input2)

Syntax for Not gate: not (output, input)

Write Verilog structural code for two inputs OR gate.

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module or_gate(A,B,Y);
input A,B; // defines two input port
output Y; // defines one output port
or (Y, A, B); // keyword or declares OR gate
endmodule

Data flow Model:

This model uses assign keyword and set of operators to write module body

List of operators used in Verilog HDL:

Relational operation Symbol Bit-wise Operation Symbol

Less than < Bit-wise NOT ~
Greater than > Bit-wise AND &
Equal to == Bit-Wise OR |
Not equal to != Bit-wise Ex-OR ^

Logical Operation Symbol Arithmetic Operation symbol

(for expression)
Logical NOT ! Binary addition +
Logical AND && Binary subtraction -
Logical OR || Binary multiplication *
Binary Division /

Write Verilog Dataflow code for two inputs OR gate

module or_gate(A,B,Y);
input A,B; // defines two input port
output Y; // defines one output port
assign Y=A | B;
endmodule

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Behavioral Model:

 In this model, statements are executed sequentially

 It uses always keyword followed by sensitivity list
 Output variables within always must be declared by using keyword reg before always
statement

Write Verilog Behavioral code for two inputs OR gate

module or_gate(A,B,Y);
input A,B; // defines two input port
output Y; // defines one output port
reg Y;
always @ (A or B) // A, B is sensitivity list
if ( (A==1) || (B==1))
Y=1;
else
Y=0;
Endmodule

Program: Write Verilog structural code, Data –flow code and Behavioral code for the
figure shown below

fig_a

Structural Code:
module fig_a(A,B,C,D,Y);
input A, B, C, D;
output Y;
wire and_op1, and_op2; // internal connections
and g1(and_op1, A, B); // g1 is upper AND gate
and g2 (and_op2, C, D); // g2 is lower AND gate
or g3(Y, and_op1, and_op2); // g3 is OR gate
endmodule

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Data-Flow Code:

module fig_a(A,B,C,D,Y);
input A, B, C, D;
output Y;
assign Y = (A&B) | (C&D);
endmodule

Behavioral Code:

module fig_a(A,B,C,D,Y);
input A, B, C, D;
output Y;
reg Y;
always @ (A or B or C or D)

if( ( A==1) && (B==1))

Y=1;
else if (( C==1) && (D==1))
Y=1;
else
Y=0;
endmodule

Program: Write Verilog structural code and data flow code for the following circuit

Structural Code:
module testckt(a,b,c,x,y);
input a,b,c;
output x,y;
wire or_op1, or_op2; // internal connections
or g1 (or_op1, a,b); // g1 is upper OR gate
or g2 (or_op2, b,c); // g2 is lower OR gate
nor g3(x, c, or_op1); // g3 is NOR gate
nand g4 (y, or_op1, or_op2); // g4 is NAND gate
endmodule

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Dataflow code:

in the above circuit, x= (a+b) + c y = (a+b) (b+c)

module testckt(a,b,c,x,y);
input a,b,c;
output x,y;
assign x= ~((a | b) | c);
assign y= ~ ((a | b) & (b | c));
endmodule

Program: write the dataflow code for the following K-map

In the above K-map Y = c + A D + B D

module tstckt(A, B, C, D, Y);

input A, B, C, D;
output Y;
assign y = ~C | (~A & ~ D) | (~ B & ~ D);
endmodule

Combinational Logic Circuit: circuit whose output is dependent only on current input

2.1 Sum of Products Method:

Fundamental product:

• A product that contains all variables in complemented or un-complemented form is

known as fundamental product.
• Fundamental products are also called as minterms.

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Fundamental products for Two inputs:

A B Fundamental Product minterm

0 0
AB m0
0 1
AB m1
1 0
AB m2
1 1
AB m3

Fundamental product for three inputs:

A B C Fundamental Product minterm

0 0 0 m0
ABC
0 0 1 m1
ABC
0 1 0 m2
ABC
0 1 1 m3
ABC
1 0 0 m4
ABC
1 0 1 m5
ABC
1 1 0 m6
ABC
1 1 1 m7
ABC
Steps to get Sum of products equation:

1. Locate each output 1 in truth table, and write down fundamental products
2. OR (logical sum) the fundamental products

Example: write sum of products equation for truth table given below

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Step1:Locate each output 1 in truth table, and write down fundamental products

Step2: OR (logical sum) the fundamental products

Sum of products Equation = A B C + A B C + A B C + A B C

The above equation is also called as Canonical Sum form

SOP Logic Circuit: to draw SOP Logic circuit, use AND gates and OR gate

Example: Draw a Logic circuit for the SOP equation

Alternate Representation of Truth table:

Truth table can be represented in the ∑m form
Example: write the ∑m form of the following table.

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Form the above table, SOP equation is written as

Y= m3 + m5 + m6 + m7

Y = F(A, B, C) = ∑m (3, 5, 6, 7)

Truth table to Karnaugh Map:

• Karnaugh map is visual display of fundamental products.

• K-map is used to simplify the Boolean expressions.

Example: Draw Karnaugh Map for two input truth table

A B Y

0 0 0

0 1 0

1 0 1

1 1 1

Steps to draw two-variable Karnaugh Map:

1. Write A and A in vertical column
2. Write B and B in horizontal row
3. Write the output value in corresponding fundamental product cell.

Three-Variable Map:
Draw the K-map for the truth table shown below

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Steps to draw three-variable Karanaugh map:

1. Write A B, A B , A B , A B in vertical column
2. Write C and C in horizontal row
3. Write the output value in corresponding fundamental product cell

Four-Variable Map:
Draw K-map for truth table shown below

Steps to draw four-variable K-map:

1. Write A B, A B , A B, A B in vertical column

2. Write C D, C D, C D, C D in horizontal row
3. Write output values in corresponding fundamental product cell

Pair:
A pair is a group of 1’s that are horizontally or vertically adjacent.
Example 1:

As shown in the figure, the first 1 represents the

product ABCD, second 1 represents ABCD, in both
products only D is changing, ABC are remaining same,
we can eliminate the variable which changes.

Hence the Boolean expression of this pair is

Y= ABC

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Example 2:

Boolean equation Y = ACD

The Quad:

A Quad is group of four 1s that are horizontally or vertically adjacent, Quad eliminates
two variables.

Examples:

As shown in the figure, four ones are grouped as

quad, it covers four columns and one row, since C D
are changing their forms, C and D can be eliminated,
AB is not changing, hence Boolean equation

Y= AB

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In this map, Quad covers two rows AB and AB

and two columns CD and CD, since B and D are
changing their forms, A and C are not changing their
forms, Boolean equation is
Y= AC

Octet:

An octet is a group of eight 1s, it eliminates three variables.

Examples:

As shown in figure, octet is covering four columns, and

two rows, in columns, C and D are changing forms, in
rows, B is changing its form , only A is remaining same,
hence Boolean equation is

Y=A

Karanaugh Simplifications:

For simplified SOP equation, group the octets first, the Quad second, and Pairs Last.

Example:

In K-MAP shown, first look for octets, since

octets are not possible, look for Quad, two quads
are possible, finally look for pairs, one pair is
possible, hence total three groups are there,
Boolean equation can be written as

Y= A B D + A C +C D

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Example: what is simplified Boolean equation for the following Logic function expressed
by minterms.

Y= F(A, B, C, D) = ∑m( 7, 9, 10, 11, 12, 13, 14, 15)

As shown in the figure, 1’s can be grouped with three quads, one pair

Simplified SOP equation = A B + AD + A C + B C D

Don’t Care Conditions:

 In digital systems, certain input conditions never occur during normal operations,
therefore corresponding output never appears.
 The symbol ‘X’ is used for the output which never appears.

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Example:

In truth table shown below, output is Low for all input entries from 0000 to 1000, high for input
entry 1001 and X for 1010 through 1111. The X is called don’t-care condition. Whenever u see
X in truth table you can let it equal to either 0 or 1.

K-map for truth table is

Simplified SOP equation is Y= AD

Logic circuit is

Remember these ideas about Don’t –Care conditions

1. Given truth table, draw a K –map with 0s, 1s and Don’t cares.
2. Encircle the actual 1s on the K-map in the largest groups you can find by treating the don’t
cares as 1s.
3. After actual 1s have been included in groups, ignore the remaining don’t cares by treating
them as 0s.

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PRODUCT-of-SUMS Method:

 Product of sums method is similar to sum of products method

 To get product-of sums equation, identify the fundamental sums in truth table for which
output is 0.
 By ANDing all fundamental sums, we get product-of sums equation.

Converting truth table in to POS equation:

1. Locate each output 0 in the truth table and write down its fundamental sums.
2. AND the fundamental sums to get POS equation.
3. In POS equation each sum term is called maxterm and is denoted by Mi

Example: convert the following table in to POS equation

Step1: write the fundamental sums for the outputs 0

the first output 0 appears for A=0, B =0, C=0, the fundamental sum for this input is A + B + C,
second output 0 appears for A=0, B=1, C=1 , fundamental sum for this input is A + B + C
third output 0 appears for A=1, B=1, C=0, fundamental sum for this input is A + B + C

Step2: AND the fundamental sums to get POS equation

Y = (A + B + C) (A + B + C) (A + B + C)

Canonical Product Form: the above table can be represented in terms of maxterms as

Y = F( A, B, C) = π M(0, 3, 6)

Converting POS equation into Logic circuit:

To draw the Logic circuit of POS equation, we need OR- AND network

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Logic circuit for the POS equation Y = (A + B + C) ( A + B + C) ( A + B + C)

The above OR- AND network can be replaced with NOR-NOR circuit

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POS simplification:

Example:
Find simplified POS equation and POS circuit for the following table.

Step 1: Draw K-map for the truth table.

Step2: invert 1s to 0s and 0s to 1s in above K- Map and group 1s and write the SOP equation.

SOP equation = A B + A B C

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Step-3 : Complement the SOP equation to get POS equation

POS equation = (A + B ) ( A + B + C)

POS circuit using NOR-NOR is

Simlification by Quine – Mc Clusky Method:

This method can be used to get simplified SOP equation.
This method has two tables
1. First table is used to determine prime implicants
2. Second table is used to determine essential prime implicants.

Determination of prime Implicants:

Stage 1: find out minterms that give output 1 from truth table, and put the minterms in different
groups depending on how many 1s minterms have, for example, first group has minterms which
have zero 1s, second group has only one 1, third group has two 1s, fourth group has three 1s so
on.
Stage 2: in this stage compare first and second group members, one by one, if they differ by only
one position, that position will by marked as’—‘ repeat the same procedure for second third
groups so on, if the members of first stage are combined at least once in second stage, those
members are marked as ‘√’.

Stage 3:
In stage 3, we combine members of different groups of stage 2 in similar way, now it
will have two ‘—‘ elements in each combination,

Repeat the stages as long the members are differ by only one position, if they differ by more than
one position stop the procedure, the members which are not marked ticked at any stage are
considered as prime implicants.

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Selection of essential Prime Implicants:

Once prime implicants are determined, prepare a table with all prime implicants along
rows, and all minterms along columns, find minimum number of prime implicants that covers all
minterms. Simplified SOP of equation can be obtained by adding all essential prime implicants.

Example:
Find the simplified SOP equation for the truth table shown below using Quine Mc
Clusky Method.

Determination of prime implicants table:

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From the above table, prime implicants are AꞋBꞋ, BꞋC , AC , AB

Selection of Prime Implicants table:

Essential prime implicants :

AꞋBꞋ covers the minterms (0,1,2,3), BꞋC covers the minterms (2,3,10,11), AC covers minterms
(10, 11, 14, 15) and AB covers minterms (12, 13, 14, 15)

Simplified SOP equation = AꞋBꞋ + BꞋC + AB

In SOP equation AC is eliminated because its minterms (10, 11 14, 15) are covered by BꞋC and
AB, hence AC is redundant which can be removed.

Hazard: unwanted transition in output signal of digital circuit is called as Hazard.

There are two types of Hazards

1. Static-1 Hazard
2. Statc-0 Hazard

Static-1 Hazard:

 This hazard occurs when A changes from 10 in any circuit in which output Y= A + AꞋ
 An A + AꞋ condition should always generate 1 at output i.e. Static-1, but the NOT gate
produces 0, because NOT output takes finite time to become 1 when A changes from
10. Hence two zeros appear at the input of OR gate for small duration, resulting a 0 at
its output. The width of this zero is called as glitch.

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Static -1 Hazard Cover circuit:

As shown in the above figure, first circuit with output y= BCꞋ + AC should always
produce 1 when B=1, A=1 and C changes from 10, but because of NOT gate delay, hazard
occurs, this hazard can be avoided by using additional AND gate as shown in the figure (D)

Static -0 Hazard:

 This type of hazard occurs when A changes from 01 in any circuit in which output
Y=A.AꞋ
 Y=A.AꞋ should always generate 0 at the output, but because of NOT gate delay, two 1s
appear at the AND gate input for small duration, hence output becomes 1.

Static-0 Hazard Cover circuit:

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In first circuit, when B=0 and A=0 and when C changes from 01, output Y= AC + BCꞋ
should produce 0 output, but because of NOT gate delay output becomes 1 for small duration,
this hazard can be avoided by adding additional OR gate with inputs A and B as shown in figure.

Dynamic Hazard:

This hazard occurs when circuit output makes multiple transitions before it settles final
value while the logic equation asks for only one transition.

Example: an output transition designed as 10 may give 1010 when dynamic hazard
occurs

Important Questions

1. Describe positive and negative Logic. List the equivalences between them 4M

2. Explain the structure of VHDL / Verilog Program 5M

3. Find the minimal SOP of the following Boolean function using K-maps

i) f(a, b, c, d) = ∑m(6,7,910,13) +d(1,4,5,11)

ii) f(w, x, y,z ) =πM(1,2,3,4,9,10) . d(0,14,15) 8M

4. Simplify f(A, B, C, D) = ∑m(0, 1, 2, 3, 10, 11, 12, 13, 14, 15) using Quine- Mc Clusky
method 8M

5. what are static hazards? How to design a hazard free circuit? Explain with an example. 4M

6. Write the truth table of the logic circuit having 3 inputs A, B and C and output expressed as

Y = A B C + A B C . Also simplify the expression using Boolean expression and implement

The logic circuit using NAND gates?

7. Using Q- M method, simplify the expressions f(A, B, C, D) = ∑m(0, 3, 5, 6, 7, 11, 14), draw
Gate diagram for the simplified expression using NAND- NAND gates

8. A digital system is to be designed in which the month of the year is given as input in four bit
Form , the month January is represented as ‘0000’ February ‘0001’ and so on. The output of
The system should be 1 corresponding to the input of the month containing 31 days otherwise
It is 0, consider the excess numbers in the input beyond ‘1100’ as don’t care conditions for
System of four variables (A, B, C, D) find the following
i) Write truth table
ii) Boolean expression in ∑m form and πM form

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iii) Using K –map, simplify the Boolean expression of canonical minterm form
iv) Implement the simplified equation using NAND- NAND gates

9. Find the essential prime implicants for the Boolean expression by using Quine- Mc clusky
Method f(A, B, C, D) = ∑m(1,3,6, 7,9, 10, 12, 13, 14, 15) 10 M

10. The system has four inputs, the output will be high only when the majority of the inputs are
High, find the following 10 M
i) Give the truth table and simplify by using K-map
ii) Boolean expression in ∑m and πM form
iii) Implement the simplified equation using NAND-NAND gates and NOR-NOR gates
11. Minimize the following Boolean function using K-map method
f(a, b, c, d) = ∑m(5, 6, 7, 12, 13) +∑d(4, 9, 14, 15) 6M
12. What is hazard? List the type of hazards and explain static-0 and static-1 hazard. 6M
13. Give SOP and POS circuit for f (A, B, C, D) = ∑m(6,8,9,10,11,12,13,14,15) 8M
14. Draw K-map for Y =F(A, B, C, D) =πM(0,1,2,4,5,10) . d(8,9,11,12,13,15) and get simplified
POS equation 4M
15. Get simplified expression for Y = F(A, B, C, D) = ∑m(2,3,7,9,11,13)+d(1,10,15) using quine
Mc-Clusky method. 10M
16. Write Verilog Structural code and data flow code for the figure shown below

17. Write Verilog structural code and data flow code for the following circuit

18. Write Verilog data flow model code for the following K-map

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19. Suppose truth table has high output for an input 0000, low output for 0001 to 1001 and don’t
cares for 1010 to 1111, what is the simplest logic circuit with this truth table? 4M

20. Draw the sum of products and product of sums circuits for K-map shown below

21. Get a minimized expression for Y = F(A, B, C, D) = A B C + A B C + A B C + A B C

22. Give SOP Form of Y= F(A, B, C, D) = πM(0, 3, 4, 5, 6, 7, 11, 15)

23. Draw K- map of Y = F (A, B, C, D) = π M(0, 1, 3, 8, 9, 10, 14, 15)
24. Give simplest POS form of K map shown below by grouping zeros.

25. Proove De Morgan’s theorems.

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