BOOLEAN ALGEBRA & LOGIC GATES

DEFINITIONS:-
Variable: The symbol which represent an arbitrary elements of an Boolean algebra known as variable. Any single variable
or a function of several variables can have either al or value. For example, in expression Y=A+ BC variables A. B and C can
have either a 1 or 0 value, and function Y also can have either a or 0 value however I value depends on the value of Boolean
expression.
Constant: In expression Y=A+1 the first term A is a variable and have value either al or 0. The second term has a fixed
value 1 So 1 is a constant here. The constant term may be 0 or 1.
Complement: A complement of a variable is represented by a "bar" over the letter. For example, the complement of a
variable A will be denoted by A. So if A=1, A = 0 and if A = 0, A = 1. Sometimes a prime symbol () is used to denote the
complement. For example, the complement of A can be written as A
Literal: Each occurrence of a variable in Boolean function either in a complemented or an uncomplemented form is called a
literal.
Boolean function : Boolean expressions are constructed by connecting the Boolean constants and variables with the
Boolean operations. These Boolean expressions are also known as Boolean formulas. We use Boolean expressions to
describe Boolean functions For example, if the Boolean expression (A + B) C is used to describe the function f, then
Boolean function is written as
f{A, B, = (A + B) C Or f= (A + B)C
LAWS OF BOOLEAN ALGEBRA:-
Commutative Laws:-
Commutative laws allow change in position of AND or OR variables. There are two commutative laws.
Law 1: A + B = B + A
Proof
A B A+B B A B+ A
0 0 0 0 0 0
0 1 1 = 0 1 1
1 0 1 1 0 1
1 1 1 1 1 1

Law 2: A . B = B . A
A B A.B B A B. A
0 0 0 0 0 0
0 1 0 = 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1

This law can be extended to any number of variables. For example

A.B.C=B.C.A=C.A.B=B.A.C
Associative Laws:-
The associative laws allow grouping of variables. There are 2 associative laws.
Law 1: (A + B) + C = A + (B + C)
A B C A+B (A+B)+C A B C B+C A+(B+C)
0 0 0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 1 1 1

0 1 0 1 1 0 1 0 1 1
=
0 1 1 1 1 0 1 1 1 1

1 0 0 1 1 1 0 0 0 1

1 0 1 1 1 1 0 1 1 1

1 1 0 1 1 1 1 0 1 1

1 1 1 1 1 1 1 1 1 1
 Law 2: (A .B) C = A (B .C)

Proof
A B C AB (AB)C A B C B.C A(B.C)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0 0 0
=
0 1 1 0 0 0 1 1 1 0
1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

This law can be extended to any number of variables. For

example A(BCD) = (ABC)D = (AB) (CD)
Distributive Laws:-
The distributive laws allow factoring or multiplying out of expressions. There are two distributive
laws. Law 1: A (B + C) = AB + AC

Proof
A B C B+C A(B+C) A B C AB AC A+(B+C)
0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0
0 1 0 1 0 0 1 0 0 0 0

0 1 1 1 0 = 0 1 1 0 0 0
1 0 0 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1
1 1 0 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1

Law 2: A + BC = (A+B) (A+C)

Proof RHS = (A+B) (A+C)
=AA+AC+BA+BC
=A+AC+AB+BC
=A(1+C+B)+BC
=A.1+BC (1+C+B=1+B=1)
= A+BC
= LHS
RULES OF BOOLEAN ALGEBRA:-
1. 0=1 1=0
2. 0∙1=0 1+0=1
3. 0∙0=0 1+1=1
4. 1∙1=1 0+0=0
5. A∙0=0 A+1=1
6. A∙1=A A+0=A
7. A∙A=A A+A=A
8. A∙ A=0 A+A =1
9. A∙B=B∙A A+B=B+A
10. A∙(B∙C)=(A∙B)∙C A+(B+C)=(A+B)+C
11. A∙(B+C)=AB+AC A+BC=(A+B)(A+C)
12. A(A+B)=A A+AB=A
13. A∙(A∙B)=A∙B A+ A+B=A+B
14. AB=A+B A+B= AB
15. (A+B)( A+C)(B+C)=(A+B)(A + C) AB+AC+BC= AB+ AC
16. A + BC=(A+B)(A+C) A(B+C)=A B +A C
17. (A+C)(A+B) = AB+AC AC+AB=(A+B) (A+C)
18. (A+B)(C+D) = AC + AD + BC + BD (AB+CD) = (A+C)(A+D)(B+C)(B+D)
19. A+B=AB+AB+AB AB =(A+B) (A+B) (A+B)
20. AB + A +AB=0 A + B ∙ A∙(A+B)=1
DIFFERENT TYPES OF LOGIC GATES:-
NOT GATE (INVERTER):-
A NOT gate, also called and inverter, has only one input and one
output. It is a device whose output is always the complement of its input.
The output of a NOT gate is the logic 1 state when its input is in logic 0 state and the logic 0 state when
its inputs is in logic 1 state.

IC No. :- 7404

Logic Symbol Truth table

INPUT OUTPUUT
A A
0 1
1 0
Timing Diagram
1 0 0 1
A

0 1 1 0
AND GATE:-
An AND gate has two or more inputs but only one output.
The output is logic 1 state only when each one of its inputs is at logic 1 state.
The output is logic 0 state evenn if one of its inputs is at logic 0 state.
IC No.:- 7408
Logic Symbol Truth Table

OUUTPUT

A B Q==A . B
0 0 0
Timing Diagram
0 1 0
0 0 1 1
1 0 0
A
1 1 1
0 1 0 1

0 0 0 1

OR GATE:-
An OR gate may have two or more inputs but only one output.
The output is logic 1 state, even if one of its input is in logic 1 state.
The output is logic 0 state, only when each one of its inputs is in logic state.

IC No.:- 7432
Logic Symbol Truth Table
INPUT OUT PUT
A B Q=A+B
0 0 0
0 1 1
1 0 1
Timing Diagram 1 1 1

0 0 1 1

0 1 0 1

0 1 1 1

Q
NAND GATE:-
NAND gate is a combination of an AND gate and a NOT gate.
The output is logic 0 when eaach of the input is logic 1 and for any other combination of inputs, the
output is logic 1.
IC No.:- 7400 two input NAND gate
7410 three input NAND gate
7420 four input NAND gate
7430 eight input NAND gate

Logic Symbol Truth Table

INPUT OUTPUT
A B Q= A.B
0 0 1
0 1 1
1 0 1
Timing Diagram
1 1 0
0 0 1 1

0 1 0 1

1 1 1 0

NOR GATE:-
NOR gate is a combination of an OR gate and a NOT gate.
The output is logic 1, only when each one of its input is logic 0 and for any other combination of inputs,
the output is a logic 0 level.

IC No.:- 7402 two input NOR gatee

7427 three input NOR gaate
7425 four input NOR gate

Logic Symbol Truth Table

INPUT OUTPUT
A B Q= A + B
0 0 1
0 1 0
1 0 0
1 1 0
Timing Diagram

0 0 1 1

0 1 0 1

1 0 0 0

EXCLUSIVE – OR (X-OR) GAATE:-

An X-OR gate is a two input, onne output logic circuit.
The output is logic 1 when one and only one of its two inputs is logic 1. Whenn both the inputs is logic 0
or when both the inputs is logic 1, the output is logic 0.

IC No.:- 7486

Logic Symbol Truth Table

INPUT OUTPPUT
A B Q=A B
0 0 0
INPUTS are A and B
0 1 1
OUTPUT is Q = A B 1 0 1
=AB+AB 1 1 0
Timing Diagram

0 0 1 1

0 1 0 1

0 1 1 0

EXCLUSIVE – NOR (X-NOR) GATE:-

An X-NOR gate is the combination of an X-OR gate and a NOT
gate. An X-NOR gate is a two input, one output logic circuit.
The output is logic 1 only when both the inputs are logic 0 or when both the inpputs is
1. The output is logic 0 when onee of the inputs is logic 0 and other is 1.
IC No.:- 74266

Logic Symbol

INPUT OUTPUT
A B OUT =A XNORR B

0 0 1
0 1 0
1 0 0
OUT=A B+A B
1 1 1
= A XNOR B

Timing Diagram

0011

0 1 0 1

1 0 0 1

OUT

UNIVERSAL GATES:-
There are 3 basic gates AND, OR and NOT, there are two universal gates NAND andd NOR, each of which
can realize logic circuits single handedly. The NAND and NOR gates are called universal building blocks. Both
NAND and NOR gates can perform all logic functions i.e. AND, OR, NOT, EXOR and EXNOR.
NAND GATE:-
a) Inverter from NAND gate

Input =A
Output Q = A

b) AND gate from NAND gate

Input s are A and B

Output Q = A.B

c) OR gate from NAND gate

Inputs are A and B

Output Q = A+B
 d) NOR gate from NAND gate

Inputs are A and B

Output Q = A+B

e) EX-OR gate from NAND gate

Inputs are A and B

Output Q = A B + AB

f) EX-NOR gate From NAND gate

Inputs are A and B

Output Q = A B + A B

NOR GATE:-
a) Inverter from NOR gate
Input =A
Output Q = A

b) AND gate from NOR gate

Input s are A and B
Output Q = A.B
 c) OR gate from NOR gate

Inputs are A and B

Output Q = A+B

d) NAND gate from NOR gate

Inputs are A and B

Output Q = A.B

e) EX-OR gate from NOR gate

Inputs are A and B

Output Q = A B + AB

f) EX-NOR gate From NOR gatee

Inputs are A and B

Output Q = A B + A B

THRESHOLD LOGIC:-
INTRODUCTION:-
The threshold element, also called the threshold gate (T-gate) is a much more powerful device than any
of the conventional logic gates such as NAND, NOR and others.
Complex, large Boolean functioons can be realized using much fewer threshold gates.
Frequently a single threshold gate can realize a very complex function which otherwise might require a
large number of conventional gates.
T-gate offers incomparably ecoonomical realization; it has not found extensive use with the digital
system designers mainly because of thhe following limitations.
1. It is very sensitive to parameter variations.
2. It is difficult to fabricate it in IC form.
 3. The speed of switching of threshold elements in much lower than that of coonventional gates.
De Morgan’s Theorem:-
De Morgan’s theorem represents two laws in Boolean algebra.

Law 1: A + B =A∙ B

Proof
A B A+B A+B A B A B AB

0 0 0 1 0 0 1 1 1

0 1 1 0 = 0 1 1 0 0
1 0 1 0 1 0 0 1 0

1 1 1 0 1 1 0 0 0
This law states that the complement of a sum of variables is equal to the product of their individual
complements.
Law 2: A∙ B = A + B
Proof

A B A.B A.B A B A B A+B

0 0 0 1
0 0 1 1 1
0 1 0 1
= 0 1 1 0 1
1 0 0 1
1 0 0 1 1
1 1 1 0
1 1 0 0 0
This law states that the complement of a product of variables is equal to the sum of their individual
complements.

SUM - OF - PRODUCTS FORM:-

This is also called disjunctive Canonical Form (DCF) or Expanded Sum of Products Form or Canonical
Sum of Products Form.
In this form, the function is the sum of a number of products terms where each product term contains all
variables of the function either in complemented or uncomplemented form.
This can also be derived from the truth table by finding the sum of all the terms that corresponds to
those combinations for which ‘f ’ assumes the value 1.
For example
f( A, B, C) = AB+BC+AC
The product term which contains all the variables of the functions either in complemented or
uncomplemented form is called a minterm.
The minterm is denoted as mo, m1, m2 … .
An ‘n’ variable function can have 2n minterms.
Another way of representing the function in canonical SOP form is the showing the sum of minterms for
which the function equals to 1.
For example
f ( A, B, C) = m1 + m2+ m3 +
m5 or
f (A, B, C) =∑ m (1, 2, 3, 5)
where ∑m represents the sum of all the minterms whose decimal codes are given the parenthesis.

PRODUCT- OF - SUMS FORM:-

This form is also called as Conjunctive Canonical Form ( CCF) or Expanded Product - of – Sums Form
or Canonical Product Of Sums Form.
This is by considering the combinations for which f =
0 Each term is a sum of all the variables.
The function f (A, B, C) = ( A + B + C∙C) + ( A + B + C∙C)
= (A+B+C)(A+B+C)(A+B+C)(A+B+C)
The sum term which contains each of the ‘n’ variables in either complemented or uncomplemented form
is called a maxterm.
Maxterm is represented as M0, M1, M2,
……. Thus CCF of ‘f’ may be written as
f( A, B, C)= M0 ∙ M4 ∙ M6∙ M7
or
f(A, B, C) = ( 0, 4, 6, 7)
 Where represented the product of all maxterms.
KARNAUGH MAP OR K- MAP:-
The K- map is a chart or a graph, composed of an arrangement of adjacent cells, each representing a
particular combination of variables in sum or product form.
The K- map is systematic method of simplifying the Boolean expression.

TWO VARIABLE K- MAP:-

A two variable expression can have 22 = 4 possible combinations of the input variables A and B.

Mapping of SOP Expression:-

The 2 variable K-map has 22 = 4 squares. These squares are called cells.
A ‘1’ is placed in any square indicates that corresponding minterm is included in the output expression,
and a 0 or no entry in any square indicates that the corresponding minterm does not appear in the
expression for output.
B
0 1

0 AB A B
A
1 AB AB

Example:-
Map expression f= AB + AB
Solution:-
The expression minterms is
F = m1 + m2 = m( 1, 2)
B
0 1

0 1
0 0 1
A 2 3
1 1 0
Minimization of SOP Expression:-
To minimize a Boolean expression givven in the SOP form by using K- map, the adjjacent squares having 1s,
that is minterms adjacent to each other are combined to form larger squares to eliminate some variables. The
possible minterm grouping in a two variable K- map are shown below

Two minterms, which are adjacent to each other, can be combined to form a bigger square called 2 –
square or a pair. This eliminates one variable that is not common to both the minterms.
Two 2-squares adjacent to eacch other can be combined to form a 4- square. A 4- square eliminates 2
variables. A 4-square is called a quad.
Consider only those variables which remain constant throughout the square,, and ignore the variables
which are varying. The non-complemented variable is the variable remaaining constant as 1.The
complemented variable is the variable remaining constant as a 0 and the variables are written as a
product term.

Example:-
Reduce the expression f= AB + A B + AB using mapping.

Solution:-
Expressed in terms of minterms, the giiven expression is
f = m0 + m1 + m3 = ∑m ( 0, 1, 3)

F=A+B
Mapping of POS Expression:-

Each sum term in the standard POS expression is called a Maxterm. A function in two variables (A,B) has 4
possible maxterms, A + B, A + B, A + B and A + B . They are represented as M0, M1, M2 and M3 respectively.

The maxterm of a two variable K-maap

Example:-
Plot the expression f= (A + B)(A + B)(A + B)
Solution:-
Expression interms of maxterms is f = πM (0, 2, 3)

Minimization of POS Expressions:-

In POS form the adjacent 0s are combbined into large square as possible. If the squares having complemented
variable then the value remain consstant as a 1 and the non-complemented variiable if its value remains
constant as a 0 along the entire squaree and then their sum term is written. The possible maxterms grouping in
a two variable K-map are shown below
Example:-
Reduce the expression f = (A + B)(A + B)(A +B ) using mapping
Solution:-
The given expression in terms of maxterms is f = πM (0, 1, 3)

THREE VARIABLE K- MAP:-

A function in three variables (A, B, C) can be expressed in SOP and POS forrm having eight possible
combination. A three variable K- map have 8 squares or cells and each square on the map represents a
minterm or maxterm is shown in the figgure below.

Example:-
Map the expression f = ABC++ABC + ABC + ABC +ABC
Solution:-
So in the SOP form the expression is f = ∑ m (1, 5, 2, 6, 7)

Example:-
Map the expression f = (A + B + C) (A + B+C) (A + B + C) (A + B + C) (A + B + C)
Solution:-
So in the POS form the expression is f = π M (0, 5, 7, 3, 6)