(A) module load cadence/innovus

(B) innovus
(C) lic
(D) encounter –log log/nov15

(I) fs lq (for check space)

(II) df –kh
(III) du -sk

Alias
Link for Unix commands

http://www.folkstalk.com/p/unix-commands-list.html

(0) awk format :::: awk ‘{print }’

(i) if ::: awk ‘{if ( $1 ~ ”design”) print }’ or awk ‘{ if ($(NF-1) ~ “design”) print }’

(ii)if else ::: awk ‘{ if ($1 ~ “Beginpoint”) print $0 > file1 ; if ($1 ~ “Endpoint”) print $0 > file2 ;

else if ($1 ~ “Slack”) print $0 > file3}’

(3)get to reguired lines::: less file | sed -n -e 12,22p -e 31,54p

(4)delete lines ::: less file | sed ‘1,23d’

(5)to print last n lines :: less file | tail -n

(6)to print first n lines :: less file | sed nq

(7)for multiple matches at a time:: grep –E “slack|rftx” |less

(8)to delete multiple matches at a time sed -e '/Beginpoint:\|Endpoint/ {N;d;}'

(8)Get three lines into one line::-> sed 'N;N;s/\n/ <space> /g'

(I) if 2 lines in single sed 'N;s/\n/ <space> /g'

(9) print the line immediately before(B) and after(A) a match and
howmany lines
Grep - A 2 “match” grep -B 2 “mat ch”

EX:: less timing.rpt | grep -A 2 "Endpoint" | less

(10) print 2 lines of context before and after match at a time
Grep -A2 -B2 “match”

EX:: less timing.rpt | grep -A 2 -B 2 "Endpoint" | less

(10)if a file open through less then to check numbers in file is as follows :: – N (ENTER)

(11)For remove last word AFTER “\”: :%s#\(.*\)\/.*#\1#g (or) :%s#\(.*\)\/\S\+#\1#g

EX:: input
AFUSE_MASTERCNT/AFUSE_MASTERCNT_AFW/MASTERCNT_SCANWP/AFUSE_MASTERCNT_OBSREG/OBSOUT_B
WE_reg_1_/SMC

AFUSE_MASTERCNT/AFUSE_MASTERCNT_AFW/MASTERCNT_SCANWP/AFUSE_MASTERCNT_OBSREG/OBSOUT_B
WE_reg_2_/SMC

command :%s#\(.*\)\/\S\+#\1#g or less exp |sed 's#\(.*\)\/.*$#\1#'|less

::output

AFUSE_MASTERCNT/AFUSE_MASTERCNT_AFW/MASTERCNT_SCANWP/AFUSE_MASTERCNT_OBSREG/OBSOUT_B
WE_reg_1_

AFUSE_MASTERCNT/AFUSE_MASTERCNT_AFW/MASTERCNT_SCANWP/AFUSE_MASTERCNT_OBSREG/OBSOUT_B
WE_reg_2_

(12)for remove ^M in gvim:: open file in gvim  %s/ctrl+q+m/ /g

In vim :: %s/ctrlvctrlm/ /g in sed::: sed ‘s/\r/ /g

(13) delete log files ::: ls -lrt | grep "Apr 15" | awk '{print " rm -rf " , $NF}' | sh

Delete empty lines or blank lines sed ‘/^$/d’ file

(14) Delete lines that begin with specified character

sed '/^u/d' file

(15) Delete lines that end with specified character

sed '/x$/d' file
TRAN REPORT FOR NETS

(16) less tran.rpt | sed -e '/*\|#/ {N;d;}' | egrep -A 1 '^\S' | grep -v '^--' | sed 'N;s/\n//g' | awk '{if ($NF ~
"R") print $0}' | less

(16) trim/remove the match ::::::::::: less all_macros|tr -d '{ }' |less

(17)replace space with new line ::: %s/ <space> /\r/g

http://www.theunixschool.com/2014/08/sed-examples-remove-delete-chars-from-
line-file.html
 MMMC CREATION

## FF 125 Pff_V1p2_T125 lib_MIN_HT

## FF -40 Pff_V1p2_Tm40 lib_MIN_LT

## SS 125 Pss_V1p0_T125 lib_MAX_HT

## SS -40 Pss_V1p0_Tm40 lib_MAX_LT

# Creating library corners

create_library_set -name lib_MAX_LT -timing $LIB(Pss_V1p0_Tm40)

create_library_set -name lib_MIN_LT -timing $LIB(Pff_V1p2_Tm40)

# Creating rc corners

create_rc_corner -name rc_T125\

-cap_table
/hyd_disk/proj4/RENESAS/pilot/fromRenesas/TIMING_LIBS/ALL_LIBS/UX8L_7LM_typ_Tx
.captbl\

-preRoute_res 1.01\

-postRoute_res 1.0037\

-preRoute_cap 1.0403\

-postRoute_cap {1.0403 1.0071 1}\

-postRoute_xcap 1.0071\

-preRoute_clkres 1.01\

-preRoute_clkcap 1.0403\

-postRoute_clkcap {1.0403 1.0071 1}\

-postRoute_clkres 1.0037\

-T 125\
 -qx_tech_file

# Creating delay corners

create_delay_corner -name MIN_LT -library_set lib_MIN_LT -rc_corner rc_Tm40

create_delay_corner -name MAX_LT -library_set lib_MAX_LT -rc_corner rc_Tm40

# Creating constraint modes

create_constraint_mode -name ACSCAN\

-sdc_files\

[list /hyd_disk/proj4/RENESAS/pilot/fromRenesas/SDC/DFT/ACSCAN/ACSCAN.sdc]

create_constraint_mode -name FUNC\

-sdc_files\

[list /hyd_disk/proj4/RENESAS/pilot/fromRenesas/SDC/FUNC/cpx3_func.sdc]

# Creating analysis views

create_analysis_view -name MIN_HT_ACBIST -constraint_mode ACBIST -delay_corner

MIN_HT

create_analysis_view -name MIN_LT_FUNC -constraint_mode FUNC -

delay_corner MIN_LT
create_analysis_view -name dc_scan_Pss_V1p0_Tm40Lib_cworstRc -delay_corner
Pss_V1p0_Tm40Lib_cworstRc -constraint_mode dc_scan

# create_analysis_view -name dc_scan_Pff_V1p2_T125Lib_cbestRc -

delay_corner Pff_V1p2_T125Lib_cbestRc -constraint_mode dc_scan

# Creating setup/hold variables

set setupViews { \
 MAX_HT_FUNC MAX_LT_FUNC MAX_HT_ACBIST MAX_LT_ACBIST
MAX_HT_ACSCAN MAX_LT_ACSCAN \

set holdViews { \

MIN_LT_FUNC MIN_LT_ACBIST MIN_LT_ACSCAN \

# Setting analysis views

set_analysis_view -setup $setupViews -hold $holdViews

# Setting default view

set_analysis_view -setup [list MAX_HT_FUNC MAX_LT_FUNC MAX_HT_ACBIST MAX_LT_ACBIST

MAX_HT_ACSCAN MAX_LT_ACSCAN]

-hold [list MIN_LT_FUNC MIN_LT_ACBIST MIN_LT_ACSCAN]

 Commands in innovus for each stage.

PLACEMENT
(I)placeDesign
From a user perspective, these are the things important in placement.

1. High fanout net synthesis

2. Use Ideal clock
3. Control Congestion
4. Scan chain reordering
5. TIE cells
6. Spare cells

7. Timing
Your clock is not propagated, hence you have a zero skew at this point. Your timing
reports should look pretty good. Make sure fanout constraints are met.
After placement, verify that all cells are placed on rows without any overlaps. You might find the
following commands useful depending on your design.
check_legality
report_placement_utilization
report_level_shifters -verbose

 Pre-placement optimization

 Scan tracing and scan reordering

 Placement optimization during the placement process

 Incremental placement on an already placed design

After placement we need to check the design and few other commands:
timeDesign -prects

(1) checkFiller -reportGap <value> (from lef)

EX: *INFO: Total number of 0.140 microns width gap found: 3

 (2) checkPlace or checkPlace -violationReportFileName
(3) refinePlace
(4) congRepair
(5) reportCongestion -trialRoute or reportCongestion - hotspot
(6) reportDensityMap
[-gridInMicron microns ]
[ -gridInRow numberRows ]
[-threshold density ]
(7)restorePlace TOPCHIP_SP.place (may not useful)
(8) savePlace mydesign.place (may not useful)
(9) getplacemode

(10) deleteFiller -cell xyz -prefix wtap_even

For reports in placement stage.

(I) report_timing - max_slack - 1.0
(II) report_timing - max_slack - 0.0 –max_paths 2 -format { } –
path_group {reg2reg}
(III) ecoAddRepeater -cell BF01D8 -net CORE/n13 relativeDistToSink
0.5 –prefix
The value should between 0 to 0.9. A low value (0.1) places the buffer near the
sink; a high value (0.9) places the buffer near the driver.

(iv) do the following to check your hold violations and setup margins on the branch.

report_timing -through CLK_BUF_2/A > setups.txt

report_timing -early -through CLK_BUF_2/A > holds.txt

 (v) ecoChangeCell -inst Top_I18 -cell BUFX20

TRAN-FIX

ecoAddRepeater -term reg1/D -relativeDistToSink 0.1 -cell BUFX2

CAP-FIX

To know the i/p & o/p of net ---> all_connected <net>

 \
setOptMode -holdFixingCells {DLYX4 DLYX2}

set_ccopt_property buffer_cells { BUFX12 BUFX8 BUFX6 BUFX4 BUFX2 }

set_ccopt_property inverter_cells { INVX12 INVX8 INVX6 INVX4 INVX2 }
set_ccopt_property clock_gating_cells { PREICGX12 PREICG8 PREICGX6
PREICGX4 }
dbGet -p2 top.insts.cell.baseClass block

Cadence wiki
http://edi.truevue.org/edi/14.17/fetxtcmdref/fetxtcmdrefTOC.html

SETUP FIXING

(A) INCREASE DRIVE STRENGTH OF DRIVER

(B) ADD BUFFER ON NET
(C) ADD REPEATERS (PLACE BUFFS WITH SOME EQUAL MARGINS)
(D) VT SWAPING
(E) PIN SWAPING
(F) LOGIC RESTRACTURE
 (G) USEFUL SKEW
(H) MACRO MODEL
(I) METAL LAYER CHANGE TO HIGH METAL

HOLD

(A) DECREASE DRIVE STRENGTH OF DRIVER

(B) ADD BUFFER ON NET
(C) VT SWAPING
(D) PIN SWAPING
(E) USEFUL SKEW
(F) MACRO MODEL
(G) METAL LAYER CHANGE TO LOW METAL

DRV FIXING

(A) OPT_DESIGN -STEGE(POST_CTS) -DRV -INCR

(B) ADD BUFFER ON NET
(C) INCREASE DRIVE STRENGTH OF DRIVER
(D) IF HAVE HIGH FANOUT THEN CLONING

(13)Innovus hold Fixing:::

(i) change the cells to HVT if it is in LVT/SVT.

EX: ecoChangeCell -inst Top_I18 -cell BUFX20

Better to add catch for continue run , even if occur any error in one line

EX: catch {ecoChangeCell -inst Top_I18 -cell BUFX20}

(ii)add delay cells at endpin by consider setup margin::

 ->this is my file

 So to get Endpoint write as below…I wrote this cmnd w.r.t my file.you may change it.

(A) less xgrp10_postRoute_reg2reg_hold.tarpt | grep -E -A 1 "Endpoint:|Slack Time" | grep -v "^-- "

| grep -v "Clock" | sed 'N;N;s/\n/ /g' |awk '{print $2,$NF}' > file1

*now we get both hold endpoint and margin

*then we need setup margin for that endpoint.grep only endpoint from file1.then proceed as below.

(B )write all endpoints ln one file and give loop for that in same file.

EX: set endpoint {

| all endpoints

Foreach x $endpoint {

Set margin [get_property [get_pins $x] slack_max]

Puts “$x,$margin”

}
****source file > file2

(C) paste both file2 and file 1 > file3

In file 3 we have

$1=endpoint $2=setup slack $3= endpoint $4= holdslack

 Less file3|awk ‘{print $2,$4,$1}’ > file4

In file if we have ^M ,then open that file in gvim and %s/ctrlvctrlm/ /g in sed:::

sed ‘s/\r/ /g

***here we need to check that design timing units is in ns/ps..my design is in ps.***

less s_h_margin | awk '{print $1,$2,int(((-$2)/0.02)+1),$NF}' | awk '{if($1>=($3*0.04)) print }' |awk
'{for(i=1; i<=$3;i++) print “catch { ecoAddRepeater -cell",bufname,”-term” ,$NF,”}”}’ > file5

explanation::if we have -100ps vio in hold. Then if buff giving 20ps delay (from report).then
(100/20=5buff) required.but in setup same cell give almost double delay 40ps.so in setup case that pin
should have(40*5 > 200ps) margin.

(i) int(((-$2)/0.02)+1 == - 100/20=5buff

(ii) ($1>=($3*0.04)) == 40*5 > 200ps
(iii) (i=1; i<=$3;i++) == add cells until it reach to 5 (5buffers).

(D) before source file5 remove all fillers

EX: deleteFiller -cell xyz -prefix wtap_even

*****source file5.

(F)refinePlace

(E) checkPlace
(F)checkFiller –reportGap 0.14 (value not sure)

(G) addFiller -cell FILL64 FILL16 FILL4 FILL2 FILL1 -prefix FILLER

FOR REPORTS

(i)timeDesign –expandReg2Reg -Numpaths 1000 -outdir /…/.../…/…/… -expandedView –postRoute

(ii) same as above but just add “-hold” at end of line.

SETUP FIXING

Report_timing –path_group {reg2reg} –max_paths 2 –max_slack 0.0 -late

 (iv) Here setup violated with 700ps.so observe the delay column.Here delay is
165.201 what I highlighted .so observe the drive strength of the driver cell.
i.e above the helighlited line.

Here INV_X3N_A9PP84TSL drive strength is X3 .so increase that to 6 or some above.

i.e ecoChangeCell –inst FE_OFC9321_CE0_SE_SELATP_CLK_450 –cell INV_X6N_A9PP84TSL_C14

again check the timing for reg2reg paths

Report_timing –path_group {reg2reg} –max_paths 2 –max_slack 0.0 -late

 (A) write format to get net.

EX:: report_timing -format {timing_point edge cell delay arrival net load
pinload fanout} -net

EX::

(i) ->Here input tran violated with 85ps and output with 15ps.
-> then add buff on net of ZN –I

(ii) Once you get that net then add buffer on that net

ecoAddRepeater -cell BF01D8 -net CORE/n13 relativeDistToSink 0.5 –prefix

report_clock_timing -type skew

report_clock_tree
 FOR db COMMANDS

http://www.edaboard.com/thread219064.html

Getting Started with dbGet

dbGet ---> (head/top/selected)

dbGet head.?
head: allCells

dbUnits

layers

mfgGrid

objType

props

EX: (I) dbGet head.dbUnits --> it just give the value(1000).i.e each micron is 1000units.

(II) dbGet head.mfgGrid

(iii) dbGet head.layers.? --> layer: extName name objType props type

(a) dbGet head.layers.name

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 CA V1 V2 V3 V4 V5 V6 V7 V8

dbGet top.?
topCell: fPlan hInst insts name nets numBidirs numInputs numInsts numNets
numPhysInsts numPhysNets numTerms objType pgTerms physInsts physNets props
statusClockSynthesized statusGRouted statusIoPlaced statusPlaced statusPowerAnalyzed
statusRCExtracted statusRouted statusScanOpted terms

Cool, lots of stuff to play with here! Try out various attributes and start thinking about how you can
use the results in scripts, or just to poke around your design and check out a few things.

Finally, select one of the instances in your design (I selected a RAM), then:
> dbGet selected.?
> inst: box cell instTerms isDontTouch isHaloBlock isJtagElem isPhysOnly isSpareGate name
objType orient pStatus pgCellTerms pgTermNets pt

This is a quick way to get information for just the things you've selected. (Try selecting more than
one thing and see how the results look.)

This has been a VERY brief introduction to playing with dbGet. (We didn't even get to dbSet yet!) I'd
love to hear in the comments if you are already using dbGet, if you know about it but haven't used it
yet, or if you didn't even know about it but think you might use it now. Have fun playing around and
finding some useful dbGet combinations - then save those for a future post, where I'll ask everyone
for their favorites.

(i) To get a list of NONDEFAULT rules in the design:

dbGet head.rules.name

(ii) To get NDR applied on a specified net:

dbGet [dbGet -p top.nets.name netName].rule.name

(iii) To get a list of all cell types used in the design:

dbGet -u top.insts.cell.name
(The "-u" filters out duplicate objects.)

(iv) To get all insTerm names which are tied to tieLo cells:
dbGet [dbGet -p [dbGet -p2 top.insts.cell.subClass
coreTieLo].instTerms.net.allTerms.isInput 1].name

(v) To get the status of your design:

dbGet top.statusIoPlaced
dbGet top.statusPlaced
dbGet top.statusClockSynthesized
dbGet top.statusRouted
dbGet top.statusRCExtracted
dbGet top.statusPowerAnalyzed

(vi) To find out which layers are used in a net:

dbGet [dbGet -p top.nets.name netName].wires.layer.name

(vii) To get database units:

dbGet head.dbUnits
(viii) To get manufacturing grid:
dbGet head.mfgGrid

(ix) To get physical only cells like filler cell, end cap cell etc:
dbGet [dbGet -p top.insts.isPhysOnly 1].name

(x) To find out the instname/cellname of the driver driving a specific net.
set netName <netName>
set inst [dbGet [dbGet -p [dbGet -p top.nets.name $netName].allTerms.isOutput
1].inst]
Puts "Net: $netName, driving inst name: [dbGet $inst.name], driving cell name:
[dbGet $inst.cell.name]"

(xi) For fanout > 32 and whch is not clock

dbGet [dbGet top.nets {.numInputTerms > 32 && .isClock == 0}].name

addHaloToBlock {1 1 1 1} -allmacro

deleteHaloFromBlock -allmacro

addHaloToBlock {1 1 1 1} XXXXXXXXXXXXX

/hyd_disk/proj4/RENESAS/pilot/flow/rel_4.9/
.
 POWER ISSUES ::: MIN STEP VIOLATIONS

So before you going to fix it, off the visability of violations (Miscellaneours.)

Select the macro and (shift+r),,,alian the macro w.r.t via.

Then remove power using below. [press d ]

Action (select) ->apply

Apply -> action (delete) ->apply

CMD:: (A) editSelect -net {VDD VSS} -layers {M1 M2 M3 M4 M5 M6 M7 M8} -shape {RING STRIPE
FOLLOWPIN IOWIRE COREWIRE BLOCKWIRE PADRING BLOCKRING FILLWIRE FILLWIREOPC DRCFILL} -
status ROUTED

(B) editDelete -selected -wires_only 1 -net {VDD VSS} -layers {M1 M2 M3 M4 M5 M6 M7 M8} -shape
{RING STRIPE FOLLOWPIN IOWIRE COREWIRE BLOCKWIRE PADRING BLOCKRING FILLWIRE FILLWIREOPC
DRCFILL} -status ROUTED

Then just select all layers, if still have vias

CMD: (A) editSelectVia -net {VSS VDD} -shape {FOLLOWPIN STRIPE} -status ROUTED

(B)editDelete -selected

Remove fillers also..place -> Physical cell ->deletefill -> fillnames

Source power file (edi_power.tcl)

Just we have few violations only…

PLACEOPT::
CTSOPT-setup::

CTSOPT-HOLD::
ROUTEOPT -setup::

ROUTEOPT-HOLD::
 REPORT ANALYSIS

(A) FROM CTS TO ROUTING I GOT SETUP VIOLATIONS MORE.

Violation paths :: -> 12(cts) t o 10320(route)

Because of in design.tcl we “set setupFix 1”..so we change it to 0.

Then again run the routeopt on routed data base.

ROUTE OPT::SETUP
We can clearly observe that TNS/ALL VIO PATHS of both before and after changes.

(B) SETUP is violating because of SKEW.

[I] 1ST need to check reports, in that I have data path is too small. Just one buff only b/w
reg2reg.

Need to check from endpoint.

i.e from ending of 1st table (arrival time). Where we get the CLK->Q from that it is data path.here

just have TL7BUFX1X20 cell only.

So the issue is because of latencys.

Just observe in schematic view based on endpoint.

 it has launch latency is 9.3725. data path deley is 0.1844

Capture latency is 4.6411

Launch – capture [9.3725 – 4.6411]

SLACK = -1.6925
placeopt_nov23 [Only soft for all macros in left side]
 Feplace_blockagechange_nov25

In this block I use partial blockage 35% for all macros of left side..
 placeopt_blkchng2small_dec6 enc

Inthis block I use to superate all macros of left side by 3parts and apply partial blockage for
35%.so 3 partial blockages in left side with 35%...and soft blockage b/w gap of top side 2 &3
rows.
set_interactive_constraint_modes [all_constraint_modes -active]
set_propagated_clock [all_clocks ]
report_timing
Icc2 command file http://icc.truevue.org/icc2/cmd

Innovus cmdfile http://edi.truevue.org/edi/14.17/fetxtcmdref/fetxtcmdrefTOC.html

Unix/linux cmd http://www.folkstalk.com/p/unix-commands-list.html

Icc2 user guide

https://solvnet.synopsys.com/dow_retrieve/latest/icc2olh/Default.htm#icc2dp/icc2dp_floorplan.html

Icc2 error command

https://solvnet.synopsys.com/dow_retrieve/latest/icc2olh/Default.htm#ni/manpages/icc2n/NDM.html#NDM-029

STA link http://www.ee.bgu.ac.il/~digivlsi/slides/STA_9_1.pdf

Change colour of edi------ setLayerPreference bg –color red/black/etc………..

For pin tran time.

report_constraint -drv_violation_type max_transition i_BUFX2/Z
report_property [get_pins DTMF_INST/TDSP_CORE_INST/i_10084/Y ]r

A nice thing about get_property is that you can specify which MMMC view you want

get_property [get_pins DTMF_INST/TDSP_CORE_INST/i_10084/Y] slew_max_rise -view

setup_func