GENUS_RAPID_ADOPTION_KIT

Overview
 Genus is a Drop-In Compatible Synthesis Tool

RTL
Constraints
.lib, .lef .sdc

Netlist Test
Genus
Drop-In Compatibility

Genus Inputs
HDL: Verilog, VHDL, System Verilog
(w/directives & pragmas)
Constraints: .SDC Optimized Verification
Library: .LIB and .LEF .sd netlist
GTech & DW foundation equivalents c
Optional: .CPF .DEF .captable .SAIF .TCF .VCD

Genus Outputs
Optimized gate-level netlist: .v Physical Design Analysis
Constraints: .SDC
Optional: scandef, DEF, Dofiles, .CONF

Standards-based compatibility
2 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved
Genus Synthesis – the Next Generation of RTL Synthesis
 A massively parallel architecture improves turnaround time by up to 5X while
maintaining quality of results
– Offers timing-driven, multi-level design partitioning across multiple threads and
machines
– Leverages parallelism at three levels

 The Genus solution synthesizes up to 10M+ instances flat without impacting

power, performance and area (PPA)

 The Genus solution allows playing in the Sandbox

– Sandbox allows any subset or partition of a design to be extracted along with full timing
and a physical context
– Extracted contexts include all the critical physical information

 The Genus solution provides tight correlation with the Innovus Implementation
System, using the same placement and routing algorithms
– Shares algorithms, engines, and a common user interface with Innovus

 Globally focused PPA optimization saves up to 20% datapath area and power
– Globally focused early PPA optimization across the whole datapath

3 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved

Before You Start
What Is Needed to Synthesize a Design?
1. Liberty Format Library (.lib) File(s)
2. Library Exchange Format (.lef) Technology File(s)
3. Verilog and/or VHDL and/or SystemVerilog File(s)
4. Synopsys Design Constraints (.sdc) File(s)
5. Genus Run Script (.tcl)
6. “Optional” but Recommended Files:
• QRC tech file / Capacitance Table File (.captbl)
• Design Exchange Format (.def) Floorplan File
• Switching Activity File(s): .saif, .tcf, .vcd
• Power:
• Power Format (.cpf) File
• Supports IEEE 1801 Standard
7. Genus Executable & Genus License
8. Genus Documents
4 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved
Start Genus
 unix:> genus [-options]
– Useful options:
[-files <string>]: execute command file
[-help]: print this message
[-log <string>]: specify logfiles
[-lic_startup <string>]:
specifies one of the following licenses
Genus_Synthesis
Virtuoso_Digital_Implem
Virtuoso_Digital_Implem_XL
[-lic_startup_options <string>]+:
checkout an option license at startup
Genus_Low_Power_Opt
Genus_Physical_Opt
Vdixl_Capacity_Opt
[-no_gui]: start with GUI disabled
[-version]: return program version information
[-legacy_ui]: start Genus with Legacy UI
 Genus is run in Legacy UI through this RAK.
 Typical:
unix:> genus –legacy_ui –f run.tcl –log base.log
 Run Genus in Legacy UI standalone for the next part :
unix:> genus –legacy_ui
 A Genus prompt will appear: legacy_genus:> , which indicates that you are
running Genus in Legacy UI.
5 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved
Create a Run Script: Use write_template

Creates a baseline synthesis template for running Genus

Should be used for each new design and/or tool release
– Ensures that all attribute/variable settings are for the latest release
– Ensures use of latest recommended synthesis flow
Supports the following
– DFT
– Low Power
– Multiple Supply Voltage (MSV)
– Retiming
– Multimode
– Area Optimization
– Netlist to Netlist Optimization
– Genus Physical Flow
– CPF Based Low Power Synthesis

6 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved

The ‘write_template’ usage model
legacy_genus@root:> write_template –outfile<string> [options]
useful options:
[-split]: writes out template script with separate file for setup, DFT and power
[-no_sdc]: writes out constraints in Genus format <optional>
[-dft]: writes out DFT attributes and commands in the template script
[-power]: writes out Clock Gating, Dynamic and Leakage power attributes in the template script
[-cpf]: writes out a template script for CPF based flow and a template CPF file (template.cpf).
[-full]: writes out a template script with all the basic commands, DFT, power and retiming attributes
[-retime]: writes out retiming attributes and commands in the template script
[-n2n]: writes out a template script for netlist to netlist optimization
[-multimode]: writes out a template script for multimode analysis
[-simple]: writes out a simple template script
[-area]: writes out a template script for area critical designs [-
yield]: writes out a template script for yield
[-physical]: writes out a template script for Genus Physical Flow

To start, use the following command:

legacy_genus@root:> write_template –outfile run.tcl

This will create a script files: run.tcl – we will use this to operate Genus
7 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved
Open Your Genus Documents
Before you proceed to edit the run scripts…
– Know where Genus’s supporting documents are kept
– They will be useful to explain new & unfamiliar commands, objects, attributes,
and variables used in the template

You can find them under the directory where tool is installed on your
system
unix:> which genus
it shows “$path_to_tool_directory/tools.xxx/bin/genus ”

Useful Genus Documents

You are able to find useful documents under the directory:
“$path_to_tool_directory/doc/

8 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved

A Quick Word about Genus run scripts…

Genus is a true Tcl-based tool, its run scripts are all Tcl scripts
They utilize variables, lists, objects, attributes, directories and
commands
Look for the angle brackets <name> to find what you need to provide
Again, use the documentation if something is not clear
The point of this training is to show you what parts of the run scripts are
relevant to what your want to do with Genus , the use of new commands,
and what parts of the scripts you need to modify
The following ‘run.tcl’ script, which is modified based on the template,
follows such style:
 New Genus Commands are shown in ‘Red color’
 The user input parts are shown in ‘Blue color’

9 Copyright © 2016 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl
####################################################################################
# MAIN SETUP (root attributes & setup variables) #
####################################################################################
#### Template Script for RTL->Gate-Level Flow (generated from Genus)
::legacy::set_attribute common_ui false / ;#run Genus in Legacy UI if Genus is invoked with Common UI

if {[file exists /proc/cpuinfo]} {

sh grep "model name" /proc/cpuinfo
sh grep "cpu MHz" /proc/cpuinfo
}
puts "Hostname : [info hostname]“
##############################################################################
## Preset global variables and attributes
##############################################################################
set DESIGN dtmf_recvr_core
set SYN_EFF medium
set MAP_EFF medium
##set MAP_EFF high
set OPT_EFF medium
set DATE [clock format [clock seconds] -format "%b%d-%T"]
set _OUTPUTS_PATH outputs_${DATE}
set _REPORTS_PATH reports_${DATE}
set _LOG_PATH logs_${DATE}

if {![file exists ${_LOG_PATH}]} {

file mkdir ${_LOG_PATH}
puts "Creating directory ${_LOG_PATH}"
}
if {![file exists ${_OUTPUTS_PATH}]} {
file mkdir ${_OUTPUTS_PATH}
puts "Creating directory ${_OUTPUTS_PATH}"
}
if {![file exists ${_REPORTS_PATH}]} {
file mkdir ${_REPORTS_PATH}
puts "Creating directory ${_REPORTS_PATH}"
10 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved
}
Edit run.tcl
##set ET_WORKDIR <ET work directory>
set_attribute init_lib_search_path {. ../LIB} /
##set_attribute script_search_path {. ../scripts} /
set_attribute init_hdl_search_path {. ../RTL} /
##Uncomment and specify machine names to enable super-threading.
#set_attribute super_thread_servers {<machine names>} /
set_attribute max_cpus_per_server 8 /

##Default undriven/unconnected setting is 'none'.

##set_attribute hdl_unconnected_input_port_value 0 | 1 | x | none /
##set_attribute hdl_undriven_output_port_value 0 | 1 | x | none /
##set_attribute hdl_undriven_signal_value 0 | 1 | x | none /

##Set synthesizing effort for each synthesis stage

set_attribute syn_generic_effort $SYN_EFF /
set_attribute syn_map_effort $MAP_EFF /
set_attribute syn_opt_effort $OPT_EFF /

##set_attribute wireload_mode <value>

set_attribute information_level 9 /

###############################################################
## Library setup
###############################################################

set_attribute library { ../LIB/slow.lib ../LIB/pll.lib ../LIB/CDK_S128x16.lib ../LIB/CDK_S256x16.lib

../LIB/CDK_R512x16.lib } /
## PLE
set_attribute lef_library { ../LEF/gsclib045_tech.lef ../LEF/gsclib045_macro.lef ../LEF/pll.lef
../LEF/CDK_S128x16.lef ../LEF/CDK_S256x16.lef ../LEF/CDK_R512x16.lef } /
##set_attribute cap_table_file <file> /

11 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl
##generates <signal>_reg[<bit_width>] format
set_attribute hdl_array_naming_style %s\[%d\] /

## Turn on TNS, affects global and incr opto

#set_attribute tns_opto true /

####################################################################
## Load Design
####################################################################

##source verilog_files.tcl
read_hdl " pllclk.v accum_stat.v alu_32.v arb.v data_bus_mach.v data_sample_mux.v decode_i.v decoder.v \
digit_reg.v conv_subreg.v dma.v dtmf_recvr_core.v execute_i.v m16x16.v mult_32_dp.v \
port_bus_mach.v prog_bus_mach.v ram_128x16_test.v ram_256x16_test.v results_conv.v spi.v \
tdsp_core_glue.v tdsp_core_mach.v tdsp_core.v tdsp_data_mux.v tdsp_ds_cs.v test_control.v \
ulaw_lin_conv.v power_manager.v "
elaborate $DESIGN
puts "Runtime & Memory after 'read_hdl'"
time_info Elaboration

check_design –unresolved

####################################################################
## Constraints Setup
####################################################################

read_sdc ../Constraints/dtmf_recvr_core_gate.sdc

puts "The number of exceptions is [llength [find /designs/$DESIGN -exception *]]"

#set_attribute force_wireload <wireload name> "/designs/$DESIGN“ /

report_timing -lint

12 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl
###################################################################################
## Define cost groups (clock-clock, clock-output, input-clock, input-output)
###################################################################################
## Uncomment to remove already existing costgroups before creating new ones.
## rm [find /designs/* -cost_group *]
if {[llength [all::all_seqs]] > 0} {
define_cost_group -name I2C -design $DESIGN
define_cost_group -name C2O -design $DESIGN
define_cost_group -name C2C -design $DESIGN
path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C
path_group -from [all::all_seqs] -to [all::all_outs] -group C2O -name C2O
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
}
define_cost_group -name I2O -design $DESIGN
path_group -from [all::all_inps] -to [all::all_outs] -group I2O -name I2O

foreach cg [find / -cost_group *] {

report timing -cost_group [list $cg] >> $_REPORTS_PATH/${DESIGN}_pretim.rpt
}

#### To turn off sequential merging on the design

#### uncomment & use the following attributes.
##set_attribute optimize_merge_flops false /
##set_attribute optimize_merge_latches false /
#### For a particular instance use attribute 'optimize_merge_seqs' to turn off sequential merging.

13 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl
####################################################################################
##Synthesizing to generic
####################################################################################
syn_generic
puts "Runtime & Memory after ‘syn_generic'"
time_info GENERIC
report datapath > $_REPORTS_PATH/${DESIGN}_datapath_generic.rpt

#generate_reports -outdir $_REPORTS_PATH -tag generic

#summary_table -outdir $_REPORTS_PATH

write_db -to_file ${DESIGN}_generic.db

####################################################################################
## Synthesizing to gates
####################################################################################
syn_map
puts "Runtime & Memory after ‘syn_map'"
time_info MAPPED
report datapath > $_REPORTS_PATH/${DESIGN}_datapath_map.rpt
foreach cg [find / -cost_group *] {
report timing -cost_group [list $cg] > $_REPORTS_PATH/${DESIGN}_[basename $cg]_post_map.rpt
}

generate_reports -outdir $_REPORTS_PATH -tag map

summary_table -outdir $_REPORTS_PATH

write_db -to_file ${DESIGN}_map.db

14 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl
##Intermediate netlist for LEC verification..
write_hdl -lec > ${_OUTPUTS_PATH}/${DESIGN}_intermediate.v
write_do_lec -revised_design ${_OUTPUTS_PATH}/${DESIGN}_intermediate.v -logfile
${_LOG_PATH}/rtl2intermediate.lec.log > ${_OUTPUTS_PATH}/rtl2intermediate.lec.do
## ungroup -threshold <value>
####################################################################################
## Incremental Synthesis
####################################################################################

## Uncomment to remove assigns & insert tiehilo cells during Incremental synthesis
##set_attribute remove_assigns true /
##set_remove_assign_options -buffer_or_inverter <libcell> -design <design|subdesign> /
##set_attribute use_tiehilo_for_const <none|duplicate|unique> /

syn_opt
puts "Runtime & Memory after syn_opt"
time_info INCREMENTAL
foreach cg [find / -cost_group *] {
report timing -cost_group [list $cg] > $_REPORTS_PATH/${DESIGN}_[basename $cg]_post_incr.rpt
}

generate_reports -outdir $_REPORTS_PATH -tag incremental

summary_table -outdir $_REPORTS_PATH

write_db -to_file ${DESIGN}_incr.db

15 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Edit run.tcl – No Editing Needed Here
###########################################################################################
## write Innovus file set (verilog, SDC, config, etc.)
###########################################################################################
##report qor > $_REPORTS_PATH/${DESIGN}_qor.rpt
report area > $_REPORTS_PATH/${DESIGN}_area.rpt
report datapath > $_REPORTS_PATH/${DESIGN}_datapath_incr.rpt
report messages > $_REPORTS_PATH/${DESIGN}_messages.rpt
report gates > $_REPORTS_PATH/${DESIGN}_gates.rpt
write_design -basename ${_OUTPUTS_PATH}/${DESIGN}_m
## write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_m.v
write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_m.sdc

#################################
### write_do_lec
#################################
write_do_lec -golden_design ${_OUTPUTS_PATH}/${DESIGN}_intermediate.v -revised_design
${_OUTPUTS_PATH}/${DESIGN}_m.v -logfile ${_LOG_PATH}/intermediate2final.lec.log >
${_OUTPUTS_PATH}/intermediate2final.lec.do
##Uncomment if the RTL is to be compared with the final netlist..
##write_do_lec -revised_design ${_OUTPUTS_PATH}/${DESIGN}_m.v -logfile ${_LOG_PATH}/rtl2final.lec.log >
${_OUTPUTS_PATH}/rtl2final.lec.do

puts "Final Runtime & Memory."

time_info FINAL
puts "============================"
puts "Synthesis Finished ........."
puts "============================"

file copy [get_attribute stdout_log / ] ${_LOG_PATH}/.

##quit

16 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Invoke Genus with run.tcl Script:
Invoke with run.tcl
unix:> genus –legacy_ui –f run.tcl –log base.log

You can use ‘-h’ option to get help for Genus commands, for example:
legacy_genus:> write_template –h
legacy_genus:> write_design -h

Successful?
– Completion of running this script will end with the message
============================
Synthesis Finished .........
============================
– And leave you with a Genus prompt : legacy_genus:>
– And finally, your REPORT & OUTPUT directories should be populated as well
– To quit the tool: legacy_genus:> quit OR legacy_genus:> exit

Problems? The next part will discuss debugging tricks utilizing the logfile
17 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved
Debug Synthesis: with logfile & timing reports
Were you successful with your synthesis run?
Look at your logfile!
– A nonstop run through the entire synthesis script without any errors or
significant warnings:
Keywords: Error, avoid, combinational, Black-boxes,
unresolved, following, read_sdc
– You can run Genus interactively to debug problems with your script
– There is also important information about your design -- with regard to your
optimization goals -- that is only available in the logfile:
Keywords: Target, incremental, Timing slack

Look in your REPORTS directory

– You should have timing reports tracking the worst negative slack of the
design through the different synthesis stages

Good Results? You’re done with the Quickstart!

18 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Problems in logfile: elaborate & check_design
--------------------
Summary
-------
Name Total
-------------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 4
Unloaded Sequential Pin(s) 17
Checking the design. Assigns 363
Undriven Port(s) 9
Check Design Report Undriven Leaf Pin(s) 0
-------------------- Undriven hierarchical pin(s) 3
Multidriven Port(s) 0
Unresolved References & Empty Modules Multidriven Leaf Pin(s) 0
------------------------------------- Multidriven hierarchical Pin(s) 0
No unresolved references in design 'dtmf_recvr_core' Multidriven unloaded net(s) 0
Constant Port(s) 0
No empty modules in design 'dtmf_recvr_core' Constant Leaf Pin(s) 6
Constant hierarchical Pin(s) 1922
Done Checking the design. Preserved leaf instance(s) 4
Preserved hierarchical instance(s) 0
Libcells with no LEF cell 0
Physical (LEF) cells with no libcell 0
Subdesigns with long module name 0
Physical only instance(s) 0
Reports from running Reports from running
Done Checking the design.
check_design -unresolved complete check_design

19 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Problems in logfile:
read_sdc dtmf_recvr_core_gate.sdc
Statistics for commands executed by read_sdc
Reading file
Statistics for commands executed by read_sdc:
"create_clock" - successful 7 , failed 0 (runtime 0.00)
"current_design" - successful 3 , failed 0 (runtime 0.00)
"get_clocks" - successful 364 , failed 0 (runtime 0.00)
"get_pins" - successful 7 , failed 0 (runtime 0.00)
"get_ports" - successful 369 , failed 0 (runtime 0.00)
"set_case_analysis“ - successful 2 , failed 0 (runtime 0.00)
"set_false_path" - successful 2 , failed 0 (runtime 0.00)
"set_input_delay" - successful 175 , failed 0 (runtime 0.00)
"set_max_fanout" - successful 1 , failed 0 (runtime 0.00)
"set_max_transition" - successful 1 , failed 0 (runtime 0.00)
"set_output_delay“ - successful 189 , failed 0 (runtime 0.00)
Total runtime0

20 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Problems in logfile:
report timing -lint
-------------------------------------------------------------------------------
Sequential data pins driven by a clock signal

The following sequential data pins are driven by a clock signal:

/designs/dtmf_recvr_core/instances_hier/SPI_INST/instances_seq/present_state_reg[0]/pins_in/d
/designs/dtmf_recvr_core/instances_hier/SPI_INST/instances_seq/present_state_reg[1]/pins_in/d
/designs/dtmf_recvr_core/instances_hier/SPI_INST/instances_seq/present_state_reg[2]/pins_in/d
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
Sequential clock pins without clock waveform

The following sequential clock pins have no clock waveform driving them. No
timing constraints will be derived for paths leading to or from these pins.

/designs/dtmf_recvr_core/instances_hier/TDSP_DS_CS_INST/instances_seq/t_bit_7_reg/pins_in/clk
/designs/dtmf_recvr_core/instances_hier/TDSP_DS_CS_INST/instances_seq/t_sel_7_reg/pins_in/clk
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
Inputs without clocked external delays

The following primary inputs have no clocked external delays. As a result the
timing paths leading from the ports have no timing constraints derived from
clock waveforms. The'external_delay' command is used to create new external
delays.

/designs/dtmf_recvr_core/ports_in/Avdd
/designs/dtmf_recvr_core/ports_in/Avss
/designs/dtmf_recvr_core/ports_in/VDD_AO
... 6 other warnings in this category.
Use the -verbose option for more details.

21 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Problems in logfile:
report timing -lint
-------------------------------------------------------------------------------

22 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Problems in logfile:
report timing -lint

Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signa 3
Sequential clock pins without clock waveform 2
Sequential clock pins with multiple clock waveforms 0
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 0
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 9
Outputs without clocked external delays 9
Inputs without external driver/transition 34
Outputs without external load 36
Exceptions with invalid timing start-/endpoints 0

Total: 93

23 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Running Genus Interactively to Debug a run script
 You can cut-and-paste a template run script, line-by-line, into an interactive
Genus session to debug any problem with the script.

 You can cut-and-paste a SDC file line-by-line :

legacy_genus:> create_clock –period 1.0 [get_ports clk]

 The most common problem with read_hdl or elaborate is that the specified file
list was incomplete, had a bad search_path, or had typos.

 The most common problem with SDC constraints is that the object can not be
found in Genus – the logfile lists a detailed explanation of each error.

 Combinational feedback loops are caused either by design or by unexpected

timing paths in the cells.

23 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Logfile Exclusive: Global Optimization Targets
Global mapping target info
==========================
Cost Group 'I2C' target slack: 231 ps
Target path end-point (Pin: SPI_INST/present_state_reg[2]/d)

Pin Type Fanout Load

Arrival
(fF) (ps)
---------------------------------------------------------------------------------------------------------------------------------
(clock refclk) <<< launch 8000 F
(create_clock_delay_domain_1_refclk_F_0) ext delay
refclk in port 1 7.0
PLLCLK_INST/refclk
PLLCLK_INST/clk1x (u) (P) pll 3 15.0
SPI_INST/spi_clk
g348/in_1
g348/z (u) unmapped_or2 2 10.0
g403/in_0
g403/z (u) unmapped_or2 1 5.0
g422/in_0
g422/z (u) unmapped_nor2 1 5.0
present_state_reg[2]/d <<<
unmapped_d_flop
present_state_reg[2]/clk setup
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - -
(clock m_clk) capture 16000 R
---------------------------------------------------------------------------------------------------------------------------------
Cost Group : 'I2C' (path_group 'I2C')
Start-point : refclk
End-point : SPI_INST/present_state_reg[2]/d

(P) : Instance is preserved

(u) : Net has unmapped pin(s).

The global mapper estimates a slack for this path of 7484ps.

24 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Logfile Exclusive: Global Optimization Targets
A target is printed for every specified clock domain & cost group.

Always check the target #s before proceeding further. Positive target is

good.

If target is too negative then either something is wrong in the constraints
or there is bug in the tool. Fix the constraint.

Target drives the tool to optimize those paths

Path adjust your I/Os so they are not showing up in target; false paths &
multicycle paths shouldn't show up either. (We’ll discuss path_adjust
later)

25 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Logfile Exclusive: Incremental Optimization Results

Global incremental optimization status

======================================
Group
Tot Wrst
Total Weighted
Operation Area Slacks
-------------------------------------------------------------------------------
global_incr 237415 0

Incremental optimization status

===============================
Group
Tot Wrst Total - - - - DRC Totals - - - -
Total Weighted Neg Max Max Max
Operation Area Slacks Slack Trans Cap Fanout
--------------------------------------------------------------------------------------------
init_delay 237326 0 0 0 0 14

26 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Look at your Timing Reports!
 Understanding a typical Genus Timing Report
============================================================
Module: dtmf_recvr_core
Technology libraries: slow_1v0
pll 0.0
CDK_S128x16 0.0
CDK_S256x16 0.0
CDK_R512x16 0.0
physical_cells
Operating conditions: slow
Interconnect mode: global
Area mode: physical library
============================================================

Pin Type Fanout Load Arrival

(fF) (ps)
---------------------------------------------------------------------------------------------------
(clock m_clk) <<< launch 0R
PM_INST
cb_seqi
clk_enable_reg_reg/clk
clk_enable_reg_reg/q (u) unmapped_d_flop 2 10.0
cb_seqi/clk_enable
PM_INST/clk_enable
TEST_CONTROL_INST/tdsp_clk_enable
preserved pin <<< (b)
(clk_gating_check_2) ext delay
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - -
(clock refclk) capture 16000 R
---------------------------------------------------------------------------------------------------
Cost Group : 'refclk' (path_group 'refclk')
Start-point : PM_INST/cb_seqi/clk_enable_reg_reg/clk
End-point : preserved pin

(u) : Net has unmapped pin(s). (b) : Timing paths are broken.

The global mapper estimates a slack for this path of 11111ps.

27 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

The Genus Virtual Design Hierarchy Database
The structure of the database is populated after elaboration
legacy_genus:/> vls constants

instances_comb
/ “root” directory
instances_hier

instances_seq
designs
sdp_groups
Top_module
analysis_views

delay_corners
CW
hdl_libraries nets
DW01
ports_in
DW02
ports_out
libraries DW03
power
DWARE
constraint_modes
object_types CWTECH
dft
GTECH
nets
messages IEEE
physical
LPWARE
modules timing

28 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

 Messages printed out during synthesis

29 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Navigating the Virtual Design Hierarchy (DH)
When you invoke Genus:
 No information is written to hard disk
– by default, nothing is saved when you “exit” Genus, hence there is a virtual DH

 Genus allows you to navigate through both real directories where you run the
design and virtual design hierarchy. To navigate in virtual DH, Genus provides
unix-like commands. There is always a letter “v” comes in front of the commands
we use to navigate real directories:
• vcd <dirname> : setting the current directory in DH
• vcd <cr> : cd by itself will return you to the root directory “/”
• vpwd : shows the current directory in the design hierarchy
• vls : lists the objects in the current directory
• vls -a : lists the short list of the object’s attributes
• vls –la : lists the full list of the object’s attributes

Most common use of navigating the DH is to verify objects exist for use
in Genus/SDC commands

29 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Searching the DH with the ‘find’ command
The ‘find’ command is the most convenient method to locate all objects
that are part of the design hierarchy
legacy_genus:> find / -object_type <name_or_wildcard>

start looking in the root directory of the DH

Valid object types in Genus:

./ hdl_subprogram/ osc_source/
actual_scan_chain/ hinst/ osc_source_reference/
actual_scan_segment/ hnet/ pcell/
analysis_view/ hpin/ pdomain/
attribute/ hpin_bus/ pg_base_pin/
base_cell/ hport/ pg_lib_pin/
base_pin/ hport_bus/ pg_pin/
blackbox/ inst/ pin/
blockage/ isolation_rule/ pinstance/
boundary_scan_segment/ jtag_instruction/ pnet/
bump/ jtag_instruction_register/ port/
cell/ jtag_macro/ port_bus/
cell_model/ jtag_port/ power_domain/
clock/ layer/ power_intent_command/
cluster/ level_shifter_group/ power_intent_command_id/
constant/ level_shifter_rule/ power_mode/
constraint_mode/ lib_arc/ power_model/
cost_group/ lib_cell/ power_scope/
ctp_enable/ lib_pin/ programmable_direct_access_function/
30 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved
Valid object types in Genus(continued):
ctp_source/ library/ rc_corner/
ctp_timed_object/ library_domain/ region/
def_pin/ library_set/ root/
delay_corner/ macro_isolation_rule/ route_type/
design/ macro_model/ row/
dft_configuration_mode/ macro_power_domain/ scan_chain/
direct_access_function/ mbist_clock/ scan_segment/
domain_macro_parameter/ memory_bank_structure/ sdp_column/
exception/ memory_data_bit_structure/ sdp_group/
external_delay/ memory_lib_cell/ sdp_instance/
extraction_grid/ memory_lib_pin_action/ sdp_row/
fill/ memory_lib_pin_alias/ seq_function/
flow/ memory_library_domain/ site/
flow_step/ memory_spare_column/ slot/
formal_verification_constraint/ memory_spare_column_map_address/ specialnet/
fpobject/ memory_spare_column_map_data/ state_retention_rule/
gcell/ memory_spare_row/ style/
group/ memory_spare_row_map_address/ tap_port/
hdl_architecture/ message/ test_bus_interface/
hdl_bind/ message_group/ test_bus_port/
hdl_block/ mmmc_design/ test_clock/
hdl_component/ mode/ test_clock_domain/
hdl_configuration/ module/ test_signal/
hdl_implementation/ net/ timing_bin/
hdl_inst/ nominal_condition/ timing_condition/
hdl_label/ nondefaultrule/ timing_path/
hdl_lib/ obj_type/ track/
hdl_operator/ opcg_domain/ via/
hdl_package/ opcg_mode/ violation/
hdl_parameter/ opcg_trigger/ wireload/
hdl_pin/ opcond/ wireload_selection/
hdl_procedure/ operating_condition/ write_mask_bit/

31 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

The ‘find’ command returns a list of objects
You can use “find” command to pass objects to other
commands
Example:
legacy_genus:> vls -l [find /designs/ -port ports_out/*]

To parse a list of objects, use the Tcl “foreach” command

along with “find” command to pull out individual objects

legacy_genus:> set in_pins [find /designs/ -port ports_in/*]

legacy_genus:> foreach foo $in_pins {puts "$foo is an input pin"}

32 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Attributes
Use ‘set_attribute’ command to assign values to these attributes and use
‘get_attribute’ command to get values of these attributes

Syntax
set_attribute <attribute name> <value> <object>
get_attribute <attribute name> <object>

set_attribute information_level 5 /
get_attribute information_level /

Get help on all the available attributes:

legacy_genus:> get_attribute –h * *

‘*’ is a wildcard character matches zero or more characters

To get information on all the attributes containing the word “info”:
legacy_genus:> get_attribute *info* *

33 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Read Design
Purely RTL Flow
legacy_genus:> read_hdl [ –vhdl] <file_names>
– Requires elaboration
Purely Structural (netlist) design
legacy_genus:> read_netlist <netlist_name>
– Implicit, automatic, elaboration
Mixed (RTL and Structural) design
legacy_genus:> read_hdl [-vhdl] <file_names> and read_hdl –netlist <netlist_name>
– Requires elaboration
Note: Default language can be modified using the following
attribute:
legacy_genus:> set_attribute hdl_language { v1995 | v2001 | sv | vhdl } /
– Default value is v2001

34 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

QoS Related Attributes

Optimization of unused logic

legacy_genus :/> set_attribute optimize_constant_0_flops true /
legacy_genus :/> set_attribute optmize_constant_1_flops true /
legacy_genus :/> set_attribute optimize_constant_latches true /
legacy_genus :/> set_attribute delete_unloaded_seqs true /
legacy_genus :/> set_attribute delete_unloaded_insts true /

35 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Defining and using Cost Groups
###################################################################################
## Define cost groups (clock-clock, clock-output, input-clock, input-output)
###################################################################################
if {[llength [all::all_seqs]] > 0} {
define_cost_group -name I2C -design $DESIGN
define_cost_group -name C2O -design $DESIGN
define_cost_group -name C2C -design $DESIGN
path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C
path_group -from [all::all_seqs] -to [all::all_outs] -group C2O -name C2O
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
}
define_cost_group -name I2O -design $DESIGN
path_group -from [all::all_inps] -to [all::all_outs] -group I2O -name I2O

Default Genus creates “default” cost group where all the paths are put.
– This default group continues to exist where ungrouped paths are positioned.
– Multiple clocks in the same domain need multiple cost_groups for flop ==> flop paths.
– If clocks are defined by reading in SDC constraints file, the cost groups are
automatically created for each of these clocks and paths are grouped into these groups.
– Paths to and from RAM blocks can be put in separate cost_group.

36 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Synthesizing the Design
 Command ‘synthesize’ is still supported by Genus. New commands for synthesis
will be introduced later.
synthesize [-to_generic] [-to_mapped] [-to_clock_gated] [-to_placed] [-effort <string>]
[-incremental] [-no_incremental] [-spatial] [<design>+]

[-to_generic]:
stops after RTL is optimized (default for a design that has not been RTL-optimized)
[-to_mapped]:
stops after technology mapping (default for generic and mapped designs)
[-to_clock_gated]:
stops after design is clock gated
[-to_placed]:
stops after the design is placed and optimized
[-effort <string>]:
effort during optimization (high, medium(default), low, or express)
[-incremental]:
incrementally optimizes mapped gates
[-no_incremental]:
does not incrementally optimize mapped gates
[-spatial]:
performs a quick placement to optimize the mapped gates
[<design>+]:
the name of the design(s)
 If you would like to perform timing-driven rtl optimizations (sharing and

37 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

 speculation), you should set the ‘-effort’ to “high”

38 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

synthesize –to_generic
Converts into generic elements

Key Steps Involved

– Sharing and Speculation
Speculation only with -effort high
– Mux optimization
Merges and collapses muxes based on design characteristics
– CSA
Implements Carry Save based on design characteristics
control attribute: set_attribute dp_perform_csa_operations true/false /
– Flop deletion
Control attributes for constant propagation:
set_attribute optimize_constant_1_flops true/false /
set_attribute optimize_constant_0_flops true/false /

38 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

synthesize –to_mapped
Maps design to technology library

Multi-dimensional concurrent optimization based on defined

constraints
– Timing
– Power
– Area

39 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Synthesizing the Design Incrementally

legacy_genus>: synthesize –to_mapped –incremental

– Works with an already mapped design
– Incrementally optimize the mapped design
– Allows the mapper to preserve the current implementation of the
design and perform incremental optimizations if and only if the
procedure guarantees an improvement in the overall cost of the
design

40 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

New commands for synthesis in Genus

However, Genus provides new commands for “synthesis”,

which seperates “synthesis” into three steps:

RC Genus
synthesize –to_generic syn_generic
synthesize –to_mapped –no_incr syn_map
synthesize –to_mapped –incr syn_opt

These new commands are more straightforward and easy to

use

41 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

New commands for synthesis in Genus
More about new commands:
syn_generic [-physical] [<design>+]
[-physical]:
takes physical domain into consideration
[<design>+]:
the name of the design(s)

syn_map [-physical] [<design>+]

[-physical]:
performs physical optimization of the mapped gates
[<design>+]:
the name of the design(s)

syn_opt [-physical] [-incremental] [<design>+]

[-physical]:
performs physical optimization of the mapped gates [-
incremental]:
performs incremental optimization of the mapped gates
[<design>+]:
the name of the design(s)

42 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Using the path_adjust command

Path adjust command can be used to tighten (or loosen) the

timing constraint on a path or set of paths
legacy_genus:> path_adjust –from <object(s) –to <object(s)> –delay <delay_value>
– Assume that in RTL code, MA, MB,
and logic are all in the same block
– During synthesis, this appears to
be an easy path to satisfy
MB
– In reality, MA, MB, and logic are
spread across the die path_adjust
can be used to make path from MA
to MB appear more critical in synthesis
– Advantage of using path_adjust is
that it is not written out in the SDC
constraints, so P&R tool sees the MA

“real” timing

legacy_genus:> path_adjust –from MA –to MB –delay -100

43 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Reporting
Report command usage: report <option>
Most used subcommands:
area - prints an area report
boundary_opto - reports boundary optimization summary
case_analysis - prints a case_analysis report
cdn_loop_breaker - reports the cdn_loop_breaker instances
cell_delay_calculation - reports how the cell delay of a libcell instance is calculated
clock_gating - prints a clock-gating report
clocks - prints a clock report
congestion - reports congestion summary
datapath - prints a datapath resources report
design_rules - prints design rule violations
dft_chains - reports on DFT scan chains
dft_clock_domain_info - reports DFT clock domain information
dft_core_wrapper - reports the wrapper segments inserted for ports using the insert_dft wrapper_cell
command
dft_registers - reports on DFT status of registers
dft_setup - reports on DFT setup
dft_violations - reports DFT violations
gates - prints a gates report
hierarchy - prints a hierarchy report
instance - prints an instance report
low_power_cells - prints Low Power cells report
low_power_intent - prints Low Power Intent report
memory - prints a memory usage report
memory_cells - prints the memory cells in the library
messages - prints a summary of error messages that have been issued
44 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved
Reporting -- continued
mode - prints a mode report
module - prints a module report
multibit_inferencing - prints a multibit inferencing report
net_cap_calculation - reports how the capacitance of the net is calculated
net_delay_calculation - reports how the net delay is calculated
net_res_calculation - reports how the resistance of the net is calculated
Nets - prints a nets report
opcg_equivalents - reports the scan cell to opcg cell equivalent mappings specified using the
'set_opcg_equivalent' command
ple - reports physical layout estimation data
port - prints a port report
power - prints a power report
proto - reports prototype synthesis information
qor - prints a QOR report
scan_compressibility - reports the scan compressibility of a design by processing its actual compression
results generated using the analyze_scan_compressibility command
sequential - prints a sequential instance report
slew_calculation - reports how the slew on the driver pin of a libcell instance is calculated
summary - prints an area, timing, and design rules report
test_power - estimates the average scan power in shift and capture modes during test
timing - prints a timing report
units - reports units
utilization - reports how floorplan utilization is calculated
yield - prints a yield report

45 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Saving and Restoring a database:write_design
‘write_design’ generates a snapshot of the current design (in its current
state) so that it can later be restored.
write_design [-basename <string>] [-gzip_files] [-innovus] [-tcf] [-hierarchical] [<design>]

[-basename <string>]: path and base filename for output data

[-gzip_files]: compress netlist and constraints
[-innovus]: generate additional files needed for reload into Innovus
[-tcf]: generate TCF file
[-hierarchical]: generate additional setup needed for ILM flow
[<design>]: design
Generates following files:
– netlist (.v)
– write_script (.g)
– Genus script to restore the snapshot (.rc_setup.tcl)
– SDC (.sdc)
– config file (.conf) , scandef if the –innovus switch is used
– SOC Encounter script (.enc_setup.tcl)
– DEF, scandef, multi-mode and CPF file will also be written if appropriate

To restore a design database:

<unix>:> genus –legacy_ui –f outputs/top.rc_setup.tcl –log restore.log

46 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Mostly Used Interface commands

write_do_lec: writes out an LEC command file

write_atpg: writes out scan chains info for ATPG
write_do_ccd: writes out ccd dofile to run constraints check
write_do_clp: write dofile to check low power structures in design
write_do_verify_cdc: write dofile to check Clock domain crossing
write_sdc: write out constraints in Synopsys Design Constraint format (SDC)
write_sdf: write sdf file for design
write_set_load: writes the net load information for design

47 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

Summary

Going Through Logs & Reports :

Check for any unresolved references and empty modules (Search
Keyword: Unresolved)
Statistics for commands executed by read_sdc (Keyword: read_sdc)
Check for any warning messages or errors after report timing –lint
(Keyword: following)
Compare the difference in the datapath architecture before and after
global mapping by comparing datapath_map.rpt and
datapath_generic.rpt
The results will be written out to the _REPORTS_PATH directory. It will
contain all the area/timing/qor/gates/power reports and the conformal
dofile to run LEC (Logic Equivalency Check).

48 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved

References
 RAK Database:
– Testcase database, Scripts and references can be found at
‘Attachments’ and ‘Related Solutions’ sections below the PDF.
– This pdf can be searched with the document ‘Title’
on https://support.cadence.com

Online:
– https://support.cadence.com

 Email:
– [email protected]

Additional Resources:
unix:> which genus
– It shows “$path_to_tool_directory/tools.xxx/bin/genus ”
The documents can be found at
– “$path_to_tool_directory/doc/
49 Copyright © 2015 Cadence Design Systems, Inc. All Rights Reserved