CHAPTER 1 - AMPLIFIERS

Biasing Circuits for Transistors

In order to operate transistor in the desired region we have to apply external dc
voltages of correct polarity and magnitude to the two junctions of the transistor. This is
nothing but the biasing of the transistor. Because dc voltages are used to bias the
transistor, biasing is known as dc biasing of the transistor.
When we bias a transistor we establish a certain current and voltage conditions for the
transistor. These conditions are known as operating conditions or dc operating point or
quiescent point. The operating point must be stable for proper operation of the
transistor. However, the operating point shifts with changes in transistor parameters
such as β, Ico and VBE. As transistor parameters are temperature dependent, the
operating point also varies with changes in temperature. Let us see the different
methods to establish and stabilize the operating point.
The DC Load Line and Operating Point
Consider a common emitter circuit shown in the Fig. 1. The transistor in the Fig. 1 is biased
with a common supply such that the base emitter junction is forward biased and the
collector base junction is reverse biased, i.e. tranistor is in the active region.

Fig. 1 Common emitter amplifier Fig. 2

In the absence of ac signal, the capacitors provide very high impedance, i.e. open circuit.
Therefore, the equivalent circuit for common emitter amplifier becomes, as shown in the Fig. 2.
Applying Kirchhoff's voltage law to the collector circuit shown in the Fig. 2,
we get,
VCC-IC(RC + RE) - VCE = 0
VCC = IC(RC + RE) + VCE
where Ic (Rc + RK) is the voltage drop across RC and RE, and VCE is the collector to emitter voltage.
If we arrange the terms
 1  VCC
I C   VCE 
 RC  RE  RC  RE 
 1  VCC
  VCE   Rdc  RC  RE
 Rdc  Rdc
and compare this equation with equation of straight line y = mx + c, where m is the slope of the
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line and c is the intercept on Y-axis, then we can draw a straight line on the graph of IC versus VCE
which is having slope - l/Rdc and Y-intercept VCC/Rdc.
To determine the two points on the line we assume VCE = VCC and VCE = 0.
and
a) When VCE = VCC ; IC = 0 and we get a point A ;
b) When VCE = 0 ;
VCE= Vcc vce= 0 IC = VCC/Rdc and we get a point B
The Fig. 3 shows the output characteristics of a common emitter configuration with points A and
B, and line drawn between them. The line drawn between points A and B is called dc load line.
The 'dc’ word indicates that only dc conditions are considered, i.e. input signal is assumed to be
zero.
The dc load line is a plot of IC versus VCE. For a given value of RC, RE and a given level of VCC. Thus,
it represents all collector current levels and corresponding collector-emitter voltages that can
exist in the circuit. Knowing any one of IC, IB or VCE, it is easy to determine the other two from the
load line. The slope of the dc load line depends on the value of Rdc. It is negative and equal to
reciprocal of the Rdc..
Applying Kirchhoff's voltage law to the base circuit of Fig. 2. we get
VCC  I B RB  VBE  I E RE  0

VCC  I B RB  VBE  1   I B RE  0

 I B RB  1   RE   VCC  VBE

Fig. 3 Common emitter output characteristics with dc load line

VCC  VBE
 IB 
RB  1   RE
As VCC >> VBE ,
VCC
IB 
RB  1   RE
If we assume, VCC = 20 V, β = 49, RE = 100 and RB = 5K then IB = 2 m A. Now, if we draw the
characteristic curve for this value of IB; then intersection of this curve and dc load line is the
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operating point. This point is the fixed point on the characteristics, so it is called quiescent point
or Q point (Quiescent means quiet, still, inactive). For different values of I B, we have different
intersection points such as P, Q and R. All these points are quiescent points.
AC Load Line
We have seen that the total dc load for the transistor is RC + RE. However, when ac signal is
applied, RE gets bypassed by CR and RL comes in parallel with RC, as shown in the Fig. 4.
The Fig. 4 shows the ac equivalent circuit for Fig. 1. It is drawn by shorting capacitors and by
shorting VCC and ground terminals. Therefore, the ac load resistance Rac = RC || RL. With this ac
load resistance Rac we have to draw a new load line to describe the circuit performance when
signal is applied. Such a load line is called ac load line.

Fig 4 ac equivalent circuit

We know that, when no signal is applied, the transistor voltage and current conditions are as
indicated at the quiescent point (Q point) on the dc load line. When an ac signal is applied, the
transistor voltage and current vary above and below point Q. Therefore, point Q is common to
both the ac and the dc load lines. Starting from the Q point, the ac load line is drawn by taking a
convenient collector current change ∆ VCE = - ∆ICRac. The current and voltage changes are
measured from the Q point to obtain another point on the ac load line. The ac load line is drawn
through this point and point Q as shown in fig 5.

Fig. 5 Common emitter output characteristics with dc and ac load lines

It is important to note that the parallel combination Rc || RL (Rac) is always less than Rc + RE (Rdc).
Therefore, the slope of ac load line is always higher than the dc load line.
Selection of Operating Point
The operating point can be selected at three different positions on the dc load line: near
saturation region, near cut-off region or at the center, i.e. in the active region. Refer Fig. 3. The
selection of operating point will depend on its application. When transistor is used as an
amplifier, the Q point should be selected at the center of the dc load line to prevent any possible
distortion in the amplified output signal. This is well-understood by going through following
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cases.
Case 1: Biasing circuit is designed to fix a Q-point at point P, as shown in Fig. 6. Point P is very
near to the saturation region. As shown in Fig. 6 the collector current is clipped at the positive
half cycle. So, even though base current varies sinusoidally, collector current is not a useful
sinusoidal waveform, i.e. distortion is present at the output. Therefore, point P is not a suitable
operating point.

Fig. 6 Operating point near saturation region gives clipping at the positive peaks
Case 2 : Biasing circuit is designed to fix a Q-point at point R as shown in Fig. 7. Point R is very
near to the cut-off region. As shown in Fig. 7 the collector current is clipped at the negative half
cycle. So, point R is also not a suitable operating point.

Fig. 7 Operating point near cut-off region gives clipping at the negative peaks
Case 3 : Biasing circuit is designed to fix a Q-point at point Q as shown in Fig. 8. The output signal
is sinusoidal waveform without any distortion. Thus point Q is the best operating point.

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Fig. 8 Operating point at the center of active region is most suitable

Bias Stabilization
From the points discussed so far, it is clear that the biasing circuit should be designed to fix the
operating point or Q-point at the center of the active region. But only fixing of the operating point
is not sufficient. While designing the biasing circuit, care should be taken so that the operating
point will not shift into an undesirable region (i.e. into cut-off or saturation region).
Two important factors are to be considered while designing the biasing circuit which are
responsible for shifting the operating point.
1.Temperature
2. Transistor current gain β

Requirements of a Biasing circuit:

i) The emitter-base junction must be forward biased (forward biased voltage 0.6V to 0.7V)
and collector-base junction must be reverse biased (within maximum limits), i.e. the
transistor should be operated in the middle of the active region or operating point (Q-point)
should be fixed at the center of the active region.
ii) The circuit design should provide a degree of temperature stability.
iii)The operating point should be made independent of the transistor parameters (such as β).

Typical Biasing Circuit

Fig. 11 shows typical biasing circuit.
In this, the emitter-base junction is forward biased by the battery VBB and collector-base junction
is reverse biased by the battery VCC. The VBE required to forward bias E-B junction is very less
(0.7V for Si transistor and 0.3V for Ge transistor). It is very difficult to have a battery V BB of either
0.7V or 0.3V. So one resistance RB is connected in series with VBB so that VBB can be of 1.5V. RB
value can be adjusted according to VBB.

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Fig. 11 Biasing circuit 1.5V. RB value can be adjusted according to VBB.

The positive terminals of both the batteries are connected to collector and base of the transistor
through RC and RB respectively.
It is always convenient and preferable to have an electronic circuit that works on a single battery.
So some modifications are made in this circuit. Instead of using two batteries which is practically
inconvenient, single battery is used to obtain both the biasing voltages. The value of R B is now
modified according to value of single battery used, Vcc. This forms a fixed bias circuit.
Fixed Bias
Fig. 12 shows the fixed bias circuit.

Circuit Analysis :
Base Circuit : Let us consider the base circuit as shown in Fig. 13.
Fig. 13 Base circuit of the fixed bias circuit
Applying Kirchhoff's voltage law to the base circuit
We get,
VCC - IBRB - VBE = 0
Solving for the current IB

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VCC  VBE
IB 
RB
VCC
IB          VCC  VBE
RB
The supply voltage VCC is of fixed value. Once the resistance RB is selected, IB is also fixed. Hence
this circuit is called as 'fixed bias circuit'.

Collector circuit:
Fig. 14 Collector circuit of the fixed bias circuit
We now consider the collector circuit as shown in Fig. 14.
Applying Kirchhoff's voltage law to the collector circuit we get,
VCC - ICRC - VCE =0
=> VCE = VCC - ICRC
The collector current in CE configuration is given as,
IC = βIB +ICEO or IC ~= βIB
=> βIB >> ICEO
From above equations
VCC = ICRC + VCE
VCC  VCE
IC 
RC
i.e. supply voltage VCC provides the voltage across RC and the collector to emitter voltage.
Therefore, voltage drop across Rc can never be more than VCC.
i.e. ICRC < VCC
or IC < VCC/RC
If IC becomes greater than the value limited by above expression, the operating point will lie in
the saturation region of the characteristics.

Advantages of fixed bias circuit :

1) This is a simple circuit which uses very few components.
2) The operating point can be fixed anywhere in the active region of the characteristics by
simply changing the value of RB. Thus, it provides maximum flexibility in the design.
Disadvantages of fixed bias circuit :
1) This circuit does not provide any check on the collector current which increases with the rise
in temperature, i.e. thermal stability is not provided by this circuit. So the operating point is not
maintained.
IC = βIB + ICEO
2) Since IC = βIB and IB is already fixed; IC depends on β which changes unit to unit and shifts the
operating point.
Thus stabilization of operating point is very poor in the fixed bias circuit.

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Because of these disadvantages, fixed bias circuit requires some modifications. In the modified
circuit, RB is connected between collector and base. Hence the circuit is called 'collector to base
bias circuit'.
Collector to Base Bias Circuit
Fig. 1.17 shows collector to base bias circuit. It is an improvement over the fixed-bias method. In
this the biasing resistor is connected between the collector and the base of the transistor. ThusIB
flows through RH and (Ic +IB ) flows through the Rc.

Fig. 17 Collector-to-base bias circuit

Voltage Divider Bias or Emitter Bias
Fig. 20 shows the voltage divider bias circuit. In this circuit, the biasing is
provided by three resistors : R1, R2 and RE. The resistors R1 and R2 act as
a potential divider giving a fixed voltage to point B which is base. If
collector current increases due to change in temperature or change in β,
the emitter current IE also increases and the voltage drop across RE
increases, reducing the voltage difference between base and emitter
(VBE). Due to reduction in VBE , base currently and hence collector current
IC also reduces. This reduction in collector current Ic compensates for the
original change in IC.

Fig. 20 Voltage divider bias circuit

Biasing of FET
Like BJT, the parameters of FET are also temperature dependent. In FET, as temperature
increases drain resistance also increases, reducing the drain current. Thus unlike BJT, thermal
runaway does not occur with FET. However, the wide differences in maximum and minimum
transfer characteristics make it necessary to keep drain current ID stable at its the quiescent
value. Let us see various biasing circuits used for FET and MOSFET amplifiers.
Fixed-bias Circuit

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Fig. 27 shows the fixed bias circuit.
Fig. 27 Fixed bias circuit

For the dc analysis coupling capacitors are open

circuits. The current through ,RG is IG which is zero.
This permits RG to replace by short circuit
equivalent, simplifying the fixed bias circuit as
shown in the Fig. 28.

Fig. 28 Simplified fixed bias circuit

We know for dc analysis

IG = 0A
and applying KVL to the input circuit we get,
VGS + VGG = 0
VGS = - VGG
Since VGG is a fixed dc supply, the voltage VGS is fixed in
magnitude, and hence the name fixed bias circuit.
For fixed bias circuit the drain current ID can be given
2
 V 
by I D  I DSS 1  GS 
 VP 
The drain to source voltage of output circuit can be determined by applying KVL
+ VDS +IDRD -VDD = 0
 VDS = VDD - IDRD

Voltage Divider Biasing Circuit

Fig. 30 shows the voltage divider bias circuit

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Fig. 30 Voltage divider bias

This circuit is similar to the voltage divider bias circuit used for transistor.
R2
As I G = 0, we can write VG  VDD as shown in fig 31.
R1  R2
Applying KVL to the input circuit we get,
VG - VGS -VS = 0
 VGS = VG - VS
 = VG - IS RS
 = VG - ID RS ( since ID = IS)
VGS = VG - ID RS
Applying KVL to the output circuit we get,
VDS + ID RD +VS - VDD = 0
 VDS = VDD - ID RD - ID RS
 = VDD - ID(RD + RS)

Fig. 31 Simplified voltage divider circuit for dc analysis

Self Bias Circuit

Fig. 33 shows the self bias circuit. It eliminates the need for two dc supplies. As mentioned
earlier, for dc analysis we can replace coupling capacitors by open circuits and we can also
replace the resistor RG by a short circuit equivalent, since IG = 0.

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Fig. 33 Self bias circuit

Fig. 34 shows simplified circuit with self bias for dc analysis.

Fig. 34 simplified self bias circuit for dc analysis

Applying KVL to input circuit we get,
- VGS - VS = 0
=> VGS = - VS = - IS RS
We know the above equations gives the relation between ID and VGS
2
 V 
I D  I DSS 1  GS 
 VP 
Substituting value of VGS in above equation we get,
2
  I D RS 
I D  I DSS 1  
 VP 

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2
 I R 
I D  I DSS 1  D S 
 VP 
Applying KVL to the output circuit we get,
VS +- VDS + ID RD – VDD = 0
 VDS = VDD - VS - ID RD
 = VDD - ID RS - ID RD
 = VDD - ID (RS + RD)
VDS = VDD - ID (RS + RD)

CE, CC and CB Amplifiers

An amplifier is used to increase the signal level; i.e. the amplifier is used to get a larger signal
output from a small signal input. We will assume a sinusoidal signal at the input of the amplifier.
At the output, signal must remain sinusoidal in waveform, with frequency same as that of the
input.
To make the transistor work as an amplifier, it is to be biased to operate in the active region, i.e.
base-emitter junction is to be forward biased, while base-collector junction to be reversed biased.
Let us consider the common emitter amplifier circuit using self bias or voltage divider bias as
shown in the Fig. 42.

Fig. 42 Common emitter amplifier

In the absence of input signal, only dc voltage are present in the circuit This is known as zero-
signal or no-signal condition or quiescent condition for the amplifier. The dc collector-emitter
voltage, VCE , the dc collector current IC and dc base current IB is the quiescent operating point for
the amplifier. On this dc quiescent operating point, we superimpose ac signal by application of ac
sinusoidal voltage at the input. Due to this base current varies sinusoidally, as shown in Fig.
42(a).

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Fig. 42(a) IBQ is quiescent DC base current

Since the transistor is biased to operate in the active region, the output is linearly proportional to
the input. The output current i.e. the collector current is β times larger than the input base
current in common emitter configuration. Hence the collector current will also vary sinusoidally
about its quiescent value, ICQ. The output voltage will also vary sinusoidally as shown in the
Fig.43 (a) and 43 (b).

Fig. 43 (a) (b)

Fig. 43 (c) Graphical representation of base current, collector current, and collector-emitter voltage
swings
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Then variations in the collector current and the voltage between collector and emitter due to
change in the base current are shown graphically with the help of load line in Fig. 43. The
collector current varies above and below its Q point value in-phase with the base current and the
collector to emitter voltage varies above its Q point value 1800 out of phase with the base voltage,
as illustrated in fig 43(c).
When one cycle of input is completed, one cycle of output will also be completed. This means the
frequency of output sinusoidal is the same as the frequency of input sinusoid. Thus in the
amplification process, frequency of the output signal does not change, only the magnitude of the
output is larger than that of the input.
Common Emitter Amplifier Circuit
Fig. 44 shows the practical circuit of common emitter transistor amplifier. It consists of different
circuit component. The functions of these components are as follows:
1. Biasing Circuit
The resistances R1, R2 and RE forms the voltage divider biasing circuit for the CE amplifier. It sets
the proper operating point for the CE amplifier.
2. Input Capacitor C1
This capacitor couples the signal to the base of the transistor. It blocks any dc component present
in the signal and passes only ac signal for amplification. Because of this biasing conditions are
maintained constant.

Fig. 44 Practical common emitter amplifier circuit

3. Emitter Bypass Capacitor CE
An emitter bypass capacitor CF is connected in parallel with the emitter resistance, RE to provide
a low reactance path to the amplified ac signal. If it is not inserted, the amplified ac signal passing
through RE will cause a voltage drop across it. This will reduce the output voltage, reducing the
gain of the amplifier.
4. Output Coupling Capacitor C2
The coupling capacitor C, couples the output of the amplifier to the load or to the next stage of the

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amplifier. It blocks dc and passes only ac part of the amplified signal.
Need for C1, C2 and CE
We know that, the impedance of capacitor is given as
1
XC 
2fC
Thus, at signal frequencies all the capacitors have extremely small impedance and it can be
treated as an ac short circuit. For bias/dc conditions of the transistor all the capacitors act as a dc
open circuit. With this knowledge we will see the importance of C1, C2 and CE.
Consider that the signal source is connected directly to the base of the transistor as shown in
Fig. 45.
Looking at the Fig. 45 we can immediately notice that source resistance Rs is in parallel with R2 .
This will reduce the bias voltage at the transistor base and, consequently alter the collector
current, which is not desired. Similarly, by connecting RL directly, the dc levels of VC and VCE will
change. To avoid this and maintain the stability of bias condition coupling capacitors are
connected. As mentioned earlier, coupling capacitors act as open circuits to dc, maintain stable
biasing conditions even after connection of RS and RL. Another advantage of connecting Q is that
any dc component in the signal is opposed and only ac signal is routed to the transistor amplifier.
The emitter resistance RF is one of the component which provides bias stabilization. But it also
reduces the voltage swing at the output. The emitter bypass capacitor CE provides a low reactance
path to the amplified a.c. signal increasing the output voltage swing.
For the proper operation of the circuit, polarities of the capacitors must be connected correctly.
The curve bar which indicates negative terminal must always be connected at a dc voltage level
lower than (or equal to) the dc level of the positive terminal (straight bar). For example, C1 in
Fig. 44 has its negative terminal at dc ground level, because it is grounded through the signal
source resistance Rs. The positive terminal of C, is at + VB with respect to ground.
Phase Reversal
The phase relationship between the input and output voltages can be determined by considering
the effect of a positive half cycle and negative half cycle separately. Consider the positive half
cycle of input signal in which terminal A is positive w.r.t. B. Due to this, two voltages, ac and dc
will be adding each other, increasing forward bias on base emitter junction. This increases base
current. The collector current is β times the base current, hence the collector current will also
increase. This increases the voltage drop across RC. Since VC = VCC – IC RC, the increase in IC results
in a drop in collector voltage VC , as VCC is constant. Thus, as Vi increases in a positive direction, V0
goes in a negative direction and we get negative half cycle of output voltage for positive half cycle
at the input.
In the negative half cycle of input, in which terminal A becomes negative w.r.t. terminal B, the ac
and dc voltages will oppose each other, reducing forward bias on base-emitter p-n junction. This
reduces base current. Accordingly collector current and drop across RC both reduce, increasing
the output voltage. Thus, we get positive half cycle at the output for negative half cycle at the
input. Therefore, we can say that there is a phase shift of 180°between input and output voltages
for a common emitter amplifier.
Common Collector Amplifier Circuit
The Fig. 46 shows common collector circuit. The dc biasing is provided by R1 R2, and RE . The load
resistance is capacitor coupled to the emitter terminal of the transistor.
Signal

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Fig. 46 Common collector circuit

When a signal is applied via to the base of the transistor, VB is increased and decreased as the
signal goes positive and negative, respectively. Looking at Fig. 46 we can write that VE = VB - VBE.
Considering VBE fairly constant, we say that variation in the VB appears at emitter and emitter
voltage VE will vary same as base voltage VB. Since the emitter is output terminal, it can be noted
that the output voltage from a common collector circuit is the same as its input voltage. In other
words, we can say that in common collector circuit emitter terminal follows the signal voltage
applied to the base. Hence the common collector circuit is also known as an emitter follower.

Common Base Amplifier Circuit

Fig. 47 shows common base circuit. The signal source is coupled to the emitter of the transistor
via C1, The load resistance RL is coupled to the collector of the transistor via C2.

Fig. 47 Common base circuit

The positive going pulse of input source increases the emitter voltage. As base voltage is constant,
the forward bias of emitter base junction reduces. This reduces Ib , reducing IC and hence the drop
across RC. Since V0 = VCC – IC RC , the reduction in IC results in an increase in V0. Therefore, we can
say that positive going input produces positive going output and similarly negative going input
produces negative going output and there is no phase shift between input and output in a
common base amplifier.
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Hybrid Model
Let us consider transistor amplifier as a black box as shown in the Fig. 48.

Fig. 48 Transistor amplifier

Here, Ii : is the input current to the amplifier
Vi : is the input voltage to the amplifier
I0 : is the output current of the amplifier and
V0 : is the output voltage of the amplifier
As we know transistor is a current operated device, input current is an independent variable. The
input current, Ii and output voltage VO devices the input voltage Vi as well as the output current I0.
Hence input voltage Vi and output current I0 are the dependent variables, whereas input current
Ii, and output voltage VO, are independent variables. Thus we can write
Vi  f1 I i ,VO 
I O  f 2 I i ,VO 

This can be written in the equation form as follows

Vi  h11I i  h12VO
I O  h21I i  h22VO
The above equations can also be written with alphabetic notations,
Vi  hi .I i  hr .VO
I O  h f .I i  hO .VO
The parameters in the above equation are defined as follows :
Vi
h11  = input resistance with output short circuited, in ohms,
Ii VO  0

Vi
h12  = fraction of output voltage at input with input open circuited.
VO I i 0

IO
h21  = Forward current transfer ratio or current gain with output short circuited.
Ii VO  0

IO
h22  = Output admittance with input open circuited, in mhos.
VO I i 0

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From the above discussion we can say that, these four parameters are not same. They have
different units. In other words, they are mixture of different units and hence referred to as hybrid
parameters. As we use small letters for ac analysis, these are commonly known as h-parameters.
The standard notations can be given as
i = 11 = input o = 22 = output
f = 21 = forward transfer r = 12 = reverse transfer
thus we can write h-parameters as follows.
a) With output short circuited
h11 = hi = Input resistance
h21 = hf = Short circuited current gain
b) With input open circuited
h12 = hr = Reverse Voltage transfer ratio
h22 = hO = Output admittance
In order to analyze transistorized amplifier circuit and calculate its input impedance, output
impedance, current gain and voltage gain, it is necessary to replace transistor circuit with its
equivalent. The equivalent circuit can be drawn with the help of two equations, as shown in
fig. 49.

Fig 49 Hybrid model or equivalent circuit of transistorized amplifier

Vi  hi .I i  hr .VO
I O  h f .I i  hO .VO

Many transistor models have been

proposed, each one having its
advantages and disadvantages. The
transistor model used in this text is
in terms of h-parameters.

Benefits of h-parameters
1. Real numbers at audio frequencies.
2. Easy to measure.
3. Can be obtained from the transistor static characteristic curves.
4. Convenient to use in circuit analysis and design.
5. Most of the transistor manufacturers specify the h-parameters.

To see how we can derive a hybrid model for a transistor, let us consider the common emitter
configuration shown in Fig. 50. The variables I b, Ic, Vh and Vc represent total instantaneous

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currents and voltages.

lb = input current
Ic = output current
Vbe = input voltage
Vcc = output voltage
Fig 50 Simple common Emitter
configuration
Fig. 51 shows the h-parameter
equivalent circuit for the common
emitter configuration.

Fig. 51 h-parameter equivalent circuit for the common emitter configuration

From the h-parameter equivalent circuit of the common emitter configuration we can write,
Vbe  hie .I b  hre .Vce
I c  h fe .I b  hoe .Vce
where
VBE VBE I C I C
hie  hre  h fe  hoe 
I B VCE Constan t
VCE I B Constan t
I B VCE Constan t
VCE I B Constan t

The quantities ΔVBE (Vbe), ΔVCE (Vce), ΔIB (Ib) and ΔIc (Ic) represent the small change in base and
collector voltages and currents.
As mentioned earlier, transistor can be represented as a two port network by making any one
terminal common between input and output. Since there are three possible configurations in
which a transistor can be used, there is a change in terminal voltage and current for different
transistor configurations. For different configurations the relation between input parameters and
output parameters also differs. Therefore, one needs to define different set of h-parameters for
different configurations. To designate the type of configuration another subscript is added to the
h-parameters.
For example :
hie = h11e = input resistance in common emitter configuration.
hfb = h21b = short-circuit current gain in common base configuration.
The Table 1 summarizes the h-parameters for all the three configurations.

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 CHAPTER 1 - AMPLIFIERS

Parameter CB CE CC
Input resistance hib hie hic
Reverse voltage gain hrb hre hrc
Forward transfer current gain hfb hfe hfc
Output admittance hob hoe hoc
Table 1

Fig. 52 Transistor configurations and their hybrid models

The basic circuit of hybrid model is same for all the three configurations, only parameters are
different. The Fig. 52 shows the transistor configurations and th< hybrid models.
The circuits and equations in Fig. 52 are valid for either an n-p-n or p-n-p transistor and are
independent of the type of load or method of biasing.
Determination of h-Parameters from Characteristics
Let us consider common emitter configuration. Its functional relationship can be defined from
equations below
Vbe  f1 I b ,Vce 
I c  f 2 I b ,Vce 
We know that the input characteristic curves give the relationship between voltage VBE and the
input current IB for different values of output voltage VCE.
Fig. 53 shows typical input characteristic curves for the common emitter configuration.

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 CHAPTER 1 - AMPLIFIERS

Fig. 53 Typical input characteristic curves for common emitter configuration

Determination of hfe and hoe from Output Characteristic Curves
Parameter hie :
From equation we have,
VBE VBE 2  VBE1
hie  =
I B VCE Constan t
I B 2  I B1
The Parameter hie can be obtained as the change in the base voltage,VBE2 – VBE1, divided by the
change in the base current IB2 – IB1, for the constant collector voltage at the quiescent point, Q.
The slope of the line EF, drawn tangent to the input characteristic curve at the point Q gives hie.
Parameter hre :
From equation we have,
VBE VBE 2  VBE 1
hre  =
VCE I B Constan t
VCE 2  VCE1
A horizontal line on the input characteristics of fig 54 represents constant base current. The
parameter hre can be obtained as the change in base voltage VBE2 – VBE1, divided by the change in
the collector voltage VCE2 – VCE1, for a constant base current IB, at the quiescent point Q.
The output characteristic curves gives the relationship between output current, IC and output
voltage , VCE for different values of input current IB. fig 54 shows typical output characteristic
curves for the common emitter configuration.

Fig. 54 Typical output characteristic curves for common emitter configuration

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 CHAPTER 1 - AMPLIFIERS
Parameter hfe :
From equation we have,
I C I C 2  I C1
h fe  =
I B VCE Constan t
I B 2  I B1
It is the ratio of change in collector current IC taken around the quiescent point Q to the
corresponding change in the base current IB for constant value of output voltage VCE at the Q
point.
Parameter hoe :
From equation we have,
I C I C 2  I C1
hoe  =
VCE I B Constan t
VCE 2  VCE1
The parameter hoe can be obtained as the change in the collector current, IC2 – IC1, divided by the
change in the collector voltage, VCE2 - VCEI, for a constant base current at the quiescent point Q.
The slope of the line AB, drawn tangent to the output characteristic curve at the point Q gives h oe.
By using similar procedure it is possible to obtain h-parameters for common base and common
collector configurations from the appropriate input and output characteristic curves.
From the above discussion it can be noticed that h-parameters are always calculated at quiescent
operating point of the amplifier. The h-parameter values depend on the quiescent point Q. As Q
point varies due to temperature changes, h-parameters also varies due to temperature changes.

Analysis of BJT Amplifier Circuit Using h-Parameters

The Fig. 55 shows basic amplifier circuit. From the Fig. 55 we can notice that to form a transistor
amplifier only it is necessary to connect an external load and signal source, along with proper
biasing. Fig. 55 represents a transistor in any one of the three possible configurations.

Fig. 55 Basic transistor amplifier

We can replace transistor circuit shown in Fig. 55 with its small signal hybrid model as shown in
Fig. 56.

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 CHAPTER 1 - AMPLIFIERS
Fig. 56 Transistor amplifier in its h-parameter model
Let us analyze hybrid model to find the current gain, the input resistance, the voltage gain, and
the output resistance.
Current Gain (Ai) :
For transistor amplifier Ai is defined as the ratio of output to input currents. It is given
IL I
by, Ai   2
I1 I1
Here IL and l2 are equal in magnitude but opposite in sign, i.e. IL=-I2
From the circuit of Fig. 56 We have,
I 2  h f I1  hoV2
Substituting V2 =-I2 RL in the equation we obtain
I 2  h f I1  ho  I 2 RL 
 I 2  ho I 2 RL   h f I1
hf
 1  ho RL I 2  h f I1
I2
 
I1 1  ho RL 

I2 hf
Ai   
I1 1  ho RL
Current Gain (AIs ) :
It is the current gain taking into account the source resistance, Rs if the model is driven by the
current source instead of voltage source. It is given by
I2 I I I1
Ais     2 . 1 => Ais  Ai .
Is I1 Is Is

Fig 57 (a) Input section of (b) input section of Hybrid model with current source
hybrid model instead of voltage source.
Looking at fig 57 (a) and using current divider equation we get,
I S RS
I1 
Z i  RS
I1 RS
 
I S Z i  RS

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 CHAPTER 1 - AMPLIFIERS

Ai RS
And hence Ais 
Z i  RS
Input Impedance (Ri)
As shown in fig 55, Ri is the input resistance looking in to the amplifier input terminals (1, 1‘). It is
given by,
V1
Ri 
I1
For the input circuit of fig 56, we have
V1 = hi I1 + hr V2
V1 hi .I1  hr .V2
Hence Ri  
I1 I1
.V2
Ri  hi  hr
I1
Substituting V2 = - I2 RL = Ai I1 RL In the above equation we get,
hr . Ai .I1 .RL
Ri  hi 
I1
Ri  hi  hr . Ai .RL
hf
Substituting Ai  
1  ho RL
hr .h f
Ri  hi 
1 RL  ho
hr .h f
Ri  hi  where YL = 1/RL
YL  ho
From this equation we can quote that the input Impedance is a function of the load impedance.
Voltage gain (AV) :
It is the ratio of output voltage V2 to the input voltage V1 . It is given by
V2
AV 
V1
Ai .I1 .RL Ai .RL
From equations we have AV  
V1 Zi
Dividing numerator and denominator by RL we get
I1 . 1
Since, 
V1 Z i
Voltage Gain (Avs) :
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 CHAPTER 1 - AMPLIFIERS
It is voltage gain including the source. It is given by,
V2 V2 V1
AVS   
VS V1 VS
V1
AVS  AV 
VS
Looking at Fig. 58 and applying potential divider theorem
we can write,
Zi
V1  VS
RS  Z i
V1 Zi
 
VS RS  Z i
Substituting value of V1/VS in equation We get,
Ri
AVS  AV 
RS  Ri
Ai .RL .A R
  AV  i L
RS  Ri Ri

Output Admittance Y0 :
It is the ratio of output current I2 to the output voltage V2 It is given by,
I2
Yo  .with.VS  0
V2
From equation, we have, I 2  h f I1  hoV2 , Dividing above equation by V2 we get,
I 2 h f I1
  ho
V2 V2

I 2 h f I1
Yo    ho
V2 V2
From Fig. 56, with Vs = 0 we can write,
Rs IS +hi Ii + hr V2 = 0
 (Rs +hi ) Ii = - hr V2
I1 hr
 
V2 RS  hi
Substituting value of I1/V2 from previous equation ,
h f hr
we obtain, Yo  ho 
hi  RS

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 CHAPTER 1 - AMPLIFIERS
From this equation we can note that output admittance is a function of the source resistance.
Power Gain ( AP ) :
It is the ratio of average power delivered to the load RL, to the input power. Output power is given
as
P2 = V2 . IL = -V2 I2
Since the input power is P1 = V1 I1 the operating power gain AP of the transistor is defined as
P2 V I R Ai RL
AP    2 2  AV . Ai  Ai2 L  AV 
P1 V1 I1 Ri Ri
Relation Between AVS and AIS :
From above equations we have
Ai .RL Ai .RS
AVS  and AiS 
RS  Ri RS  Ri
Taking ratio of above two equations we get,
AVS .RL .RL
  AVS  AiS .
AiS RS RS

Table 2 summarizes small signal analysis of a transistor amplifier

hf
Ai  
1  ho RL
Ai RS
Ais 
Z i  RS
hr .h f
Ri  hi  hr . Ai .RL = hi 
YL  ho
Ai .RL
AV 
Zi
Ri Ai RL A R
AVS  AV  =  iS L
RS  Ri Ri  RS RS
h f .hr 1
Yo  ho  
hi  RS Ro

.RL
AP  AV . Ai  Ai2
Ri
Table 2

Table 3 shows the typical values of h parameters for three different configurations at normal
room temperature and at quiescent operating point IEQ = 4.3 mA
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 CHAPTER 1 - AMPLIFIERS

Parameter CE CC CB

h11 = hi 1100Ω 1100Ω 21.6Ω

h12 = hr 25 x10- 4 ~1 29 x10- 4

h21 = hf 50 - 51 -0.98

h22 = ho 25 µA/V 25 µA /V 0.49 µA /V

Table 3
Guidelines for Analysis of a Transistor Circuit
In the previous section we have seen generalized transistor circuit analysis using h-parameters.
There are many transistor circuits. Circuits may consist of different biasing techniques, different
configurations and so on. The analysis of such transistor circuits for its small signal behavior can
be made by following simple guidelines. These guidelines are :
1. Draw the actual circuit diagram.
2. Replace coupling capacitors and emitter bypass capacitor by short circuit.
3. Replace dc source by a short circuit. In other words, short Vcc and ground lines.
4. Mark the points B(base), C(collector), E(emitter) on the circuit diagram and locate these points
as the start of the equivalent circuit.
5. Replace the transistor by its h-parameter model.
Following example explains us how to use guidelines for the analysis of a transistor circuit.
Consider a common emitter amplifier with voltage divider bias circuit as shown in the Fig. 59 (a)

(a) Actual circuit diagram Fig. 59 (b) Circuit with capacitors as a short circuit

Guideline 1: Draw actual circuit diagram

Guideline 2 : Short coupling and bypass capacitors
Guideline 3 : Short Vcc and ground lines
Guideline 4 : Mark point= B, C, E and locate these points as the start of the equivalent
circuit

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 CHAPTER 1 - AMPLIFIERS

(c) Circuit with Vcc and ground short circuit (d) Circuit with B, C and E points located
Fig. 59
Guideline 5 : Replace transistor by its h-parameter model
and calculate effective Ri (Ri’) and effective R0 (R'0). For example, in above
circuit R’i = R1 || R2 || Ri
and R'0 = R0 || Rc.
with these guidelines we will analyze CE,CB and CC amplifier circuits in coming sections.

Fig. 59 (e) Circuit with transistor replaced by h-parameter equivalent

From Table 2 we can write the generalized formulae for common emitter, common I collector and
common base configurations. However, in most of the times h-parameters are specified for
common emitter configuration, therefore, for analysis of common collector and common base
configurations we have to first convert given h-parameters for common emitter configuration
into the desired configuration by using conversion formulae given in Table 14.
h-parameter conversion table :

Symbol Common emitter Common Common base T equivalent

collector circuit

hie 1,100 Ω hie * hib re

rb 
1  h fb 1 a

hre 25 x10-4 1 - hrc * hib hob re

 hrb
1  h fb 1  a re

hfe 50 - (1 + hfc) * h fb a

1  h fb 1  a 

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 CHAPTER 1 - AMPLIFIERS

hoe 25µA/V hoe* hob 1

1  h fb 1  a rc

hib hie hie 21.6Ω re + (1 - a) rb


1  h fe h fe

hrb hie hoe hic hoc 29 x 10- 4 rb

 hre hre  1
1  h fe h fc rc

hfb h fe 1  h fc - 0.98 -a
 
1  h fe h fc

hob hoe hoc 0.49 µA/V 1

1  h fe

h fc rc

hic hie * 1100Ω hib re

rb 
1  h fb 1  a 
hrc 1-hre~=1* 1 1 re
1
1  a rc
hfc -(1+hfe)* - 51 
1 1

1  h fb 1  a 
hoc hoc * 25µA/V hob 1
1  h fb 1  a .rC
a h fe 1  h fc -hfb 0.980
1  h fe h fe

rc 1  h fe h fc 1 2.04 M
hoe
.*  .*
hoc hob

re hrc 1  hrc hrb 10Ω

.* .* hiib  (1  h fb ). *
hoc hoc hob

rb hre h fc hrb 590Ω

hie  (1  h fe ). * hic  h (1  hrc ). * .*
hoe oc hob

* Exact

FET AMPLIFIERS
Field effect transistor amplifiers provide an excellent voltage gain with the added advantage of
high input impedance. There are three basic FET circuit configurations : common source,
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 CHAPTER 1 - AMPLIFIERS
common drain , and common gate. These are similar to the bipolar transistor common emitter ,
common collector and common base circuits respectively, the only difference is that BJT controls
a large output (collector) current by means of, relatively small input (base current), whereas, FET
controls an output (drain) current by means of small input (gate) voltage. It is important to note
that in both the cases the output current is the controlled variable.
JFET as an Amplifier
Field-effect transistor amplifier circuits use the voltage-controlled nature of the JFET. In the
pinch-off region, ID depends (approximately) only on VGS.
Let us discuss the use of the JFET as an amplifier by considering the common-source circuit,
shown in the Fig. 73.

The voltage VGG provides the necessary reverse-

bias between gate and source of the JFET. The
signal to be amplified is Vs.
The volt-ampere characteristics of the JFET is as
shown in Fig. 74.
On the output characteristics, a load line
corresponding to VDD = 40 V and RD = 8 kΩ is
constructed.
The transistor is biased at point Q and results in
VDSQ = 20 V and lDSQ =2.70 mA.

Fig. 73 Common source circuit

Assuming that the signal voltage Vs is a sinusoid of peak voltage Vm = 0.5 V, this signal is
superimposed on the quiescent level. The instantaneous gate-to source voltage is
vgs = VS - VGG
The resulting waveforms for iD and VDS are as shown in Fig. 74.
Both quantities, iD and
VDS can be considered
as sinusoids
superimposed on the
dc values.
Fig. 74 volt-ampere
characteristics of the
JFET

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 CHAPTER 1 - AMPLIFIERS
Then VGS = -VGC+Ves
= -1.5+ 0.5 sin ωt
= 2.70 + 0.5 sin ωt mA
Vout = VDS = VDSQ + Vds
= 20 - 4 sin ωt
We observe that the output signal is greater than the input signal, thus indicating amplification.
Note that the quiescent operating point Q is selected to be approximately the midpoint of the load
line. This gives undistorted output, i.e. output waveform is sinusoidal when the input signal is
sinusoidal. If the operating point is selected either close to the ohmic region or near the pinch-off
voltage, i.e. at the one of the ends of the load line, the output sinusoid would be clipped during
either the positive or negative half-cycles of the input signal. In case of common-source circuit of
JFET, there is a phase shift of 180° between the input and output sinusoidal voltages.
Frequency Response
Over the range of frequencies at which it is to be used, an amplifier should ideally provide the
same amplification for all frequencies. The degree to which this is done is usually indicated by a
curve, known as frequency response curve of the amplifier. This curve is a plot of the voltage gain
of an amplifier against the frequency of input signal. A typical frequency response of an R-C
coupled amplifier is illustrated in Fig. 89.
Fig 89 Frequency response and bandwidth of the RC coupled Amplifier
To plot this curve, input voltage to the amplifier is
kept constant and frequency of input signal is
continuously varied.
The output voltage at each frequency of input signal
is noted; and the gain of the amplifier is calculated.
The output voltage or the voltage gain of the
amplifier is then plotted against frequency.
For an A.F. amplifier, the frequency range of interest
is quite large, from 20 Hz to 20 kHz.
Hence to show clearly the voltage gain over such a
wide frequency range, the frequency of input signal is
plotted on x-axis using log scale (instead of usual
linear scale).
However the output voltage or voltage gain of the amplifier is plotted on y-axis with linear scale.
It is seen from the frequency response curve of an audio frequency amplifier that the gain of the
amplifier remains fairly constant in the mid-frequency range, while the gain varies with
frequency in low and high frequency regions of the curve. The frequency-response is nearly ideal
over a wide range of mid-frequency. Only at low and high frequency ends, the gain deviates from
ideal characteristics.
To indicate how constant an amplifier's gain is with frequency variation, we may specify the
range of frequencies over which the gain does not deviate more than 70.7% of the maximum gain
at some reference mid-frequency. This is shown in Fig. 89 where these two frequencies are
indicated by f1 and f2.
Bandwidth of the amplifier is defined as the difference between f2 and f1.
i.e. Bandwidth of the amplifier = f2 - f1
The frequency f2 is in high frequency region, while the frequency f1 lies in low frequency region.
These two frequencies are also referred to as half-power frequencies since gain or output voltage
drops to 70.7% of maximum value and this represents a power level of one-half the power at the

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 CHAPTER 1 - AMPLIFIERS
reference frequency in mid-frequency region. Although this drop to 70.7 % of maximum value
may seem to be large drop, the change is not easily noticeable to the listener, so that an amplifier
may be considered to have a flat response from f1 and f2 .
Effect of Coupling Capacitors :
Recall that the reactance of a capacitor is XC = 1/2fc. At medium and high frequencies, the factor f
makes XC very small, so that all coupling capacitors behave as short circuits. At low frequencies,
XC increases. This increase in XC drops the signal voltage across the capacitor and reduces the
circuit gain.
As signal frequencies decreases, the capacitor reactance increase and circuit gain continues to
fall, reducing the output voltage.
Effect of Bypass Capacitors :
At lower frequencies, the bypass capacitor CE is not a short. So the emitter is not at ac ground. Xc
in parallel with RE (Rs in case of FET) creates an impedance. The signal voltage drops across this
impedance reducing the circuit gain. This is illustrated in Fig.90

(a) BJT (b) JFET

Fig. 90 At low frequencies emitter (source in case of JFET) is not at ac ground
Effect of Internal Transistor Capacitances :
At high frequencies, the coupling and bypass capacitors act as a short circuit and do not affect
the amplifier frequency response. However, at high frequencies, the internal capacitances,
commonly known as junction capacitances do come into play, reducing the circuit gain.
Fig. 91 shows the junction capacitances for both a BJT and a JFET. In case of the BJT, Cbe is the
base emitter junction capacitance and Cbc is the base collector junction capacitance. In case of
JFET, Cgs is the internal capacitance between gate and source and Cgd is the internal capacitance
between gate and drain.
At higher frequencies, the reactances of the junction capacitances are low. As frequency
increases, the reactances of junction capacitances fall. When these reactances become small
enough, they provide shunting effect as they are in parallel with junctions. This reduces the
circuit gain and hence the output voltage.

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(b)JFET Fig. 91 Internal transistor capacitances

Low Frequency Response
Fig. 92 High-pass RC circuit
Let us consider a high-pass RC circuit shown in the Fig. 92 to
calculate the low frequency response of an amplifier.
Looking at Fig. 92 and using complex variable S,
we can write,
Vi ( S ) R1 s
Vo ( S )  
R1  1 s
1
sC1
R1C1
From the above equation, we can say that the voltage
transfer function at low frequencies,
AL(s) = Vo(s)/Vi (s), has one zero at s = 0 and one pole at s = - 1 /R1 C1. For real frequencies, s = jω
= j2πf and the equation becomes
j 1 1
AL ( jf )   
1 1 1
j  1 1
R1C1 R1C1 j jR1C1 2f

1 1 1
  where f l 
j 1  j( f l f ) 2R1C1
1
2R1C1 f
The magnitude | AL | and the phase lead θL of the gain are given by
1 fl
AL   L  tan 1
1  ( fl f ) f
2

At the frequency f = fL, AL = 1/√2 = 0.707, whereas in the mid band region (f >> fL), AL ->1. Hence
fL is that frequency at which the gain has fallen to 0.707 times its mid band value Amjd. This drop
in signal level, corresponds to a decibel reduction of 20 log (1 /√2), or 3dB. Therefore, the fLis
referred to as the lower 3dB frequency.
High Frequency Response
Let us consider a low-pass RC circuit shown in the Fig. 93 to calculate the high frequency
response of an amplifier.
Fig 93

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Looking at Fig. 93 and using complex variable s, we can write,

1
sC2 1
Vo ( S )  Vi ( S )  Vi ( S )
1 1  sR2 C 2
R2 
sC2
From the above equation, we can say that the voltage transfer
function at high frequencies, AH(s) = Vo(s)/Vi(s), has a single
pole of s = - 1/R2 C2. For real frequency] s = jω= j 2πf, equation becomes
1 1
AH ( jf )  
1  jR2 C 2 1  j 2fR 2 C 2

1 1
 where fH 
f 2R2 C 2
1 j
fH
The magnitude AH and the phase lead θH of the gain are given by
1 f
AH   H  tan 1
1 ( f fH ) fH
2

At the frequency f = fH, A= = l/√2 = 0.707, whereas in the mid band region f <<fH, AH -> 1. Hence fH
is that frequency at which the gain has fallen to 0.707 times its mid band value Amid. This drop is
3dB in decibels and therefore, the fH is referred to as the higher 3 dB frequency.
Low Frequency Analysis of BJT
Let us consider a typical common emitter amplifier as shown in Fig. 94.
The amplifier shown in Fig. 94 has three RC networks that affect its gain as the frequency is
reduced below midrange. These are :
1. RC network formed by the input coupling capacitor C, and the input impedance of the
amplifier.
2. RC network formed by the output coupling capacitor C2, the resistance looking in at the
collector, and the load resistance.
3. RC network formed by the emitter bypass capacitor CF and the resistance looking in at the
emitter.

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Fig. 94 Typical RC coupled common emitter amplifier

Input RC Network
Fig. 95 shows input RC network formed by C1 and the input impedance of the amplifier. Note that
Vout shown in the Fig. 95 is the output voltage of the network.

Fig 95
Applying voltage divider theorem we can write
 
 V
Rin
Vout
 R 2  XC 2  in
 in 1 
We know that a critical point in the amplifiers response is
generally accepted to occur when the output voltage is 70.7
percent of the input (Vout = 0.707 Vin ) . Thus we can write, at critical point
Rin 1
 0.707 
Rin2  XC12 2

Therefore at this condition Rin = Xc1.

At this condition the overall gain is reduced due to the attenuation provided by the input
RC network. The reduction in overall gain is given by
V 
AV  20 log out   20 log( 0.707)  3dB
 Vin 
The frequency fc at this condition is called lower critical frequency and is given by
1
fc  where Rin = R1 || R2 || hie
2Rin C1

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1
 fc 
2 R1 R2 hie

Output RC Network
Fig. 96 shows output RC network formed by C2, resistance looking in at the collector and the load
resistance.

Fig. 96 (a) Current source (b) Current source replaced by voltage source
The critical frequency for this RC network is given by,
1
fc 
2 RC  RL C 2
Bypass Network
Fig. 97 (b) shows RC network formed by the emitter bypass capacitor CE and the resistance
looking in at the emitter.
hie  RTH
Where is the resistance looking in at the emitter. It is derived as follows

Ve hie V h I b RTH hie RTH  hie
R   ib  ie => R   
Ie  I b  I b  

(a) (b)
Fig..97 Bypass RC Network
Where RT| = R1 || R2 || Rs. It is the thevenin's equivalent resistance looking from the base of the
transistor towards the input as shown in the Fig. 13 (a).
The critical frequency for the bypass network is

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1 1
fc  
2RC E  h  RTH  
2  ie  || RE C E
   
We have seen that each network has a critical frequency. It is not necessary that all these
frequencies should be equal. The network which has higher critical frequency than other two
network is called dominant network. The dominant network determines the frequency at which
the overall gain of the amplifier begins to drop at-20dB/decade.

High Frequency Analysis of BJT

Let us consider a typical common emitter amplifier as shown in Fig. 105.

Fig. 105 Typical RC coupled common emitter amplifier

As mentioned earlier, at high frequencies, the coupling and bypass capacitors act as a short
circuit and do not affect the amplifier frequency response. However, at higher frequencies the
internal capacitances do come into play. Fig. 106 shows the high frequency equivalent circuit for
the given amplifier circuit.

Fig. 106 High frequency equivalent circuit

Using Miller theorem this high frequency equivalent circuit can be further simplified as follows.
The internal capacitance Cbc can be splitted into Cin (miiler) and Cout (miller) as shown in the Fig. 107.

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Fig. 107 Simplified high frequency equivalent circuit

Where C in (miller) = Cbc ( A v + 1 )
 A  1
And Cout( miller )  Cbc  V 
 AV 
Fig. 107 shows that there are two RC networks which affect the high frequency response of the
amplifier. These are :
1) Input RC Network and
2) Output RC Network

Input RC Network
Fig. 108 shows input RC network.

Fig. 108 Input RC network

This network is further reduced as shown in the Fig. 109. At high frequencies capacitive
reactance becomes smaller. If we apply voltage divider theorem, voltage at point A in Fig. 109
reduces as capacitive reactance reduces with increase in frequency above midrange. This reduces
the signal voltage applied to the base, reducing the circuit gain and hence the output voltage.

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Fig. 109 Reduces input RC network

The critical frequency can be calculated at condition capacitive reactance is equal to the
resistance, i.e. XC1 = Rs || R1 || R2 || hie.
It is given as,
1
f c (input) 
2 RS || R1 || R2 || hie CT
where CT = Cbc + Cin(miller)

Output RC Network
Fig. 110 shows the output RC network

(a) Output network with current source (b) Output network with voltage source
Fig. 110

The critical frequency can be given as

1 1
f c ( output)  
2Ro Cout( miller ) 2 RC || RL Cbc AV  AV  1

We have seen that both the networks have critical frequencies. It is not necessary that these
frequencies should be equal. The network which has lower critical frequency than other network
is called dominant network.

Cascade Connection
For faithful amplification amplifier should have desired voltage gain, current gain and it should
match its input impedance with the source and output impedance with the load. Many times
these primary requirements of the amplifier cannot be achieved with single stage amplifier,
because of the limitation of the transistor/FET parameters. In such situations more than one

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amplifier stages are cascaded such that input and output stages provide impedance matching
requirements with some amplification and remaining middle stages provide most of the
amplification.
In short we can say that,
• When the amplification of a single stage amplifier is not sufficient, or,
• When the input or output impedance is not of the correct magnitude, for a particular
application two or more amplifier stages are connected, in cascade. Such amplifier, with two
or more stages is also known as multistage amplifier.
Fig. 121 shows the block diagram of two stage cascaded amplifier. These stages are connected
such that the output of the first stage is connected to the input of the second stage.

Fig. 121 Block diagram of two stage cascade amplifier

As shown in the Fig. 121 Vi1 is the input of the first stage and Vo2 is the output of the second stage.
Therefore Vo2/Vi1 is the overall voltage gain of two stage amplifier and it can be given as,
Vo 2 Vo 2 Vi 2
AV   .
Vi1 Vi 2 Vi1
We know that, V01 = Vi2
Vo 2 Vo1
 AV  .
Vi 2 Vi1
= AV2 Av1
So that, we can say the voltage gain of multistage amplifier is the product of voltage gains of
the individual stages.
The gain of the amplifier can be further increased by connecting more number of stages in
cascade, as shown in the Fig. 122.

Fig. 122 Multistage amplifier with n number of stages

Voltage Gain :

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We have seen that the resultant voltage gain of the multistage amplifier is the product of voltage
gains of the various stages.
Av = Av1 . Av2 . Av3 …… Avn
The voltage gain of the k th stage is given as
AiK RLK
AVK 
RiK
where RLK is the effective load resistance of the k th stage and RiK is the input impedance of the
kth stage.
Selection of Configuration in Cascading Amplifiers
From design point of view we divide the multistage amplifier in three parts : Input stage, middle
stages and output stage.
Input stage is designed such that its input impedance matches with the source impedance and the
output stage is designed such that its output impedance matches with the load impedance. The
remaining middle stages are designed to provide necessary power (voltage as well as current)
gain.
The transistor works as an amplifier in common collector, common base and common emitter
configuration with the characteristics shown in table 8. These characteristics play very important
role in selection of configurations in the cascading amplifiers.
Let us consider the multistage amplifier with the three amplifier stages. Assume that input signal
is available with very low source impedance, and with a sufficient gain, amplifier has to drive the
low impedance.

Comparison of Transistor Configurations :

Sl.No. -Characteristic Common Base Common Emitter Common Collector

1. Input resistance Very low (20Ω) Low (1k Ω) High (500 k Ω)

2 Output resistance Very high (1M Ω) High (40k Ω) Low (50Ω)

3. Input Current IE IB IB

4. Output Current IC IC IE

5. Input voltage Emitter and Base Base and Emitter Base and Collector
Applied between

6. Output voltage Collector and Base Collector and Emitter Emitter and Collector
taken between

7. Current IC IC IE
amplification factor  
IE IB IB

8. Current gain Less than unity High (20 to few High (20 to few

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hundreds) hundreds)

9. Voltage gain Medium Medium Low

10. Applications As a input stage of For audio signal For impedance

multistage amplifier amplification matching

Table .8
Looking at the Table 18 we can easily select the common base configuration for the input stage
because the input impedance of the common collector configuration matches with a very low
source impedance.
We know that the common emitter configuration provides voltage as well as current gain hence it
is the best choice for the middle stages.
The output stage must be selected such that its output impedance should match with the load
impedance. In our case, output impedance is low and hence looking at table 8 we can select the
common collector configuration for output stage.
Methods of Cascading Multistage Amplifiers
In multistage amplifier, the output signal of preceding stage is to be coupled to the input circuit of
succeeding stage. For this interstage coupling, different types of coupling elements can be
employed. These are :
1) RC coupling 2) Transformer coupling 3) Direct coupling

RC Coupling
Fig. 123 shows RC coupled amplifier using transistors. As shown in the Fig. 123 the output signal
of first-stage is coupled to the input of the next stage through coupling capacitor and resistive
load at the output terminal of first stage.

Fig. 123 Two stage RC coupled amplifier using transistors

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The coupling does not affect the quiescent point of the next stage since the coupling capacitor C c
blocks the dc voltage of the first stage from reaching the base of the second stage. The RC
network is broadband in nature. Therefore, it gives a wideband frequency response without peak
at any frequency and hence used to cover a complete AF amplifier bands. However its frequency
response drops off at very low frequencies due to coupling capacitors and also at high
frequencies due to shunt capacitors such as stray capacitance.

Fig. 124 shows the frequency response of RC coupled amplifier.

Transformer Coupling
Fig. 125 shows transformer coupled amplifier using transistors. As shown in the Fig. 1.125 the
output signal of first stage is coupled to the input of the next stage through an impedance
matching transformer.

Fig. 125 Two stage transformer coupled amplifier using transistors

This type of coupling is used to match the impedance between output and input cascaded stage.
Usually, it is used to match the larger output resistance of AF power amplifier to a low impedance
load like loudspeaker, As we know, transformer blocks dc, providing dc isolation between the-
two stages. Therefore, transformer coupling does not affect the quiescent point of the next stage.
Frequency response of transformer coupled amplifier is poor in comparison with that of an RC
coupled amplifier. Its leakage inductance and interwinding capacitances does not allow amplifier
to amplify the signals of different frequencies equally well, Interwinding capacitance of the
transformer coupled may give rise resonance at certain frequency which makes amplifier to give
very high gain at that frequency. By putting shunting capacitors across each winding of the
transformer, we can get resonance at any desired RF frequency. Such amplifiers are called tuned
voltage amplifiers.

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These provide high gain at the desired of frequency, i.e. they amplify selective frequencies. For
this reason, the transformer-coupled amplifiers are used in radio and TV receivers for amplifying
RF signals.
As dc resistance of the transformer winding is very low, almost all dc voltage applied by V cc is
available at the collector. Due to the absence of collector resistance it also eliminates unnecessary
power loss in the resistor.

Fig. 126 shows the frequency response of transformer coupled amplifier.

Direct Coupling
Fig. 127 shows direct coupled amplifier using, transistors. As shown in the Fig. 127 the output
signal of first stage is directly connected to the input of the next stage. This direct coupling allows
the quiescent dc collector current of first stage to pass through base of the next stage, affecting its
biasing conditions.
Due to absence of RC components, its low frequency response is good but at higher
frequencies shunting capacitors such as stray capacitances reduce the gain of the amplifier.
The transistor parameters such as VBE and β change with temperature causing the collector
current and voltage to change. Because of direct coupling these changes appear at the base of the
next stage and hence in the output. Such unwanted change in the output is called Drift and is a
serious problem in direct coupled amplifiers.

Fig. 127 Two stage directly coupled amplifier using transistors

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Fig. 128 Frequency Response of directly coupled amplifier

Comparison Between Various Cascading Method

Parameter RC Coupled Transformer Coupled Direct Coupled

Coupling Resistor and Capacitor Impedance matching -

Components transformer

Block DC Yes Yes No

Frequency Flat at middle Not uniform, high at Flat at middle

response frequencies resonant frequency and low frequencies and
at other frequencies improvement in the low
frequency response

Impedance Not achieved Achieved Not achieved

matching

DC No No Yes
amplification

Weight Light Bulky and heavy

Drift Not present Not present Present

Hum Not present Present Not present

Application Used in all audio small Used in amplifier where Used in amplification of
signal amplifiers. Used in impedance matching is an slow varying
record players, tape important criteria. Used in parameters and where
recorders, public address the output stage of the pubic DC amplification is
systems, radio receivers address system to match the required.
and television receivers. impedance of loudspeaker.
Used in the RF amplifier
stage of the receiver as a
tuned voltage amplifier.

Table. 9

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Darlington Connection
We have seen that out of three configurations (CB, CC and CE), common collector or emitter
follower circuit has high input impedance. Typically it is 200 kΩ to 300 kΩ. A single stage emitter
follower circuit can give input impedance up to 500 kΩ. In many application we require input
impedance higher than 500 kΩ. In such cases, the input impedance of the circuit can be improved
by direct coupling of two stages of emitter follower amplifier. Fig. 130 shows the direct coupling
of two stages of emitter follower amplifier. This cascaded connection of two emitter follows is
called the Darlington connection. Here, emitter current of first stage is the base current of the
second stage.

Fig. 130 Darlington emitter follower circuit

Darlington connection of two transistor improves current gain and input resistance of the circuit.
One might think that by connection of one more stage there will be further improvement in the
input impedance and current gain. But unfortunately this is not possible because of the
following two reasons :
1. Darlington connection of two transistors, emitter of the first transistor is directly connected
to the base of the second transistor. Because of direct coupling dc output current of the first
stage is (1 + hfe) Ib1. If Darlington connection for n transistor is considered, then due to direct
coupling the dc output current for last stage is (1 + hfe)n times Ib1. Due to very large
amplification factor even two stage Darlington connection has large output current and
output stage may have to be a power stage. As power amplifiers are not used in the amplifier
circuits it is not possible to use more than two transistors in the Darlington connection.

2. In Darlington transistor connection, the leakage current of the first transistor is amplified by
the second transistor and overall leakage current may be high, which is not desired.

Introduction of Power Amplifiers

Consider a public address system (P.A.) or amplifying system as shown in the Fig. 131.
Fig 131. PA system
The system consists of many stages
connected in cascade. Hence
basically it is a multistage amplifier.
The input is sound signal of a human
speaker and the output is given to
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the loud speaker which is an amplified input signal. The input and the intermediate stages are
small signal amplifiers. The sufficient voltage gain is obtained by all the intermediate stages.
Hence these stages are called voltage amplifiers.
But the last stage gives an output to the load like a loud speaker. Hence the last stage must be
capable of delivering an appreciable amount of a.c. power to the load. So it must be capable of
handling large voltage or current swings or in other words large signals. The main aim is to
develop sufficient power hence the voltage gain is not important, in the last stage. Such a stage,
which develop and feed sufficient power to the load like loudspeaker, servomotor, handling the
large signals is called Large Signal Amplifier or Power Amplifier.
Power amplifiers find their applications in the public address systems, radio receivers, driving
servomotor in industrial control systems, tape players, T.V. receivers, cathode ray tubes etc.
Features of a Power Amplifier
As stated earlier, a power amplifier is the last stage of a multistage amplifier. The previous stages
develop sufficient gain and the input signal level or amplitude of a power amplifier is large of the
order of few volts. The h-parameter analysis is applicable to small signal amplifiers and not valid
for power amplifiers as power amplifiers are large signal amplifiers. Hence the analysis of power
amplifier is carried out graphically by drawing a load line on the output characteristics of the
transistors, used in it.
The power amplifiers have to feed the loads like loud speakers, having low impedance values. For
maximum power transfer to the load, the impedance matching is an important criteria in the
power amplifiers. For impedance matching, the output impedance of the power amplifiers must
be small. Hence common collector or emitter follower circuit is very common in power
amplifiers, which has very low output impedance. The common emitter circuit with step down
transformer for impedance matching, is also commonly used in the power amplifiers.
The power amplifiers develop an a.c. power of the order of few watts. Similarly large power gets
dissipated in the form of heat, at the junctions of the transistors used in the power amplifiers.
Hence the transistors used in the power amplifiers are of large size, having large power
dissipation rating, called power transistors. Such transistors have heat sinks. A heat sink is a
metal cap having bigger surface area, press fit on the body of a transistor, to get more surface
area, in order to dissipate the heat to the surroundings. In general, the power amplifiers have
bulky components.
A faithful reproduction of the signal, after the conversion, is important. Due to nonlinear nature
of the transistor characteristics, there exists a harmonic distortion in the signal. Ideally signal
should not be distorted. Hence the analysis of signal distortion in case of the power amplifiers is
important.
The power amplifiers developing power at audio frequency range are called audio frequency
(A.F.) power amplifiers.

Classification of Power Amplifiers

For an amplifier, a quiescent operating point (Q point) is fixed by selecting the proper d.c. biasing
to the transistors used. The quiescent operating point is shown on the load line, which is plotted
on the output characteristics of the transistor. The position of the quiescent point on the load line
decides the class of operation of the power amplifier.

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The various classes of the power amplifiers are :

i) Class A ii) Class B iii) Class C and iv) Class AB
Before defining the position of the quiescent point on the load line, for the various classes, let us
revise in brief the concept of load line.
Consider a common emitter circuit as shown in the Fig. 132.
The transistor is biased with VCC to obtain the required values of IC, IE and VCE.

Fig. 132 Common emitter circuit

Applying Kirchhoff's voltage law to the output circuit i.e. collector circuit, we get
VCC – IC RC - VCE = 0
where
VCC = ICRC+ VCE
RC = Load resistance
 1  VCC
I C   VCE 
 RC  RC
Comparing this equation with an equation of a straight line,
y = mx+c
We can draw a straight line on a graph of IC versus VCE i.e. output characteristics.
1 V
The slope of this straight line is  and its Y-intercept is CC .
RC RC
From the above equation , we can write
i) When VCE = VCC , IC = 0
ii) When VCE = 0, IC = VCC / RC
These two points can be located to draw a straight line on the output characteristics. Such a line
having slope as the reciprocal of the load resistance, drawn on the output characteristics is called
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a load line. Such a load line is shown in the Fig. 133.

The characteristic curves are plotted for various values of IB. The intersection of the output
characteristic curve and a load line is the operating point. This point is fixed for a transistor
called quiescent point or Q point as shown in the Fig. 133.
The values of collector current and the collector to emitter voltage, corresponding to the Q point
are ICQ and vCEQ respectively. Hence the co-ordinates of the Q point are (vCEQ , ICQ). The
corresponding value of the base current is denoted as IBQ.

Fig. 133 Output characteristics with a load line

On this d.c. quiescent operating point, if an a.c. signal is superimposed, by the application of a.c.
sinusoidal voltage at the input, the base current varies sinusoidally about its quiescent value I BQ
as shown in the Fig. 134(a). Since the transistor is biased to operate in the active region, the
output is linearly proportional to the input. The output i.e. the collector current is β times larger
than the input base current in the common emitter configuration. Hence the collector current
also varies sinusoidally about its quiescent value ICQ. The output voltage also varies sinusoidally
about its quiescent value VCEQ. The sinusoidal variations in IC and VCE are shown in the Fig. 134
(b) and (c) respectively.

Fig. 134 Variations in IB, IC and VCE due to the sinusoidal input
These variations in IC and VCE, due to the change in IB, can be shown graphically with the help of a
load line as shown in the Fig. 135.
The collector current varies above and below its quiescent value, in phase with the base current.
The collector-to-emitter voltage varies above and below its quiescent value, 180° out of phase

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with the base current, as shown in the Fig. 135.

Fig. 135 Graphical representation of IB , IC and VCE swings

Now let us define the various classes of the power amplifiers, depending on the position of the Q
point, on a load line.

Class A Amplifiers
The power amplifier is said to be class A amplifier if the Q point and the input signal are selected
such that the output signal is obtained for a full input cycle. For this, position of the Q point is
approximately at the midpoint of the load line.
For all values of input signal, the transistor remains in the active region and never enters into cut-
off or saturation region. When an a.c. input signal is applied, the collector voltage varies
sinusoidally hence the collector current also varies sinusoidally. The collector current flows for
360° (full cycle) of the input signal. In other words, the angle of the collector current flow is 360°
i.e. one full cycle.
The current and voltage waveforms for a class A operation are shown with the help of output
characteristics and the load line, in the Fig. 136.

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Fig. 136 Waveforms representing class A operation

As shown in the Fig. 136, for full input cycle, a full output cycle is obtained. Here signal is
faithfully reproduced, at the output, without any distortion. This is an important feature of a class
A operation. The efficiency of class A operation is very small.

Class B Amplifiers
The power amplifier is said to be class B amplifier if the Q point and the input signal are selected,
such that the output signal is obtained only for one half cycle for a full input cycle. For this
operation, the Q point is shifted on X-axis i.e. transistor is biased to cut-off.
Due to the selection of Q point on the X-axis, the transistor remains, in the active region, only for
positive half cycle of the input signal. Hence this half cycle is reproduced at the output. But in a
negative half cycle of the input signal, the transistor enters into a cut-off region and no signal is
produced at the output. The collector current flows only for 180° (half cycle) of the input signal.
In other words, the angle of the collector current flow is 180° i.e. one half cycle.
The current and voltage waveforms for a class B operation are shown in the Fig. 137.

Fig. 137 Waveforms representing class B operation

As only a half cycle is obtained at the output, for full input cycle, the output signal is distorted in
this mode of operation. To eliminate this distortion, practically two transistors are used in the
alternate half cycles of the input signal. Thus overall a full cycle of output signal is obtained
across the load. Each transistor conducts only for a half cycle of the input signal.
The efficiency of class B operation is much higher than the class A operation.
Class C Amplifiers
The power amplifiers is said to be class C amplifier, if the Q point and the input signal are selected
such that the output signal is obtained for less than a half cycle, for a full input cycle. For this
operation, the Q point is to be shifted below X-axis.
Due to such a selection of the Q point, transistor remains active, for less than a half cycle. Hence
only that much part is reproduced at the output. For remaining cycle of the input cycle, the
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transistor remains cut-off and no signal is produced at the output. The angle of the collector
current flow is less than 180°.
The current and voltage waveforms for a class C amplifier operation -are shown in the Fig. 138.
In class C operation, the transistor is biased well beyond cut-off. As the collector current flows for
less than 180°, the output is much more distorted and hence the class C mode is never used for
A.F. power amplifiers. But the efficiency of this class ot operation is much higher and can reach
very close to 100%.

Fig. 138 Waveform representing class C operation

Though the class C mode is never used for audio frequency power amplifiers, it is preferred in the
special areas like communication in tuned circuits.
Class AB Amplifiers
The power amplifier is said to be class AB amplifier, if the Q point and the input signal are
selected such that the output signal is obtained for more than 180° but less than 360° for a full
input cycle. The Q point position is above X-axis but below the midpoint of a load line. The
current and voltage waveforms for a class AB operation are shown in the Fig. 139.

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Fig. 139 Waveforms representing class AB operation

The output signal is distorted in class AB operation. The efficiency is more than class A but less
than class B operation. The class AB operation is important to eliminate cross over distortion.
In general as the Q point moves away from the centre of the load line below towards the X-axis,
the efficiency of class of operation increases.
Comparison of Amplifier Classes
The comparison of various amplifier classes is summarized in Table 1.10.

Class A B C AB

Operating 360° 180° Less than 180° 180° to 360°

Cycle

Position of Q Centre of On X axis Below X axis Above X-axis but

point load line below the centre of
load line

Efficiency Poor, 25% Better, High Higher than A but less

to 50% 78.5% than B 50% .to 78.5%

Table 10
Analysis of Class A Amplifiers
The class A amplifiers are further classified as directly coupled and transformer coupled
amplifiers. In directly coupled type, the load is directly connected in the collector circuit. While in
the transformer coupled type, the load is coupled to the collector using a transformer called an
output transformer.
Series Fed, Directly Coupled Class A Amplifier

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A simple fixed-bias circuit can be used as a large signal class A amplifier as shown in the Fig. 140.
The difference between small signal version of this circuit is that the signals handled by this large
signal circuit are of the order of few volts. Similarly the transistor used, is a power transistor. The
value of RB is selected in such a way that the Q point lies at the centre of the d.c. load line.

Fig. 140 Large signal class A amplifier

The circuit represents the directly coupled class A amplifier as the load resistance is directly
connected in the collector circuit. Most of the times the load is a loudspeaker, the impedance of
which varies from 3 to 4 ohms to 16 ohms. The beta of the transistor used is less than 100.
The overall circuit handles large power, in the range of a few to tens of watts without providing
much voltage gain.
The graphical representation of a class A amplifier is shown in the Fig. 141.

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Fig. 141 Graphical representation of class A amplifier

Applying Kirchhoff's voltage law to the circuit shown in the Fig. 140, we get
VCC = IC RL + VCE + VCC
IC RL = - VCE + VCC
 1  VCC
I C   VCE 
 RL  RL
1
The equation is similar to other equation of IC and thus the slope of the load line is  and its
RL
VCC
Y-intercept is .
RL
The change is because the collector resistance RC is named as load resistance RL in this circuit.
The Q point is adjusted approximately at the centre of the load line.
D.C. Operation
The collector supply voltage Vcc and resistance RB decides the dc base-bias current IBQ.
V  0.7
I BQ  CC
RB
The corresponding collector current is then,
ICC = β IBQ
From the voltage equation , the corresponding collector to emitter voltage is,
VCEQ = VCC - ICQ RL
Hence the Q point can be defined as Q (VCEQ, ICQ).
D.C. Power Input
The d.c. power input is provided by the supply. With no a.c input signal, the d.c. current drawn is
the collector bias current ICQ . Hence d.c. power input is,
PDC = VCC.ICQ
It is important to note that even if a.c. input signal is applied, the average current drawn from the
d.c. supply remains same. Hence above equation represents d.c. power input to the class A series
fed amplifier.
A.C. Operation
When an input a.c. signal is applied, the base current varies sinusoidally.
Assuming that the nonlinear distortion is absent, the nature of the collector current and collector
to emitter voltage also vary sinusoidally as shown graphically in the Fig. 141.
The output current i.e. collector current varies around its quiescent value while the output
voltage i.e collector to emitter voltage varies around its quiescent value. The varying output
voltage and output current deliver an a.c. power to the load.
A.C. Power Output
For an alternating output voltage and output current swings, shown in the Fig. 141, we can write,

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 CHAPTER 1 - AMPLIFIERS

Vmin = Minimum instantaneous value of the collector (output) voltage

Vmax = Maximum instantaneous value of the collector (output) voltage and
VPP = Peak to peak value of a.c. output voltage across the load.
 VPP = Vmax - Vmin
Now Vm = Amplitude (peak) of a.c. output voltage as shown in the Fig. 141.
VPP Vmax  Vmin
 Vm  
2 2
Similarly we can write for the output current as,
Imin = Minimum instantaneous value of the collector (output) current
Imax = Maximum instantaneous value of the collector (output) current and
VPP = Peak to peak value of a.c. output (load) current
 IPP = Imax - Imin
Now Im = Amplitude (peak) of a.c. output (load) current as shown in the Fig. 141
I PP I max  I min
 Im  
2 2
Hence the r.m.s. values of alternating output voltage and current can be obtained as,
Vm Im
VRMS  I RMS 
2 2
Hence we can write,
Vrms = Irms RL
i.e. Vm = Im RL
The a.c. power delivered by the amplifier to the load can be expressed by using r.m.s values,
maximum i.e. peak values and peak to peak values of output voltage and current.
i) Using r.m.s values :
Pac = Vrms Irms
Or Pac  I RMS
2
RL
2
VRMS
Or Pac 
RL
ii) Using peak values :
Vm Im
Pac = Vrms Irms = 
2 2
Vm .I m
Or Pac 
2

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 CHAPTER 1 - AMPLIFIERS

.I m2 RL .Vm2
Or Pac  
2 2 RL
iii) Using peak to peak values :
VPP I PP
V .I .
V .I
Pac  m m  2 2  PP PP
2 2 8
2 2
.I PP RL .VPP
Pac  or Pac 
8 8 RL
But as VPP = Vmax - Vmin and IPP = Imax - Imin; from above equations, the a.c. power can be expressed
as below, for graphical calculations.
Vmax  Vmin I max  I min 
Pac  '
8
Efficiency
The efficiency of an amplifier represents the amount of a.c. power delivered or transferred to the
load, from the d.c. source i.e. accepting the d.c. power input. The generalized expression for an
efficiency of an amplifier is,
Pac
%   100
Pdc
Now for class A operation, we have derived the expressions for Pac and Pdc, hence using them we
can write
Vmax  Vmin I max  I min 
%   100
8VCC .I CQ

Maximum Efficiency
For maximum efficiency calculations, assume maximum swings of both the output voltage and
output current. The maximum wings are shown in fig 142.
From the Fig. 142, we can see that the minimum voltage possible is zero and maximum voltage
possible is VCC, for a maximum swing. Similarly the minimum current is zero and the maximum
current possible is 2ICQ , for a maximum swing.

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 CHAPTER 1 - AMPLIFIERS

Fig. 142 Maximum voltage and current swings

Vmax = VCC and Vmin = 0
Imax = 2ICQ and Imin = 0
Using Efficiency equation we can write,
VCC  02I CQ  0 2VCC I CQ
% max   100   100 = 25%
8VCC .I CQ 8VCC .I CQ

Thus the maximum efficiency possible in case of directly coupled series fed class A amplifier is
just 25%.
This maximum efficiency is an ideal value. For a practical circuit, it is much less than 25%, of the
order of 10 to 15%. Very low efficiency is the biggest disadvantage of class A amplifier.
Power Dissipation
As stated earlier, power dissipation in large signal amplifier is also large. The amount of power
that must be dissipated by the transistor is the difference between the d.c. power input Pdc and
the a.c. power delivered to the load Pac.
Pd = Power dissipation
i.e. Pd = Pdc - Pac
The maximum power dissipation occurs when there is zero a.c. input signal. When a.c. input is
zero, the a.c. power output is also zero. But transistor operates at quiescent condition, drawing
d.c. input power from the supply equal to VCC ICQ. This entire power gets dissipated in the form of
heat. Thus d.c. power input without a.c. input signal is the maximum power dissipation.
(Pd)max = VCC ICQ
Thus value of maximum power dissipation decides the maximum power dissipation rating of the
transistor to be selected for the amplifier.
Advantages and Disadvantages
The advantages of directly coupled class A amplifier can be stated as,

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 CHAPTER 1 - AMPLIFIERS

1. The circuit is simple to design and to implement

2. The load is connected directly in the collector circuit hence the output transformer is
not necessary. This makes the circuit cheaper.
The disadvantages are :
1. The load resistance is directly connected in collector and carries the quiescent collector
current. This causes considerable wastage of power.
2. Power dissipation is more. Hence power dissipation arrangements like heat sink are
essential.
3. The output impedance is high hence circuit cannot be used for low impedance loads, such as
loudspeakers.
4. The efficiency is very poor, due to large power dissipation.
Analysis of Class B amplifiers
As Stated earlier, for class B operation, the quiescent operating point is located on the X axis
itself. Due to this collector current flows only for a half cycle for a full cycle of the input signal.
Hence the output signal is distorted. To get a full cycle across the load, a pair of transistors is
used in class-B operation. The two transistor alternate half cycles of the input signal and a full
cycle across the load is obtained. The two transistors are identical in characteristics and called
matched transistors.
Depending upon the types of the two transistors whether p-n-p or n-p-n, the two circuit
configurations of class B amplifier are possible. These are,
1. When both the transistors are of same type i.e. either n-p-n or p-n-p the circuit is called push-
pull class B A.F. power amplifier circuit.
2. When the two transistors form a complementary pair i.e. one n-p-n and other p-n-p then the
circuit is called complementary symmetry class B A.F. power amplifier circuit.
Push Pull Class B Amplifier
The push pull circuit requires two transformers, one as input transformer called driver
transformer and l and the other to connect the load called output transformer. The input
signal is applied to the primary of the driver transformer. Both the transformers are
centre tapped
transformers. The
push pull class B
amplifier circuit is
shown in the Fig. 148.
In the circuit, both Q1
and Q2 transistors are
of n-p-n type. The
circuit can use both
Q1and Q2 of p-n-p
type. In such a case,
the only change is that
the supply voltage
must be –VCC, the basic
circuit remains the
same. Generally the

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 CHAPTER 1 - AMPLIFIERS

circuit using n-p-n transistors is used. Both the transistors are in common emitter configuration.
Fig. 148 Push pull class B amplifier
The driver transformer drives the circuit. The input signal is applied to the primary of the driver
transformer. The centre tap on the secondary of the driver transformer is grounded. The centre
tap on the primary of the output transformer is connected to the supply voltage +VCC.
With respect to the centre tap, for a positive half cycle of input signal, the point A shown on the
secondary of the driver transformer will be positive, while the point B will be negative.

Fig. 149 Basic push pull operation

Thus the voltages in the two halves of the driver transformer will be equal but with opposite
polarity. Hence the input signals applied to the base of the transistors Q1 and Q2 will be 1800 out
of phase.
The transistor Q1 conducts for the positive half cycle of the input producing positive half cycle
across the load. While the transistor Q2 conducts for the negative half cycle of the input producing
negative half cycle across the load. Thus across the load, we get a full cycle for a full input cycle.
The basic push pull operation is shown in the Fig. 149.

Fig. 150 Waveforms for push pull class B

amplifier

When point A is positive, the transistor Q1 gets

driven into an active region while the transistor
Q2 is in cut off region. While when point A is
negative, the point B is positive, hence the
transistor Q2 gets driven into an active region
while the transistor Q1 is in cut off region.
The waveforms of the input current, base
currents, collector currents and the load current
are shown in the Fig. 150.
For the output transformer, the number of the
turns of each half of the primary is N1 while

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 CHAPTER 1 - AMPLIFIERS

the number of the turns on the secondary is N2. Hence the total number of primary turns is 2N1.
So turns ratio of the output transformer is specified as 2N1:N2.

D.C.Operation
The d.c. biasing point i.e. Q point is adjusted on the X-axis such that VCEQ = VCC and ICEO is zero.
Hence the co-ordinates of the Q point are (VCC , 0). There is no d.c. base bias voltage.
D.C.Power Input
Each transistor output is in the form of half rectified waveform. Hence if Im is the peak value of
the output current of each transistor, the d.c. or average value is Im /π , due to half rectified
waveform. The two currents, drawn by the two transistors, form the d.c. supply are in the same
direction. Hence the total d.c. or average current drawn from the supply is the algebraic sum of
the individual average current drawn by each transistor.
Im Im 2I m
 I dc   
  
The total d.c. power input is given by,
2
PDC  VDC  I DC  VCC .I m


A.C.Operation
When the a.c. signal is applied to the driver transformer, for positive half cycle Q1 conducts. The
path of the current drawn by the Q1 is shown in the Fig. 151.
For the negative half cycle Q2 conducts. The path of the current drawn by Q2 is shown in the
Fig.151(b).

(a) Q1 Conduction Fig. 1.151 (b) Q2 Conduction

It can be seen that when Q1, conducts, lower half of the primary of the output transformer does
not carry any current. Hence only N1 number of turns carry the current. While when Q2 conducts,
upper half of the primary does not carry any current. Hence again only N1 number of turns carry
the current. Hence the reflected load on the primary can be written as,

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 CHAPTER 1 - AMPLIFIERS

RL N2
RL  where n =
n2 N1
It is important to note that the step down turns ratio is 2N1 : N2 but while calculating the reflected
load, the ratio n becomes N2/N1. So each transistor shares equal load which is the reflected load
R'L given by the above equation.
The slope of the a.c. load line is -1/R'L while the d.c. load line is the vertical line passing through
the operating point Q on the x-axis. The load lines are shown in the Fig. 152.

Fig. 152 Load lines for push pull class B amplifier

The slope of the a.c. load line (magnitude of slope) can be represented in terms of Vm and Im as,
1 I Vm
 m RL 
RL Vm Im
where Vm = Peak value of the collector current

A.C. Power Output

As Im and Vm are the peak values of the output current and the output voltage respectively, then
Vm Im
VRMS  and I RMS 
2 2
Hence the a.c. power output is expressed as,
2
Vrms
Pac  Vrms  I rms  I 2
RL 
RL
rms

While using peak values it can be expressed as,

Vm I m I m2 .RL V2
Pac    m
2 2 2 RL

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 CHAPTER 1 - AMPLIFIERS

Efficiency
The efficiency of the class B amplifier can be calculated using the basic equation
 Vm I m 
 
% 
Pac
 100   2 
 100
PDC 2
VCC I m

 Vm
  100
4 VCC

Maximum Efficiency
From the equation it is clear that as the
peak value of the collector voltage
increases, the efficiency increases. The
maximum value of Vm possible is equal to
VCC as shown in the Fig. 153.
 VCC
% MAX    100  78.5%
4 VCC
Thus the minimum possible theoretical
efficiency in case of push pull class B
amplifier is 78.5% which is much higher
than the transformer coupled class A
amplifier. For practical circuits it is up to 65 to 70%. Fig 153.

Power Dissipation
The power dissipation by both the transistors is the difference between a.c. pow« output and d.c.
power input.
Pd = PDC - Pac
2 Vm I m
 VCC I m 
 2
2 Vm Vm2
 Pd  VCC 
 RL 2 RL
Let us find out the condition for maximum power dissipation. In case of class A amplifier, it is
maximum when no input signal-is there. But in class B operation, when the input signal is zero,
Vm = 0 hence the power dissipation is zero and not the maximum.

Maximum power dissipation : The condition for maximum power dissipation can be obtained
by differentiating the equation of Pd with respect to Vm and equating it to zero.

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 CHAPTER 1 - AMPLIFIERS

dPd 2 VCC 2Vm

  0
dVm  RL 2 RL
2 VCC 2Vm

 RL 2 RL
2
Vm  VCC

This is the condition for maximum power dissipation. Hence the maximum power dissipation
is,
2 VCC 4 V2 4 V2 2 V2
Pd max 
2
VCC   2 CC  2 CC  2 CC
  RL  2 RL  RL  RL
2
2 VCC
Pd max 
 2 RL
Note : For maximum efficiency, Vm = VCC hence the power dissipation is not maximum when the
efficiency is maximum. And when power dissipation is maximum, efficiency is not maximum. So
maximum efficiency and maximum power dissipation do not occur simultaneously, in case
of class B amplifiers.
Vm2
Now Pac 
2 RL
And Vm = VCC is the maximum condition.
2
VCC
Hence Pac max 
2 RL
2
2 VCC 4  VCC
2

Now Pd max  2   
 RL  2  2 RL 


Pd max 
4
Pac max 
2
This much power is dissipated by both the transistors hence the maximum power dissipation per
transistor is (Pd)max/ 2 .
4
Pac max 
Pd max per.transistor   2
Pac max 
2

2 2
This is the maximum power dissipation rating of each transistor. For example 10W maximum
power is to be supplied to the load, then power dissipation rating of each transistor should be —
2/π2 x 10 i.e. 2.02 W.
Advantages and Disadvantages
The advantages of push pull class B operation are :
1. The efficiency is much higher than the class A operation.

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 CHAPTER 1 - AMPLIFIERS
2. When there is no input signal, the power dissipation is zero.
3. The even harmonics get cancelled. This reduces the harmonic distortion.
4. As the d.c. current components flow in opposite direction through the winding, there is no
possibility of d.c. saturation of the core.
5. Ripples present in supply voltage also get eliminated.
6. Due to the transformer, impedance matching is possible.

The disadvantages of the circuit are:

1. Two center tap transformers are necessary.
2. The transformers make the circuit bulky and hence costlier.
3. Frequency response is poor.

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