Computer Architecture Lecture Notes – Input/ Output

Input / Output
Input/Output Problems
• There is a wide variety of peripherals
- Delivering different types of data
- At different speeds
- In different formats
• All input and output devices are slower than CPU and RAM
• The Input/output devices need I/O modules to
- Interface to CPU and Memory
- Interface to one or more peripherals

Generic Model of I/O Module

External Devices
• Human readable
- Screen, printer, keyboard
• Machine readable
- Monitoring and control
• Communication
- Modem
- Network Interface Card (NIC)
External Device Block Diagram
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 Computer Architecture Lecture Notes – Input/ Output

Typical I/O Data Rates

I/O Module Functions

i. Control & Timing
ii. CPU Communication
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 Computer Architecture Lecture Notes – Input/ Output

iii.Device Communication
iv.Data Buffering
v. Error Detection

I/O Steps
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to/from CPU
• Variations for transfer mechanisms
• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

I/O Module Diagram

I/O Module Decisions

• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions e.g. Unix treats everything it can as a file

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 Computer Architecture Lecture Notes – Input/ Output

Input / Output Techniques

• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

Programmed I/O
• CPU has direct control over I/O
- Sensing status (polling)
- Read/write commands
- Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time

Programmed I/O - detail

• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later

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 Computer Architecture Lecture Notes – Input/ Output

I/O Commands
• CPU issues address which identifies module (& device if >1 per module)
• CPU issues command which performs the following:-
- Control - telling module what to do e.g. to spin up disk
- Test - check status e.g. power? Error?
- Read/Write - Module transfers data via buffer from/to device

Addressing I/O Devices

• Under programmed I/O data transfer is very like memory access (CPU viewpoint)
• Each device is given a unique identifier
• CPU commands contain identifier (address)
I/O Mapping
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 Computer Architecture Lecture Notes – Input/ Output

• Memory mapped I/O

- Devices and memory share an address space
- I/O looks just like memory read/write
- No special commands for I/O i.e. Large selection of memory access commands
available
• Isolated I/O
- Separate address spaces
- Need I/O or memory select lines
- Special commands for I/O
Limited set
Larger address space

Interrupt Driven I/O

• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts CPU when ready

Interrupt Driven I/O Basic Operation

• CPU issues read command
• I/O module gets data from peripheral

• CPU does other work

• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data

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 Computer Architecture Lecture Notes – Input/ Output

CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
- Save context (registers)
- Process interrupt i.e. Fetch data & store
- Resume interrupted process
-

Interrupt Steps (H/W and S/W)

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Design Issues
• How do you identify the module issuing the interrupt?
• How do you deal with multiple interrupts i.e. an interrupt handler being interrupted

Identifying Interrupting Module

• Different line for each module
- PC
- Limits number of devices
• Software poll
- CPU asks each module in turn
- Slow
• Daisy Chain or Hardware poll
- Interrupt Acknowledge sent down a chain
- Module responsible places vector on bus
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 Computer Architecture Lecture Notes – Input/ Output

- CPU uses vector to identify handler routine

• Bus Master
- Module must claim the bus before it can raise interrupt e.g. PCI & SCSI

Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
• If bus mastering only current master can interrupt

• Interrupt masking

ISA Bus Interrupt System

• ISA bus chains two 82C59As together
• Link is via interrupt 2
• Gives 15 lines i.e. 16 lines less one for link
• IRQ 9 is used to re-route anything trying to use IRQ 2 also called Backwards
compatibility
• Incorporated in chip set

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 Computer Architecture Lecture Notes – Input/ Output

82C59A Interrupt Controller

Intel 82C55A Programmable Peripheral Interface

Using 82C55A to Control Keyboard/ Display

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Direct Memory Access

• Interrupt driven and programmed I/O require active CPU intervention
- Transfer rate is limited
- CPU is tied up
• DMA is the answer

DMA Function
• Additional Module (hardware) on bus
• DMA controller takes over I/O data transfer from CPU

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 Computer Architecture Lecture Notes – Input/ Output

DMA Module Diagram

DMA Operation
• CPU tells DMA controller:-
- Read/Write
- Device address
- Starting address of memory block for data
- Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

DMA Transfer Cycle Stealing

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• DMA controller takes over bus for a cycle

• Transfer of one word of data

• Not an interrupt CPU does not switch context

• CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU doing transfer or being interrupted for every
data unit

DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
• I/O to DMA then DMA to memory
• CPU is suspended twice

DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once DMA to memory

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• CPU is suspended once

DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once i.e. DMA to memory
• CPU is suspended once

I/O Channels
• I/O devices getting more sophisticated e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed because:-
- It takes load off CPU
- A dedicated processor is faster

I/O Channel Architecture

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 Computer Architecture Lecture Notes – Input/ Output

Interfacing
• Connecting devices to I/O modules
• Tailored to peripheral

• Interface types
- Serial interface
- Parallel interface e.g. FireWire, InfiniBand

IEEE 1394 FireWire

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• High performance serial bus

• Fast
• Low cost
• Expandable
• Easy to implement
• Also being used in digital cameras, VCRs and TV

FireWire Configuration
• Daisy chain where up to 63 devices on single port
• Really 64 of which one is the interface itself
• Up to 1022 buses can be connected with bridges
• Automatic configuration
• No bus terminators
• May be tree structure

Simple FireWire Configuration

FireWire 3 Layer Stack

• Physical
- Transmission medium, electrical and signaling characteristics, bus arbitration
• Link
- Transmission of data in packets

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• Transaction
- Request-response protocol

FireWire Protocol Stack

FireWire - Physical Layer

• Data rates from 25 to 400Mbps
• Bus arbitration
- Based on tree structure
- Root acts as arbiter
- First come first served
- Natural priority controls simultaneous requests i.e. who is nearest to root
- Fair arbitration (Fairness Intervals)
- Urgent arbitration

FireWire - Link Layer

Two transmission types
a. Asynchronous
- Variable amount of data and several bytes of transaction data transferred as a packet
- To explicit address
- Acknowledgement returned
b. Isochronous
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- Variable amount of data in sequence of fixed size packets at regular intervals

- Simplified addressing
- No acknowledgement

FireWire Sub-actions

InfiniBand
• I/O specification aimed at high end servers
- Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel)
• Version 1 released early 2001
• Architecture and spec. for data flow between processor and intelligent I/O devices
• Intended to replace PCI in servers
• Increased capacity, expandability, flexibility

InfiniBand Architecture
• Remote storage, networking and connection between servers
• Attach servers, remote storage, network devices to central fabric of switches and links
• Greater server density
• Scalable data centre
• Independent nodes added as required
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• I/O distance from server up to

- 17m using copper
- 300m multimode fibre optic
- 10km single mode fibre
• Up to 30Gbps

InfiniBand Switch Fabric

InfiniBand Operation
• 16 logical channels (virtual lanes) per physical link
• One lane for management, rest for data
• Data in stream of packets
• Virtual lane dedicated temporarily to end to end transfer
• Switch maps traffic from incoming to outgoing lane

InfiniBand Protocol Stack

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