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Parallel Processing

1. Parallel processing mechanisms utilize multiple functional units, pipelining within the CPU, overlapping CPU and I/O operations, a hierarchical memory system, and balancing subsystem bandwidths. 2. Techniques like multiplicity of functional units, parallelism within the CPU like pipelining, and multiprogramming/time sharing allow different parts of the processing to occur in parallel. 3. The goal is to keep all parts of the system like the CPU, memory, and I/O busy and balanced so that the overall throughput and performance is maximized.

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Sanjay Savi
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86 views

Parallel Processing

1. Parallel processing mechanisms utilize multiple functional units, pipelining within the CPU, overlapping CPU and I/O operations, a hierarchical memory system, and balancing subsystem bandwidths. 2. Techniques like multiplicity of functional units, parallelism within the CPU like pipelining, and multiprogramming/time sharing allow different parts of the processing to occur in parallel. 3. The goal is to keep all parts of the system like the CPU, memory, and I/O busy and balanced so that the overall throughput and performance is maximized.

Uploaded by

Sanjay Savi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Parallel Processing Mechanisms

1. Multiplicity of functional units


2. Parallelism and pipelining within the CPU
3. Overlapped CPU and I/O operations
4. Use of a hierarchical memory system
5. Balancing of subsystem bandwidths
6. Multiprogramming and time sharing

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1. Multiplicity of functional units
n Early computers
q one ALU that perform one operation at a time.
q Slow process
n Multiple and specialized functional units.
q operate in parallel.
n IBM 360/91 →
q two parallel execution units (fixed and floating point
arithmetic)
n CDC-6600 →
q 10 functional units
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System Architecture of CDC-6600

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2. Parallelism and pipelining within CPU
n Parallel Adders
q bit serial adders.
q carry-lookahead and carry save adders.
n Multiplier recoding and convergence division.
n Phases of instruction execution are pipelined
q Instruction fetch, decode, operand fetch, arithmetic
logic execution, store result.
n Instruction Prefetch and data buffering.

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3. Overlapped CPU and I/O operations

n I/O operations performed simultaneously


with CPU computations
q separate I/O controllers, channels or I/O
processors.
n DMA channels – cycle stealing.

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4. Use of a hierarchical memory system

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5. Balancing of subsystem
n
bandwidths
. td  tm  t p
n Bandwidth of a system
q no: of operations performed per unit time.
n Memory bandwidth B  m

q no: of words that can be accessed per unit time.


W
B 
t m
m

n Processor bandwidth B  p
q max: CPU computation rate.
q Ex: Cray-1 → 160 MFLOPS
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n I/O bandwidth B  d

q Average data transfer rate.


q Ex: Modern drives has Bd = 1 megabyte/sec
n Utilization bandwidth of memory Bum 
u B B
u
 B
B m

M
m
and m m

n Utilization bandwidth of CPU


u R
B  w
p
T p

n Utilization bandwidth of I/O B  u


d
q lower than the actual bandwidth.
n Relationship b/w BWs u  u
Bm B m
 B
8
p
 B B
p d
n Bandwidth balancing between CPU and
memory.
§ Cache memory
§ tc  t p
n Bandwidth balancing between memory and I/O
§ Buffer
§ Multiplexing
n Totally balanced system
where u and
u
B B B
p d
u
m
Bp  B p B
u
m
 B m
6. Multiprogramming and time sharing

n Batch processing
q Sequential execution
n Multiprogramming
q Interleaving of CPU and I/O operations
among several programs
n Time sharing
q Assign fixed or variable time slices to
multiple programs

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