A B C D E

1 1

2
Compal confidential 2

JBK00 LA-4091P Schematics Document

Mobile AMD S1G2 CPU with ATI
RS780MN & SB700 core logic
3 3

2008-05-13
REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 1 of 46
A B C D E
 A B C D E

Compal Consumer AMD UMA 17"

confidential
72QFN
1
Thermal Sensor AMD S1G2 CPU DDR2 800MHz 1.8V DDR2-SO-DIMM X2 1

BANK 0, 1, 2, 3 P8, 9 Clock Generator

ADM1032ARMZ SLG8SP626
638-PIN uFCPGA 638
P6 P15
Dual Channel
P4, 5, 6, 7

Fan conn P4
Htper Transport Link 2.6GHz
16X16

ATI RS780MN Finger Print

P31
LVDS Panel
Interface P17 USB Camera
2
P10, 11, 12,13,14 with Digital MIC P17
2

CRT
P16 USB2.0 X12
A-Link Express II USB conn x3
P31
4X PCI-E
HDMI
P18
BT Conn
P31
PCI-E BUS*5 Azalia

ATI SB700 SATA Master-1

SATA Master-2 Dock
P35
SATA Slave
Realtek Mini-Card*2 Express Card
SATA Slave
8102EL(10/100M) WLAN & TV Tunner
P26 P19,20,21,22,23

P25 P26

3
RJ45 Conn. LPC BUS Audio CKT AMP & Audio Jack 3
LED P25 Codec_IDT9271 P29 TPA6020A2 P30
P34

MDC V1.5
RTC CKT. JMB385 SPI ROM
SPI ENE P34

P19
25LF080A
P37
KB926 P33
P27
SATA HDD Connector
P24
Power On/Off CKT. Touch Pad CONN. Int.KBD
P34 CardReader P33
P27 P34
CIR SATA ODD Connector
P24
P34
DC/DC Interface CKT.
P43
SATA 2nd HDD Connector
P24
DC/DC Interface CKT.
4
ACCELEROMETER. P43 e-SATA Connector 4

LIS302DLTR P28
P31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 2 of 46
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 A B C D E

O MEANS ON X MEANS OFF

Voltage Rails

Symbol Note :
+5VS
1
+3VS : means Digital Ground 1

power
plane +2.5VS
+1.8VS
+1.5VS : means Analog Ground
+1.1VS
+B +5VALW +1.8V @ : means just reserve , no build
+VGA_CORE
+3VL +3VALW +0.9V
+1.2V_HT
DEBUG@ : means just reserve for debug.
+5VL +1.2VALW
State +CPU_CORE_NB
+3V_LAN Layout Notes
+CPU_CORE_0 L
+CPU_CORE_1 UMA@ : means for RS780M.

S0
O O O O
S1
2
O O O O 2

S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X

I2C / SMBUS ADDRESSING

SMBUS Control Table
DEVICE HEX ADDRESS SERIAL
THERMAL
SENSOR
SOURCE INVERTER BATT EEPROM CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
3
DDR SO-DIMM 0 A0 10100000 ADM1032 I / II Slot 2 3

DDR SO-DIMM 1 A4 10100100 SMB_EC_CK1

CLOCK GENERATOR (EXT.) D2 11010010 SMB_EC_DA1
KB926 X V V X X X X X X X
ACCELEROMETER 3A 00111010 SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X X X
I2C_CLK
I2C_DATA
RS780M
X X X X X X X V X X
EC SM Bus1 address EC SM Bus2 address DDC_CLK0

Device HEX Address Device HEX Address

DDC_DATA0
RS780M X X X X X X X X V X
DDC_CLK1
Smart Battery 16H 0001 011X b
ADI1032-2 CPU 9AH 1001 101X b
DDC_DATA1
RS780M X X X X X X X X X X
24C16 A0H 1010 000X b SCL0
CPU SIC interface 98H 1001 100X b SDA0
SB700 X X X X V V X X X V
SCL1
SDA1
SB700 X X X X X X V X X X
SCL2
4
SDA2
SB700 X X X X X X X X X X 4

SCL3
SDA3
SB700 X X X X X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 3 of 46
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 A B C D E

1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10

Near CPU Socket

+1.2V_HT
JP1A

2 2
VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 +VLDT_B 1 2
D2 AE3 C7 4.7U_0805_10V4Z
VLDT_A1 VLDT_B1
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15
H_CADIN15
N5
P5
L0_CADIN_L14
L0_CADIN_H15
L0_CADOUT_L14
L0_CADOUT_H15 T4
T3
H_CADOP15
H_CADON15
PWM Fan Control circuit +5VS
L0_CADIN_L15 L0_CADOUT_L15

10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10

10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
J5 Y4 JP2
10 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 10

1
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10 1 1 1 1
C8 C9 2
D1 @ 0.1U_0402_16V4Z 2
10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10
P1 R3 CH751H-40PT_SOD323-2 4.7U_0805_10V4Z 3
10 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 10 2 2 GND
10 H_CTLIP1 P3 T5 H_CTLOP1 10 4

2
L0_CTLIN_H1 L0_CTLOUT_H1 GND
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10
ACES_88231-02001
+VCC_FAN @
@ 6090022100G_B

1
2
5
6

1
D Q1 @ D2
G
3 RLZ5.1B_LL34
33 FAN_PWM S SI3456BDV-T1-E3_TSOP6

2
4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 HT I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 4 of 46
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 A B C D E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH JP1C
9 DDR_B_D[63..0]
MEM:DATA
DDR_A_D[63..0] 8
DDR_A_CLK0 DDR_B_D0 C11 G12 DDR_A_D0
1 +1.8V DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDR_B_D2 A14 H14 DDR_A_D2
C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
B14 MB_DATA3 MA_DATA3 G14
2

1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4

R1 DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDR_B_D6 D12 C13 DDR_A_D6
DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
A13 MB_DATA7 MA_DATA7 E13
1 DDR_B_D8 A15 H15 DDR_A_D8
1

+MCH_REF DDR_B_D9 MB_DATA8 MA_DATA8 DDR_A_D9

A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z

C11 DDR_B_D10 A19 E17 DDR_A_D10

MB_DATA10 MA_DATA10
2

1 1 1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11

2 MB_DATA11 MA_DATA11
C12

C13

R2 DDR_A_CLK#1 DDR_B_D12 C14 E14 DDR_A_D12

1K_0402_1% DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13
D14 MB_DATA13 MA_DATA13 F14
DDR_B_D14 C18 C17 DDR_A_D14
2 2 DDR_B_CLK0 DDR_B_D15 MB_DATA14 MA_DATA14 DDR_A_D15
D18 G17
1

DDR_B_D16 MB_DATA15 MA_DATA15 DDR_A_D16

1 D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17
C14 DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18
D24 MB_DATA18 MA_DATA18 D22
1.5P_0402_50V9C DDR_B_D19 C25 E20 DDR_A_D19
DDR_B_CLK#0 2 DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20
B20 MB_DATA20 MA_DATA20 E18
DDR_B_D21 C20 F18 DDR_A_D21
DDR_B_CLK1 DDR_B_D22 MB_DATA21 MA_DATA21 DDR_A_D22
B24 MB_DATA22 MA_DATA22 B22
1 DDR_B_D23 C24 C23 DDR_A_D23
DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
E23 MB_DATA24 MA_DATA24 F20
C15 DDR_B_D25 E24 F22 DDR_A_D25
1.5P_0402_50V9C DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
G25 MB_DATA26 MA_DATA26 H24
DDR_B_CLK#1 2 DDR_B_D27 DDR_A_D27
G26 MB_DATA27 MA_DATA27 J19
DDR_B_D28 C26 E21 DDR_A_D28
DDR_B_D29 MB_DATA28 MA_DATA28 DDR_A_D29
D26 MB_DATA29 MA_DATA29 E22
DDR_B_D30 G23 H20 DDR_A_D30
+0.9V +0.9V DDR_B_D31 MB_DATA30 MA_DATA30 DDR_A_D31
G24 MB_DATA31 MA_DATA31 H22
JP1B DDR_B_D32 AA24 Y24 DDR_A_D32
2 DDR_B_D33 MB_DATA32 MA_DATA32 DDR_A_D33 2
AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDR_B_D34 AD24 AB22 DDR_A_D34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D35 MB_DATA34 MA_DATA34 DDR_A_D35
Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDR_B_D36 AA26 W22 DDR_A_D36
VTT3 VTT7 DDR_B_D37 MB_DATA36 MA_DATA36 DDR_A_D37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R4 39.2_0402_1% A10 DDR_B_D38 AD26 Y22 DDR_A_D38
VTT9 DDR_B_D39 MB_DATA38 MA_DATA38 DDR_A_D39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
+1.8V 1 2 AE10 Y10 VTT_SENSE DDR_B_D40 AC22 Y20 DDR_A_D40
MEMZN VTT_SENSE PAD T1 MB_DATA40 MA_DATA40
R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41
+MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42
T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44
8 DDR_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T3 AF24 MB_DATA44 MA_DATA44 AB21
DDR_A_ODT1 V22 DDR_B_D45 AF23 AD21 DDR_A_D45
8 DDR_A_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDR_B_ODT0 DDR_B_D46 AC20 AD19 DDR_A_D46
MA1_ODT0 MB0_ODT0 DDR_B_ODT0 9 MB_DATA46 MA_DATA46
V19 W23 DDR_B_ODT1 DDR_B_D47 AD20 Y18 DDR_A_D47
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 9 MB_DATA47 MA_DATA47
Y26 DDR_B_D48 AD18 AD17 DDR_A_D48
DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49
8 DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50
8 DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# 9 MB_DATA50 MA_DATA50
U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# 9 MB_DATA51 MA_DATA51
V20 U22 DDR_B_D52 AF19 Y17 DDR_A_D52
MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53
AC18 MB_DATA53 MA_DATA53 AB17
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D54 AF16 AB15 DDR_A_D54
8 DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB 9 MB_DATA54 MA_DATA54
DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
8 DDR_CKE1_DIMMA MA_CKE1 MB_CKE1 DDR_CKE1_DIMMB 9 MB_DATA55 MA_DATA55
DDR_B_D56 AF13 AB13 DDR_A_D56
DDR_B_D57 MB_DATA56 MA_DATA56 DDR_A_D57
N19 MA_CLK_H0 MB_CLK_H0 P22 AC12 MB_DATA57 MA_DATA57 AD13
N20 R22 DDR_B_D58 AB11 Y12 DDR_A_D58
DDR_A_CLK0 MA_CLK_L0 MB_CLK_L0 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59
8 DDR_A_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDR_B_CLK0 9 Y11 MB_DATA59 MA_DATA59 W11
DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 DDR_B_D60 AE14 AB14 DDR_A_D60
8 DDR_A_CLK#0 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK#0 9 MB_DATA60 MA_DATA60
DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 DDR_B_D61 AF14 AA14 DDR_A_D61
8 DDR_A_CLK1 MA_CLK_H2 MB_CLK_H2 DDR_B_CLK1 9 MB_DATA61 MA_DATA61
DDR_A_CLK#1 AA16 AF17 DDR_B_CLK#1 DDR_B_D62 AF11 AB12 DDR_A_D62
8 DDR_A_CLK#1 MA_CLK_L2 MB_CLK_L2 DDR_B_CLK#1 9 MB_DATA62 MA_DATA62
P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63
MA_CLK_H3 MB_CLK_H3 MB_DATA63 MA_DATA63
P20 MA_CLK_L3 MB_CLK_L3 R25 9 DDR_B_DM[7..0] DDR_A_DM[7..0] 8
3 DDR_B_DM0 DDR_A_DM0 3
8 DDR_A_MA[15..0] DDR_B_MA[15..0] 9 A12 MB_DM0 MA_DM0 E12
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM3 E25 F24 DDR_A_DM3
DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4
M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM5 AE22 Y19 DDR_A_DM5
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7
L21 MA_ADD7 MB_ADD7 L24
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS0 C12 G13 DDR_A_DQS0
MA_ADD8 MB_ADD8 9 DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 8
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD9 MB_ADD9 9 DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 8
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD10 MB_ADD10 9 DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 8
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
MA_ADD11 MB_ADD11 9 DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 8
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS2 A24 C22 DDR_A_DQS2
MA_ADD12 MB_ADD12 9 DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 8
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
MA_ADD13 MB_ADD13 9 DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 8
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS3 F26 G22 DDR_A_DQS3
MA_ADD14 MB_ADD14 9 DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 8
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
MA_ADD15 MB_ADD15 9 DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 8
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
9 DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 8
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
8 DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 9 9 DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 8
DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
8 DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 9 9 DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 8
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
8 DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 9 9 DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 8
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
9 DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 8
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
8 DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# 9 9 DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 8
DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
8 DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# 9 9 DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 8
DDR_A_WE# T24 U23 DDR_B_WE# DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
8 DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# 9 9 DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 8

@ @ 6090022100G_B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 DDRII I/F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 5 of 46
A B C D E
 A B C D E

+2.5VDDA
VDDA=300mA
L1
+2.5VS 1 2 3300P_0402_50V7K
1 FBM_L11_201209_300L_0805
1 1 1 +1.8V 1 2
C16 + R10 10K_0402_5%
@ 100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 1 2
0.22U_0603_16V4Z R5 300_0402_5%
2 2 2 2

2
B
1 R6 2 ENTRIP2 39
Q3 @ 0_0402_5%
JP1D

E
1 CPU_THERMTRIP#_R R7 1
SI2: remove 100uF 3 1 1 2 H_THERMTRIP# 20,33

C
0_0402_5%
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 VDDA2 KEY2 W18

1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC

15 CLK_CPU_BCLK CLKIN_H SVC CPU_SVC 43
C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD
CLKIN_L SVD CPU_SVD 43

1
LDT_RST# B7
R8 H_PWRGD RESET_L
A7 PWROK +1.8V 1 2
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R R9 300_0402_5%
CPU_LDT_REQ# LDTSTOP_L THERMTRIP_L CPU_PROCHOT#_1.8 R11
C6 AC7

2
LDTREQ_L PROCHOT_L CPU_PROCHOT#_1.8
15 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 +1.8V 1 2 H_PROCHOT# 19
C21 3900P_0402_50V7K CPU_SIC AF4 R42 300_0402_5% @ 0_0402_5%
CPU_SID SIC
Address:100_1100 AF5 SID
+1.8VS AE6 W7 THERMDC_CPU PV:change PROCHOT# & delete Q2
ALERT_L THERMDC THERMDA_CPU
Place close to CPU wihtin 1.5" THERMDA W8
R13 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
2

R14 1 2 44.2_0402_1% CPU_HTREF1 P6

R15
+1.2V_HT HT_REF1 +1.8V sense no support
300_0402_5% 43 CPU_VDD0_FB_H CPU_VDD0_FB_H F6 W9 +CPU_CORE_NB
VDD0_FB_H VDDIO_FB_H PAD T22
43 CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
+CPU_CORE_0 VDD0_FB_L VDDIO_FB_L PAD T21
R484 10_0402_5%
1

LDT_RST# R487 10_0402_5% 43 CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 VDD_NB_FB_H VDD_NB_FB_H 1 2

19 LDT_RST# VDD1_FB_H VDDNB_FB_H VDD_NB_FB_H 43
1 2CPU_VDD0_FB_H 43 CPU_VDD1_FB_L CPU_VDD1_FB_L AB6
VDD1_FB_L VDDNB_FB_L G6 VDD_NB_FB_L
VDD_NB_FB_L 43
VDD_NB_FB_L 1 2
1 1 2CPU_VDD0_FB_L R485 10_0402_5%
C22 R486 10_0402_5% CPU_DBRDY G10
0.01U_0402_25V4Z CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10 Close to CPU
@ CPU_TCK AC9
2 CPU_TRST# TCK CPU_TDO
AD9 TRST_L TDO AE9
Close to CPU CPU_TDI AF9 TDI
2 CPU_TEST23_TSTUPD CPU_TEST28_H_PLLCHRZ_P 2
AD7 TEST23 TEST28_H J7 PAD T5 route as differential
+CPU_CORE_1 H8 CPU_TEST28_L_PLLCHRZ_N as short as possible
+1.8VS TEST28_L PAD T6
R489 10_0402_5% CPU_TEST19_PLLTEST0 H10 testpoint under package
TEST18
1 2CPU_VDD1_FB_H CPU_TEST18_PLLTEST1 G9 TEST19 TEST17 D7 CPU_TEST17_BP3
PAD T7
1 2CPU_VDD1_FB_L @ 30.1_0402_1%
TEST16 E7 CPU_TEST16_BP2
PAD T8
2

R493 1 2CPU_TEST25_H_BYPASSCLK_H E9 F7 CPU_TEST15_BP1 +1.8V

TEST25_H TEST15 PAD T10
R21 R488 10_0402_5% 1 2CPU_TEST25_L_BYPASSCLK_L E8 C7 CPU_TEST14_BP0 0718 AMD --> 1K ohm
TEST25_L TEST14 PAD T12
300_0402_5% +1.8VR492
@ 30.1_0402_1% CPU_TEST21_SCANEN AB8 C3 CPU_SVC 1 2
CPU_TEST20_SCANCLK2 TEST21 TEST7 CPU_SVD R22 1K_0402_5%
MV:follow ANT 0E CRB AF7 K8 1 2
1

H_PWRGD TEST20 TEST10

19,43 H_PWRGD change R493 to GND CPU_TEST24_SCANCLK1 AE7 TEST24
R23 1K_0402_5%
CPU_TEST22_SCANSHIFTEN AE8 C4
& R492 to +1.8V CPU_TEST12_SCANSHIFTENB TEST22 TEST8 CPU_TEST27_SINGLECHAIN
1 AC8 TEST12 1 2
CPU_TEST27_SINGLECHAIN AF8 R24 @ 300_0402_5%
C23 TEST27 CPU_TEST29_H_FBCLKOUT_P
TEST29_H C9 PAD T13
@ 0.1U_0402_16V4Z +1.8VS 1 R25 2 0_0402_5% C2 C8 CPU_TEST29_L_FBCLKOUT_N CPU_TEST21_SCANEN R26 1 2 300_0402_5%
2 TEST9 TEST29_L PAD T14
AA6 CPU_TEST20_SCANCLK2 R27 2 1@ 300_0402_5%
TEST6 CPU_TEST24_SCANCLK1 R28 2 1 300_0402_5%
2

A3 H18 CPU_TEST22_SCANSHIFTEN R29 2 1@ 300_0402_5%

R30 RSVD1 RSVD10 CPU_TEST12_SCANSHIFTENB R31 2
A5 RSVD2 RSVD9 H19 MV:unmount strap pin 1@ 300_0402_5%
300_0402_5% B3 AA7 CPU_TEST15_BP1 R32 2 1@ 300_0402_5%
+1.8VS RSVD3 RSVD8 CPU_TEST14_BP0 R33 2
B5 RSVD4 RSVD7 D5 1@ 300_0402_5%
C1 C5 CPU_TEST19_PLLTEST0 R34 2 1@ 300_0402_5%
1

CPU_LDT_REQ# RSVD5 RSVD6 CPU_TEST18_PLLTEST1 R35 2

CPU_LDT_REQ# 11,19 1@ 300_0402_5%
2

CPU_TEST23_TSTUPD R49 2 1@ 300_0402_5%

R36 1 @ 6090022100G_B
300_0402_5% C24 PV:AMD 4.1 recommend
0.01U_0402_25V4Z
@
1

LDT_STOP# 2
11,19 LDT_STOP#
1
3 C25 3
0.01U_0402_25V4Z
@
2
1 2

C939 @ 0.1U_0402_16V4Z
R175
R814
+3VS 2 1 2 1
2.09V for Gate
@ 20K_0402_5% @ 34.8K_0402_1%~N
+1.8V
R18 SI2: Add 300 ohm
+1.8V 2 1
2
G

@ 220_0402_5% R37

@ 220_0402_5% R38

@ 220_0402_5% R39

@ 220_0402_5% R40

300_0402_5% R41
2.2K_0402_5%
HDT Connector

1
CPU_SID 3 1 SMB_EC_DA1 32,33,34,37
S

PV:change to 2.2K Q127 @ FDV301N_NL_SOT23-3 FDV301N, the Vgs is: JP3

min = 0.65V 1 2
R19

2
Typ = 0.85V 3 4
EC is PU to 5VALW 5 6
+1.8V 2 1 Max = 1.5V CPU_DBREQ#
7 8
2

+3VS
G

2.2K_0402_5% CPU_DBRDY
CPU_TCK 9 10
CPU_SIC CPU_TMS
11 12 +3VS
3 1 SMB_EC_CK1 32,33,34,37 13 14
S

CPU_TDI
15 16
0.1U_0402_16V4Z

1 CPU_TRST#
17 18

5
Q129 @ FDV301N_NL_SOT23-3 CPU_TDO U1
C26 19 20 LDT_RST#
2

P
21 22 HDT_RST# B
23 24 4 Y
2
26 A 1 SB_PWRGD 20,33,43 4

G
4 U2 NOTE: HDT TERMINATION IS REQUIRED
1 8 SMB_EC_CK2 @ NC7SZ08P5X_NL_SC70-5
SMB_EC_CK2 33 FOR REV. Ax SILICON ONLY.

3
VDD SCLK @ SAMTEC_ASP-68200-07
THERMDA_CPU 2 7 SMB_EC_DA2
D+ SDATA SMB_EC_DA2 33
C27
1 2 THERMDC_CPU 3 6
2200P_0402_50V7K D- ALERT#
2200p change to 4 5
1000p for ADT7421
THERM# GND Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
ADM1032ARMZ-2REEL_MSOP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 CTRL
Address:100_1101 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 6 of 46
A B C D E
 A B C D E

JP1F

VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JP1E +CPU_CORE_1

AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C30 + C28 + C31 + C29 K12 T8 AC11 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 U9 AC21 L10
Near CPU Socket L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15 U11 AD6
VSS17
VSS18
VSS82
VSS83 L12
L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE_0 M10 V10 AE15 M9
+CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
C32 C33 C34 C35 1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C36 C37 C38 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9
+CPU_CORE_0 H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C40 C41 C42 C43 C44 C45 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D13
VSS43
VSS44
VSS108
VSS109 T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
6090022100G_B D21 U8
Athlon 64 S1 VSS48 VSS113
D23 U10
VDDIO decoupling. Processor Socket
@
D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 U16

+1.8V
+CPU_CORE_NB decoupling. F11
F13
VSS52
VSS53
VSS54
VSS117
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C46 C47 C48 C49 C50 C51 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C52 C53 C54 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M @ 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
SI2: reserve 22u
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket
@

Between CPU Socket and DIMM

+1.8V +0.9V
3 3
Near Power Supply
1
C55
1
C56
1
C57
1
C58
VTT decoupling. 1
C: Change to NBO CAP
+ C59
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_Y_4VM
2 2 2 2 2

180PF Qt'y follow the distance between

+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

1 1 1 1 1 1
C60 C61 C62 C63 C64 C65 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C66 C67 C68 C69 C70 C71 C72 C73
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 2 2 2 2 2 2 2 2
to follow AMD Layout
+1.8V
review recommand for
EMI Near CPU Socket Right side.
+0.9V
1
1 1 1 1 C: Change to NBO CAP
+ C78
C74 C75 C76 C77 220U_Y_4VM 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C79 C80 C81 C82 C83 C84 C85 C86
2 2 2 2 2 @ 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G2 PWR & GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 7 of 46
A B C D E
 A B C D E

+V_DDR_MCH_REF

+1.8V JP4 +1.8V

1 VREF VSS 2
3 4 DDR_A_D4 DDR_A_D[0..63]
DDR_A_D0 VSS DQ4 DDR_A_D5 DDR_A_D[0..63] 5 +0.9V +1.8V
5 DQ0 DQ5 6
DDR_A_D1 7 8 DDR_A_DM[0..7] RP1
DQ1 VSS DDR_A_DM[0..7] 5
9 10 DDR_A_DM0 DDR_A_MA6 1 8 1 2
DDR_A_DQS#0 VSS DM0 DDR_A_DQS[0..7] DDR_A_MA7 C87 0.1U_0402_16V4Z
11 DQS0# VSS 12 DDR_A_DQS[0..7] 5 2 7
DDR_A_DQS0 13 14 DDR_A_D6 DDR_A_MA11 3 6 1 2
DQS0 DQ6 DDR_A_D7 DDR_A_MA[0..15] DDR_A_MA14 C88 0.1U_0402_16V4Z
15 VSS DQ7 16 DDR_A_MA[0..15] 5 4 5
1 DDR_A_D2 1
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12 DDR_A_DQS#[0..7] 47_0804_8P4R_5%
DQ3 DQ12 DDR_A_D13 DDR_A_DQS#[0..7] 5 RP2
21 VSS DQ13 22
DDR_A_D8 23 24 DDR_CKE0_DIMMA 8 1 1 2
DDR_A_D9 DQ8 VSS DDR_A_DM1 DDR_A_BS#2 C90 0.1U_0402_16V4Z
25 DQ9 DM1 26 7 2
27 28 DDR_A_MA15 6 3 1 2
DDR_A_DQS#1 VSS VSS DDR_CKE1_DIMMA C89 0.1U_0402_16V4Z
29 DQS1# CK0 30 DDR_A_CLK0 5 5 4
DDR_A_DQS1 31 32
DQS1 CK0# DDR_A_CLK#0 5
33 34 47_0804_8P4R_5%
DDR_A_D10 VSS VSS DDR_A_D14 RP3
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15 +1.8V DDR_A_MA0 1 8 1 2
DQ11 DQ15 DDR_A_BS#1 C91 0.1U_0402_16V4Z
39 VSS VSS 40 2 7
DDR_A_MA2 3 6 1 2

2
DDR_A_MA4 4 5 C92 0.1U_0402_16V4Z
41 42 R43
DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% 47_0804_8P4R_5%
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21 RP4
DQ17 DQ21 DDR_A_MA5
47 48 8 1 1 2

1
DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF DDR_A_MA8 C93 0.1U_0402_16V4Z
49 DQS2# NC 50 +V_DDR_MCH_REF 9 7 2

0.1U_0402_16V4Z
DDR_A_DQS2 51 52 DDR_A_DM2 DDR_A_MA9 6 3 1 2
DQS2 DM2

1000P_0402_25V8J
53 54 1 1 DDR_A_MA12 5 4 C94 0.1U_0402_16V4Z
VSS VSS

2
C96
DDR_A_D18 55 56 DDR_A_D22
DQ18 DQ22

C95
DDR_A_D19 57 58 DDR_A_D23 R44 47_0804_8P4R_5%
DQ19 DQ23 1K_0402_1% RP5
59 VSS VSS 60
DDR_A_D24 DDR_A_D28 2 2 DDR_A_BS#0
61 DQ24 DQ28 62 8 1 1 2
DDR_A_D25 63 64 DDR_A_D29 DDR_A_MA1 7 2 C98 0.1U_0402_16V4Z

1
DQ25 DQ29 DDR_A_MA10
65 VSS VSS 66 6 3 1 2
DDR_A_DM3 67 68 DDR_A_DQS#3 DDR_A_MA3 5 4 C97 0.1U_0402_16V4Z
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 72 47_0804_8P4R_5%
DDR_A_D26 VSS VSS DDR_A_D30 RP6
73 DQ26 DQ30 74
DDR_A_D27 75 76 DDR_A_D31 DDR_CS1_DIMMA# 8 1 1 2
2 DQ27 DQ31 DDR_A_ODT1 C100 0.1U_0402_16V4Z 2
77 VSS VSS 78 7 2
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA DDR_A_WE# 6 3 1 2
5 DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA 5
81 82 DDR_A_CAS# 5 4 C99 0.1U_0402_16V4Z
VDD VDD DDR_A_MA15
83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14 47_0804_8P4R_5%
5 DDR_A_BS#2 BA2 NC/A14
87 88 RP7
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_ODT0
89 A12 A11 90 1 8 1 2
DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_MA13 2 7 C102 0.1U_0402_16V4Z
DDR_A_MA8 A9 A7 DDR_A_MA6 DDR_A_RAS#
93 A8 A6 94 3 6 1 2
95 96 DDR_CS0_DIMMA# 4 5 C101 0.1U_0402_16V4Z
DDR_A_MA5 VDD VDD DDR_A_MA4
97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2 47_0804_8P4R_5%
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 5
DDR_A_BS#0 107 108 DDR_A_RAS#
5 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 5
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 5
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
5 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 5
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
5 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
DDR_A_ODT1 119 120
5 DDR_A_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D44
139 VSS DQ44 140
3 DDR_A_D40 DDR_A_D45 3
141 DQ40 DQ45 142
DDR_A_D41 143 144
DQ41 VSS DDR_A_DQS#5
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_A_CLK1 5
165 VSS CK1# 166 DDR_A_CLK#1 5
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
VSS DQ63
9,15,20,28 SMB_CK_DAT0 195 SDA VSS 196
9,15,20,28 SMB_CK_CLK0 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200
1
4 C103 P-TWO_A5692B-A0G16-P 4
0.1U_0402_16V4Z @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 8 of 46
A B C D E
 A B C D E

+1.8V
JP5 +1.8V +0.9V +1.8V
1 2 DDR_B_D[0..63] RP8
8 +V_DDR_MCH_REF VREF VSS DDR_B_D[0..63] 5
3 4 DDR_B_D4 DDR_B_BS#1 1 8 2 1
DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_DM[0..7] DDR_B_MA2 C105 0.1U_0402_16V4Z
5 DQ0 DQ5 6 DDR_B_DM[0..7] 5 2 7
DDR_B_D1 7 8 DDR_B_MA0 3 6 1 2
DQ1 VSS

1000P_0402_25V8J
1 9 10 DDR_B_DM0 DDR_B_DQS[0..7] DDR_B_MA6 4 5 C106 0.1U_0402_16V4Z
DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] 5
11 DQS0# VSS 12

C104
DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15] 47_0804_8P4R_5%
1 DQS0 DQ6 DDR_B_MA[0..15] 5 1
15 16 DDR_B_D7
2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] RP9
17 DQ2 VSS 18 DDR_B_DQS#[0..7] 5
DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA4 1 8 2 1
DQ3 DQ12 DDR_B_D13 DDR_B_MA14 C108 0.1U_0402_16V4Z
21 VSS DQ13 22 2 7
DDR_B_D8 23 24 DDR_B_MA7 3 6 1 2
DDR_B_D9 DQ8 VSS DDR_B_DM1 DDR_B_MA11 C107 0.1U_0402_16V4Z
25 DQ9 DM1 26 4 5
27 VSS VSS 28
DDR_B_DQS#1 29 30 47_0804_8P4R_5%
DQS1# CK0 DDR_B_CLK0 5
DDR_B_DQS1 31 32
DQS1 CK0# DDR_B_CLK#0 5
33 34 RP10
DDR_B_D10 VSS VSS DDR_B_D14 DDR_B_BS#2
35 DQ10 DQ14 36 8 1 2 1
DDR_B_D11 37 38 DDR_B_D15 DDR_CKE0_DIMMB 7 2 C109 0.1U_0402_16V4Z
DQ11 DQ15 DDR_CKE1_DIMMB
39 VSS VSS 40 6 3 1 2
DDR_B_MA15 5 4 C110 0.1U_0402_16V4Z

41 42 47_0804_8P4R_5%
DDR_B_D16 VSS VSS DDR_B_D20
43 DQ16 DQ20 44
DDR_B_D17 45 46 DDR_B_D21 RP11
DQ17 DQ21 DDR_B_MA5
47 VSS VSS 48 8 1 2 1
DDR_B_DQS#2 49 50 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z
DDR_B_DQS2 DQS2# NC DDR_B_DM2 DDR_B_MA9
51 DQS2 DM2 52 6 3 1 2
53 54 DDR_B_MA12 5 4 C112 0.1U_0402_16V4Z
DDR_B_D18 VSS VSS DDR_B_D22
55 DQ18 DQ22 56
DDR_B_D19 57 58 DDR_B_D23 47_0804_8P4R_5%
DQ19 DQ23
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D28 RP12
DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_BS#0
63 DQ25 DQ29 64 8 1 2 1
65 66 DDR_B_MA10 7 2 C114 0.1U_0402_16V4Z
DDR_B_DM3 VSS VSS DDR_B_DQS#3 DDR_B_MA3
67 DM3 DQS3# 68 6 3 1 2
69 70 DDR_B_DQS3 DDR_B_MA1 5 4 C113 0.1U_0402_16V4Z
NC DQS3
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30 47_0804_8P4R_5%
2 DDR_B_D27 DQ26 DQ30 DDR_B_D31 2
75 DQ27 DQ31 76
77 78 RP13
DDR_CKE0_DIMMB VSS VSS DDR_CKE1_DIMMB DDR_B_ODT1
5 DDR_CKE0_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMB 5 8 1 2 1
81 82 DDR_CS1_DIMMB# 7 2 C116 0.1U_0402_16V4Z
VDD VDD DDR_B_MA15 DDR_B_CAS#
83 NC NC/A15 84 6 3 1 2
DDR_B_BS#2 85 86 DDR_B_MA14 DDR_B_WE# 5 4 C115 0.1U_0402_16V4Z
5 DDR_B_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11 47_0804_8P4R_5%
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6 RP14
A8 A6 DDR_B_MA13
95 VDD VDD 96 1 8 2 1
DDR_B_MA5 97 98 DDR_B_MA4 DDR_B_ODT0 2 7 C118 0.1U_0402_16V4Z
DDR_B_MA3 A5 A4 DDR_B_MA2 DDR_B_RAS#
99 A3 A2 100 3 6 1 2
DDR_B_MA1 101 102 DDR_B_MA0 DDR_CS0_DIMMB# 4 5 C117 0.1U_0402_16V4Z
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1 47_0804_8P4R_5%
A10/AP BA1 DDR_B_BS#1 5
DDR_B_BS#0 107 108 DDR_B_RAS#
5 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 5
DDR_B_WE# 109 110 DDR_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDR_CS0_DIMMB# 5
111 VDD VDD 112
DDR_B_CAS# 113 114 DDR_B_ODT0
5 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 5
DDR_CS1_DIMMB# 115 116 DDR_B_MA13
5 DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120
5 DDR_B_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
3 DQ35 VSS DDR_B_D44 3
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_B_CLK1 5
165 VSS CK1# 166 DDR_B_CLK#1 5
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
193 194 DDR_B_D63
VSS DQ63
8,15,20,28 SMB_CK_DAT0 195 SDA VSS 196
8,15,20,28 SMB_CK_CLK0 197 SCL SAO 198 +3VS
+3VS 199 VDDSPD SA1 200
1
4 4
C119 PTI_A5652D-A0G16-P
0.1U_0402_16V4Z @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII SO-DIMM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 9 of 46
A B C D E
 A B C D E

SI2:Change to RS780MN
U3B
D4 GFX_RX0P GFX_TX0P A5 TMDS_B_DATA2 18
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 TMDS_B_DATA2# 18
A3 GFX_RX1P GFX_TX1P A4 TMDS_B_DATA1 18
B3 GFX_RX1N GFX_TX1N B4 TMDS_B_DATA1# 18
1 1
C2 GFX_RX2P GFX_TX2P C3 TMDS_B_DATA0 18
C1 GFX_RX2N GFX_TX2N B2 TMDS_B_DATA0# 18
E5 GFX_RX3P GFX_TX3P D1 TMDS_B_CLK 18
F5 GFX_RX3N GFX_TX3N D2 TMDS_B_CLK# 18
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
J5 GFX_RX6N GFX_TX6N F2
J7 GFX_RX7P GFX_TX7P H4
J8 GFX_RX7N GFX_TX7N H3
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 GFX_RX9P GFX_TX9P J2
L8 GFX_RX9N GFX_TX9N J1

PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4
M7 GFX_RX10N GFX_TX10N K3
P5 GFX_RX11P GFX_TX11P K1
M5 GFX_RX11N GFX_TX11N K2
R8 GFX_RX12P GFX_TX12P M4
P8 GFX_RX12N GFX_TX12N M3
R6 GFX_RX13P GFX_TX13P M1
R5 GFX_RX13N GFX_TX13N M2
P4 GFX_RX14P GFX_TX14P N2
P3 GFX_RX14N GFX_TX14N N1
T4 GFX_RX15P GFX_TX15P P1
T3 GFX_RX15N GFX_TX15N P2

AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K New Card

26 PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 26
AD4 AC2 PCIE_ITX_PRX_N0 C153 1 2 0.1U_0402_16V7K
26 PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 26
AE2 AB4 PCIE_ITX_PRX_P1 C154 1 2 0.1U_0402_16V7K Cardreader
2 27 PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 27 2
AD3 AB3 PCIE_ITX_PRX_N1 C155 1 2 0.1U_0402_16V7K
27 PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 27
AD1 AA2 PCIE_ITX_PRX_P2 C156 1 2 0.1U_0402_16V7K
26 PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 26
AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 C157 1 2 0.1U_0402_16V7K WLAN
26 PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 26
V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K
25 PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 25
W6 Y2 PCIE_ITX_PRX_N3 C159 1 2 0.1U_0402_16V7K GLAN
25 PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 25
U5 GPP_RX4P GPP_TX4P Y4
U6 Y3 H_CADOP[0..15] H_CADIP[0..15]
GPP_RX4N GPP_TX4N 4 H_CADOP[0..15] H_CADIP[0..15] 4
U8 V1 PCIE_ITX_PRX_P5 C160 1 2 0.1U_0402_16V7K
26 PCIE_PTX_C_IRX_P5 GPP_RX5P GPP_TX5P PCIE_ITX_C_PRX_P5 26 H_CADON[0..15] H_CADIN[0..15]
U7 V2 PCIE_ITX_PRX_N5 C161 1 2 0.1U_0402_16V7K TV Tuner
26 PCIE_PTX_C_IRX_N5 GPP_RX5N GPP_TX5N PCIE_ITX_C_PRX_N5 26 4 H_CADON[0..15] H_CADIN[0..15] 4

19 SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P 19
19 SB_RX0N Y8 AE7 SB_TX0N_C C163 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 19
19 SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 19
19 SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX1N 19
19 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C166 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P 19 HT_RXCAD0P HT_TXCAD0P
19 SB_RX2N AA6 AC6 SB_TX2N_C C168 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N 19 HT_RXCAD0N HT_TXCAD0N
19 SB_RX3P W5 AD5 SB_TX3P_C C169 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P 19 HT_RXCAD1P HT_TXCAD1P
19 SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N 19 HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R55 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 1 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R56 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22
RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
RS780R1@ HT_RXCAD5P HT_TXCAD5P

HYPER TRANSPORT CPU I/F

H_CADON5 P23 J24 H_CADIN5
H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P25 HT_RXCAD6P HT_TXCAD6P K24
GFX_TX0,TX1,TX2 and TX3 H_CADON6 P24 K25 H_CADIN6
DP0 H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 HT_RXCAD7P HT_TXCAD7P K23
AUX0 and HPD0 H_CADON7 N25 K22 H_CADIN7
HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8
3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

4 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 4

4 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 4
4 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 4
4 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 4
H_CTLOP0 M22 M24 H_CTLIP0
4 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 4
H_CTLON0 M23 M25 H_CTLIN0
4 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 4
H_CTLOP1 R21 P19 H_CTLIP1
4 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 4
H_CTLON1 R20 R18 H_CTLIN1
4 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 4
1 R57 2 301_0402_1% C23 HT_RXCALP HT_TXCALP B24 1 R58 2 301_0402_1%
A24 HT_RXCALN HT_TXCALN B25

0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"

layout 1:2 layout 1:2
4
RS780R1@ 4

NEED CHECK R68 & R69 WITH AMD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780-HT/PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 10 of 46
A B C D E
 A B C D E

+3VS
L2 AVDD=100mA
1 2 RED 1 2 +AVDD1
R62 @ 140_0402_1% BLM18PG121SN1D_0603 1
1 2 GREEN
R63 @ 150_0402_1% +1.8VS C170
1 BLUE L4 2.2U_0603_6.3V4Z 1
1 2
R64 @ 150_0402_1% +AVDD2 2
0_0603_5% 1
U3C
C172 F12 A22 LVDS_A0+ 17
+1.8VS 2.2U_0603_6.3V4Z AVDD1(NC) TXOUT_L0P(NC)
2
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 LVDS_A0- 17
F14 AVDDDI(NC) TXOUT_L1P(NC) A21 LVDS_A1+ 17
L6 G15 B21 LVDS_A1- 17
+AVDDQ AVSSDI(NC) TXOUT_L1N(NC)
1 2 H15 AVDDQ(NC) TXOUT_L2P(NC) B20 LVDS_A2+ 17
+1.8VS +NB_HTPVDD BLM18PG121SN1D_0603 1 H14 A20
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) LVDS_A2- 17
L7 A19
C175 TXOUT_L3P(NC)
1 2 E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z

CRT/TVOUT
1 F17 Y(DFT_GPIO2)
2
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 LVDS_B0+ 17
C176 A18 LVDS_B0- 17
2.2U_0603_6.3V4Z RED TXOUT_U0N(NC)
16 RED G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17 LVDS_B1+ 17
2
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 LVDS_B1- 17
GREEN E18 D20 LVDS_B2+ 17
+1.1VS 16 GREEN GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 GREENb(NC) TXOUT_U2N(NC) D21 LVDS_B2- 17
L9 +NB_PLLVDD BLUE E19 D18 L3
16 BLUE BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
1 2 F19 D19 +VDDLTP18 1 2 +1.8VS
+1.8VS +VDDA18HTPLL BLM18PG121SN1D_0603 BLUEb(NC) TXOUT_U3N(NC) BLM18PG121SN1D_0603
1 1
L10 CRT_HSYNC A11 B16 LVDS_ACLK+ 17
14,16 CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
1 2 C178 CRT_VSYNC B11 A16 LVDS_ACLK- 17 C171
14,16 CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
BLM18PG121SN1D_0603 1 2.2U_0603_6.3V4Z F8 D16 2.2U_0603_6.3V4Z
2 16 UMA_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) LVDS_BCLK+ 17 2
16 UMA_CRT_DAT E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17 LVDS_BCLK- 17
C179
2.2U_0603_6.3V4Z R65 1 2 715_0402_1% G14
2 DAC_RSET(PWM_GPIO1) +VDDLTP18 L5
VDDLTP18(NC) A13
+NB_PLLVDD +NB_PLLVDD A12 B13 +VDDLT18 1 2 +1.8VS
+NB_HTPVDD PLLVDD(NC) VSSLTP18(NC) BLM18PG121SN1D_0603
+NB_HTPVDD D14 PLLVDD18(NC) 1 1
B12 A15 +VDDLT18

LVTM
2 PLLVSS(NC) VDDLT18_1(NC) C173 C174 2
B15

PLL PWR
+1.8VS +VDDA18PCIEPLL VDDLT18_2(NC) 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
L11 2 2
VDDLT33_2(NC) B14
1 2 +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
BLM18PG121SN1D_0603 1 E7 C14
R67 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS)
VSSLT2(VSS) D15
C180 1 2 NB_RESET# D8 C16
14,19,25,26,27,32,33 PLT_RST# SYSRESETb VSSLT3(VSS)
2.2U_0603_6.3V4Z NB_PWRGD A10 C18
2 20 NB_PWRGD POWERGOOD VSSLT4(VSS)
6,19 LDT_STOP# C10 LDTSTOPb VSSLT5(VSS) C20
C12 E20

PM
6,19 CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
+1.8VS C25
15 CLK_NBHT HT_REFCLKP
15 CLK_NBHT# C24 HT_REFCLKN
1 2 NB_PWRGD
R371 300_0402_5% E11
15 NB_OSC_14.318M REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 UMA_ENVDD 17
LVDS_BLON(PCE_RCALRP) F7 ENBKL 33
+1.1VS 1 2 1 2 15 NBGFX_CLK T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12
R71 R72 T1 2 1
15 NBGFX_CLK# GFX_REFCLKN
For SB700 A12 use 4.7K_0402_5% 4.7K_0402_5% R73 100K_0402_5%
U1 GPP_REFCLKP
U2 GPP_REFCLKN
SI2: Add 100K for white screen issue

15 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)
15 CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)

17 LCD_DDC_CLK B9 I2C_CLK
17 LCD_DDC_DAT A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HPD 18
18 HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC)
18 HDMICLK_UMA A8 DDC_CLK0/AUX0P(NC)
B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 1 2 SUS_STAT# 20
A7 R77 0_0402_5% SUS_STAT_R# 14 Strap pin
3 DDC_DATA1/AUX1N(NC) 3
THERMALDIODE_P AE8
+3VS 2 1 B10 STRP_DATA THERMALDIODE_N AD8

PV: Change to Un-mount @R88

@ R88 10K_0402_5% G11 D13 1 2
RSVD TESTMODE R80
C8 1.8K_0402_5%
14 AUX_CAL AUX_CAL(NC)
Strap pin RS780M_FCBGA528
RS780R1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 VEDIO/CLK GEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 11 of 46
A B C D E
 2 1

U61 U3D
MEM_BA0 L2 B9 MEM_DQ15 PAR 4 OF 6
MEM_BA1 BA0 DQ15 MEM_DQ11 MEM_A0 MEM_DQ0
L3 BA1 DQ14 B1 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
D9 MEM_DQ13 MEM_A1 AE16 AA20 MEM_DQ1
MEM_A12 DQ13 MEM_DQ12 MEM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2
R2 A12 DQ12 D1 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
MEM_A11 P7 D3 MEM_DQ8 MEM_A3 AE15 Y19 MEM_DQ3
MEM_A10 A11 DQ11 MEM_DQ10 MEM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4
M2 A10/AP DQ10 D7 AA12 MEM_A4(NC) MEM_DQ4(NC) V17
MEM_A9 P3 C2 MEM_DQ9 MEM_A5 AB16 AA17 MEM_DQ5
MEM_A8 A9 DQ9 MEM_DQ14 MEM_A6 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6
P8 A8 DQ8 C8 AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
MEM_A7 P2 F9 MEM_DQ3 MEM_A7 AD14 Y15 MEM_DQ7
MEM_A6 A7 DQ7 MEM_DQ7 MEM_A8 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8
N7 A6 DQ6 F1 AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
MEM_A5 N3 H9 MEM_DQ1 MEM_A9 AD15 AD19 MEM_DQ9
A5 DQ5 MEM_A9(NC) MEM_DQ9/DVO_D5(NC)

SBD_MEM/DVO_I/F
MEM_A4 N8 H1 MEM_DQ6 MEM_A10 AC16 AE22 MEM_DQ10
MEM_A3 A4 DQ4 MEM_DQ5 MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11
N2 A3 DQ3 H3 AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
MEM_A2 M7 H7 MEM_DQ0 MEM_A12 AC14 AB20 MEM_DQ12
MEM_A1 A2 DQ2 MEM_DQ4 MEM_A12(NC) MEM_DQ12(NC) MEM_DQ13
M3 A1 DQ1 G2 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_A0 M8 G8 MEM_DQ2 AC22 MEM_DQ14
A0 DQ0 MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
1

MEM_BA1 AE17
R91 MEM_CLKN MEM_BA2 MEM_BA1(NC) MEM_DQS_P0
K8 CK VDDQ A9 +1.8V_MEM_VDDQ AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_CLKP J8 C1 W18 MEM_DQS_N0 MEM_COMP_P and MEM_COMP_N trace
100_0402_1% CK VDDQ MEM_RAS# MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS_P1
C3 W12 AD20
B @ MEM_CKE K2
VDDQ
C7 MEM_CAS# Y12
MEM_RASb(NC) MEM_DQS1P(NC)
AE21 MEM_DQS_N1 width >=10mils and 10mils spacing from B
2

CKE VDDQ MEM_CASb(NC) MEM_DQS1N(NC)

VDDQ C9 MEM_WE# AD18 MEM_WEb(NC)
other Signals in X,Y,Z directions
E9 MEM_CS# AB13 W17 MEM_DM0
VDDQ MEM_CKE MEM_CSb(NC) MEM_DM0(NC) MEM_DM1 +1.8VS
VDDQ G1 AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
MEM_CS# L8 G3 MEM_ODT V14 L12
CS VDDQ MEM_ODT(NC) L13 +1.8V_IOPLLVDD
VDDQ G7 IOPLLVDD18(NC) AE23 1 2
MEM_WE# K3 G9 MEM_CLKP V15 AE24 +NB_IOPLLVDD 1 2 +1.1VS 0_0603_5%
WE VDDQ MEM_CLKN MEM_CKP(NC) IOPLLVDD(NC) 0_0603_5%
W14 MEM_CKN(NC) 1 1
MEM_RAS# K7 A1 SIDE@ AD23 1
RAS VDD MEM_COMP_P IOPLLVSS(NC) C181 C183
VDD E1 2 1 AE12 MEM_COMPP(NC)
MEM_CAS# L7 J9 R92 40.2_0402_1% AD12 AE18 +MEM_VREF1 2.2U_0603_6.3V4Z C182 2.2U_0603_6.3V4Z
CAS VDD MEM_COMP_N MEM_COMPN(NC) MEM_VREF(NC) 2 0.1U_0402_16V4Z 2
VDD M9 +1.8V_MEM_VDDQ 2 1
MEM_DM0 +1.8V_MEM_VDDQ R93 40.2_0402_1% RS780M_FCBGA528 SIDE@ 2 SIDE@ SIDE@
F3 LDM VDD R1
MEM_DM1 B3 SIDE@ RS780R1@
UDM +VDDL
VDDL J1

1U_0603_10V6K
VSSDL J7
MEM_ODT K9 1 Layout Note: 50 mil for VSSDL
ODT
C184
MEM_DQS_P0 F7 SIDE@
MEM_DQS_N0 LDQS 2
E8 LDQS VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
MEM_DQS_P1 B7 D8
MEM_DQS_N1 UDQS VSSQ
A8 UDQS VSSQ E7
VSSQ F2
VSSQ F8
+MEM_VREF J2 H2
VREF VSSQ
VSSQ H8
A2 NC
E2 NC VSS A3
MEM_BA2 L1 E3
NC VSS
R3 NC VSS J3
R7 NC VSS N1
R8 NC VSS P9

HY5PS561621AFP-25_FBGA84
SIDE@

+1.8V_MEM_VDDQ +1.8V_MEM_VDDQ
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

2
1K_0402_1%

1K_0402_1%

1 1
C195

C196

SIDE@ SIDE@ SIDE@ SIDE@

+1.8V_MEM_VDDQ
R96

R97

A A
2 2 +1.8VS
1

L15
+MEM_VREF +MEM_VREF1 22U_0805_6.3V6M 1 2
1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SIDE@0_0805_5%
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 1 1 1 220 ohm @ 100MHz,2A

1 1
2

2
1K_0402_1%

1K_0402_1%

C608

C607

C201

C202

SIDE@ SIDE@ SIDE@ SIDE@ C203

C199

C200

SIDE@ SIDE@ SIDE@ SIDE@

SIDE@ 1 1 2 2 2
2 2
R98

R99
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 SIDE PORT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 12 of 46
2 1
 A B C D E

U3F
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L16 1
2A H19 VSSAHT7 VSSAPCIE7 G2
+1.1VS 2 1 +VDDHT J22 G4
0_0805_5% VSSAHT8 VSSAPCIE8
L17 VSSAHT9 VSSAPCIE9 H7
1 1 1 1 1 L22 VSSAHT10 VSSAPCIE10 J4
L17 L24 R7
C209 C206 C207 C208 C210 VSSAHT11 VSSAPCIE11
1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
2 2 2 2 2 U3E VSSAHT13 VSSAPCIE13
N22 VSSAHT14 VSSAPCIE14 L4
J17 A6 +VDDA11PCIE P20 L7
VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 R19 VSSAHT16 VSSAPCIE16 M6
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L18 2A 0.1U_0402_16V4Z 0.1U_0402_16V4Z M16 D6 C212 10U_0805_10V4Z R24 P6
+VDDHTRX VDDHT_4 VDDPCIE_4 VSSAHT18 VSSAPCIE18
2 1 P16 VDDHT_5 VDDPCIE_5 E6 R25 VSSAHT19 VSSAPCIE19 R1
0_0805_5% R16 F6 C220 1 2 1U_0402_6.3V4Z H20 R2
VDDHT_6 VDDPCIE_6 C219 1U_0402_6.3V4Z VSSAHT20 VSSAPCIE20
1 1 1 1 T16 VDDHT_7 VDDPCIE_7 G7 1 2 U22 VSSAHT21 VSSAPCIE21 R4
H8 C222 1 2 1U_0402_6.3V4Z V19 V7
C215 C214 C216 C217 C218 VDDPCIE_8 C221 1U_0402_6.3V4Z VSSAHT22 VSSAPCIE22

GROUND
PV:Change C215 from 4.7u to 10u H18 VDDHTRX_1 VDDPCIE_9 J9 1 2 W22 VSSAHT23 VSSAPCIE23 U4
G19 K9 C224 2 1 0.1U_0402_16V4Z W24 V8
2 2 2 2 VDDHTRX_2 VDDPCIE_10 C223 0.1U_0402_16V4Z VSSAHT24 VSSAPCIE24
F20 VDDHTRX_3 VDDPCIE_11 M9 2 1 W25 VSSAHT25 VSSAPCIE25 V6
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2
0.1U_0402_16V4Z 0.1U_0402_16V4Z B23 R9 W4
VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L19 2A V9 M14 W8
+VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 N13 VSS13 VSSAPCIE31 Y6
0_0805_5% AD24 PJP3 P12 AA4
L43 VDDHTTX_2 VSS14 VSSAPCIE32
1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_VDDC P15 VSS15 VSSAPCIE33 AB5
+1.35VS 2 1 AB22 VDDHTTX_4 VDDC_2 J14 R11 VSS16 VSSAPCIE34 AB1
C225 C226 C227 C228 C229 AA21 U16 PAD-OPEN 4x4m R14 AB7
@ FBMA-L11-201209-221LMA30T_0805 VDDHTTX_5 VDDC_3 VSS17 VSSAPCIE35
Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
2 2 2 2 2
W19 VDDHTTX_7 VDDC_5 K15 U14 VSS19 VSSAPCIE37 AC4

POWER
2
V18 VDDHTTX_8 VDDC_6 M12 VDD_CORE=5A U11 VSS20 VSSAPCIE38 AE1
2
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 V12 AB2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

330U_D2E_2.5VM
C247

C240

C241

C242

C243

C230

C231

C244

C232

C233

C245
L22 2A N14 1 AA14 D11
+VDDA18PCIE VDDC_12 VSS26 VSS2
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8

C234
<BOM Structure>0_0805_5% P10 P13 + AB11 E14
VDDA18PCIE_2 VDDC_14 VSS28 VSS4
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 AB17 VSS30 VSS6 J15
C235 C246 C236 C237 C238 C239 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15
R10 VDDA18PCIE_9 VDDC_21 T14
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Y9 J16 RS780M_FCBGA528
0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 AA11 1 2 RS780R1@
VDDA18PCIE_13 VDD_MEM2(NC) +1.8VS
AE9 Y11 L82 SIDE@0_0603_5% PV:Add 0ohm unmount
VDDA18PCIE_14 VDD_MEM3(NC)
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
AB10 1U_0402_6.3V4Z 2 1 C249 SIDE@
VDD_MEM5(NC) +VDD_MEM 1U_0402_6.3V4Z 2 C248 SIDE@
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10 1
G9 0.1U_0402_16V4Z 2 1 C597 SIDE@
VDD18_2 0.1U_0402_16V4Z 2 C598 SIDE@
+1.8VS AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 1
AD11 H12 0.1U_0402_16V4Z 2 1 C599 SIDE@
VDD18_MEM2(NC) VDD33_2(NC)
1 2 MV:Add 0ohm mount
1 1 RS780M_FCBGA528 0_0402_5% R625
C251 RS780R1@ +3VS
1U_0402_6.3V4Z C252
1U_0402_6.3V4Z 1 2
2 2 0.1U_0402_16V4Z C250
3
@ 3
1 2
0.1U_0402_16V4Z C253

+1.8VS

U67
1 VIN VCNTL 6 +3VS
1 2 GND NC 5
1

C903 3 7 1
@ 10U_0805_10V4Z VREF NC C463
2 R599 @ 1U_0603_10V6K
4 VOUT NC 8
@ 1K_0402_1%
2
9
2

TP
@ G2992F1U_SO8
+VREF1.35V

+1.35VS
1

Q56 R600
@ 2N7002_SOT23-3 @ 3K_0402_5% 2 1
1

4 D 4
1 2 2 C702 C905
36 VLDT_EN#
2

R601 @ 0_0402_5% G
S 1 2 @ 10U_0805_10V4Z
2
3

C703
@ 0.1U_0402_16V7K
1 @ 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 13 of 46
A B C D E
 A B C D E

RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

SI2: Change to 3K pull high
11,16 CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO.
R101 3K_0402_5%
1 : Enable (RX780, RS780)
2 1
1 R102 @ 3K_0402_5% 0 : Disable (RX780, RS780) 1
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
RS780 use register to control PCI-E configure 010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011

2 2

DFT_GPIO1: LOAD_EEPROM_STRAPS

11 AUX_CAL 1 2
@R104
@ R104 150_0402_1% Selects Loading of STRAPS from EPROM
D4 @ CH751H-40PT_SOD323-2
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
RS780 DFT_GPIO1 2 1 0 : I2C Master can load strap values from EEPROM if connected, or use
11 SUS_STAT_R# PLT_RST# 11,19,25,26,27,32,33
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
3 3

RX780: Enables the Test Debug Bus using PCIE bus

1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS780)
11,16 CRT_HSYNC 2 1
R107 @ 3K_0402_5% 0 : Enable (RS780)

2 1 +3VS
R125 3K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS780 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 14 of 46
A B C D E
 A B C D E

+1.2V_HT +VDDCLK_IO +3VS_CLK

R167
+3VS 1 2
R168 0_0805_5% 1 1 1 1 1 1 1 1
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 C451
0_0805_5% 1 1 1 1 1 1 C444
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
2 2 2 2 2 2
+3VS_CLK
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1
1 C458 C459 C460 C461 1

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2

CLK_XTAL_OUT

CLK_XTAL_IN

SI2:follow AMD request modify resistor value

Y2
R170 1 2 33_0402_5%
CLK_48M_USB 20
2 1 OSC_14M_NB
NB_OSC_14.318M_R 1 2
14.31818MHZ_20P_6X1430004201 R379 158_0402_1% NB_OSC_14.318M 11
RS780 1.1V 158R/90.9R

+3VS_CLK
1 1 1 2 R380
C464 C465 90.9_0402_1%

22P_0402_50V8J 22P_0402_50V8J R220 1 2 @ 33_0402_5% MV:unmount for MP

2 2 CLK_14M_SIO 32
CLK_NBHT 11

+3VS_CLK
+3VS_CLK
CLK_NBHT# 11 NB
1 2 +3VS_CLK MV:Add for ICS CLK

CLK_XTAL_OUT
Routing the trace at least 10mil R174 8.2K_0402_5%
CLK_CPU_BCLK 6

CLK_XTAL_IN

SEL_SATA
1 2

2
27M_SEL
2 C629 @ 1U_0402_6.3V4Z 2
1 2 R186
R946 0_0402_5% @ 261_0402_1% CPU
1 2
R945 0_0402_5%

1
CLK_CPU_BCLK# 6

73

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
U10

GND

XTAL_IN

REF_1/SEL_SATA
VSS_48
48MHz_0
48MHz_1
VDD_48

CPU_K8_0
HTT_0#/66M_1

PD#
XTAL_OUT

VSS_REF
REF_0/SEL_HTT66

REF_2/SEL_27

HTT_0/66M_0
VDD_REF
VDD_HTT

VSS_HTT

CPU_K8_0#
CLKREQ_NCARD# 1 2 +3VS_CLK
R324 8.2K_0402_5%
CLKREQ_MCARD2# 1 2
1 54 +3VS_CLK R325 8.2K_0402_5%
8,9,20,28 SMB_CK_CLK0 SCL VDD_CPU CLKREQ_MCARD1#
2 SDA VDD_CPU_I/O 53 +VDDCLK_IO 1 2
8,9,20,28 SMB_CK_DAT0 R326 8.2K_0402_5%
+3VS_CLK 3 VDD_DOT VSS_CPU 52
4 51 CLKREQ_NCARD# CLKREQ_LAN 1 2
SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# 26 R390 8.2K_0402_5%
5 SRC_7/27M_SS CLKREQ_2# 50
CLKREQ_MCARD2# 26
6 VSS_DOT VDD_A 49 +3VS_CLK
7 SRC_5# VSS_A 48
8 SRC_5 VSS_SATA 47
PA_RS7X0A1 11 CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK 19 PA_RS7X0A1
SB LINK 11 CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# 19 SB SRC
11 VSS_SRC VDD_SATA 44 +3VS_CLK
+VDDCLK_IO 12 43 CLKREQ_MCARD1#
VDD_SRC_IO CLKREQ_3# CLKREQ_MCARD1# 26
26 CLK_PCIE_MCARD1# 13 SRC_3# CLKREQ_4# 42
Card reader 26 CLK_PCIE_MCARD1 14 SRC_3 SB_SRC_SLOW# 41 1 2 +3VS_CLK
15 40 R372 10K_0402_5%
26 CLK_PCIE_MCARD2# SRC_2# SB_SRC_0
MiniCard_2 26 CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39
+3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
+VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO

VDD_ATIG_IO

VSS_SB_SRC
3 3

ATIGCLK_2#

ATIGCLK_1#

ATIGCLK_0#
CLKREQ_0#

SB_SRC_1#
ATIGCLK_2

ATIGCLK_1

ATIGCLK_0

SB_SRC_1
VDD_ATIG
VSS_ATIG
VSS_SRC
SRC_1#

SRC_0#
SRC_1

SRC_0

+3VS_CLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2

SLG8SP626VTR_QFN72_10x10
R179
@ 8.2K_0402_5% SI2: Use new version CLK gen
1

SEL_SATA +3VS_CLK
+3VS_CLK
+VDDCLK_IO
2

R181 NB CLOCK INPUT TABLE

NBGFX_CLK 11
8.2K_0402_5% R180 NB GFX
NBGFX_CLK# 11
8.2K_0402_5% NB CLOCKS RX780 RS780
1

HT_REFCLKP
1

27M_SEL 100M DIFF 100M DIFF

HT_REFCLKN 100M DIFF 100M DIFF
CLK_PCIE_MCARD0 27
MiniCard_1 REFCLK_P
CLK_PCIE_MCARD0# 27
1 configure as SATA output CLKREQ_LAN 14M SE (1.8V) 14M SE (1.1V)
CLKREQ_LAN 25
SEL_SATA 1 * configure as 27M and 27M_SS output REFCLK_N NC vref
CLK_PCIE_LAN 25
0 * configure as normal SRC(SRC_6) output 27M_SEL GLAN
CLK_PCIE_LAN# 25
* default 0 configure as SRC_7 output GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
* default New Card
CLK_PCIE_NCARD 26 NC or 100M DIFF OUTPUT
GPP_REFCLK 100M DIFF
4 CLK_PCIE_NCARD# 26 4
GPPSB_REFCLK 100M DIFF 100M DIFF

Use voltage divider resistor R379 & R380 to pull low

1 configure as single-ended 66MHz output

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
NB_OSC_14.318M
0* configure as differential 100MHz output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
* default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 15 of 46
A B C D E
 A B C D E

CRT CONNECTOR
1 1
+5VS +R_CRT_VCC +CRT_VCC
D36 F2
2 1 1 2

1
D35 D37 D34 1
RB491D_SOT23 1A_6VDC_MINISMDC110
C475
0.1U_0402_16V4Z
+3VS 2
DAN217_SC59 DAN217_SC59DAN217_SC59

3
@ @ @

MV: modify bead to BLM15BB121SN1D JP6

6
L47 11
RED 1 2 RED_L 1
11 RED
BLM15BB121SN1D_0402 7
L48 D_DDCDATA 12
GREEN 1 2 GREEN_L 2
11 GREEN
BLM15BB121SN1D_0402 8
L49 HSYNC 13
BLUE 1 2 BLUE_L 3
11 BLUE
BLM15BB121SN1D_0402 +CRT_VCC 9

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
VSYNC 14

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
69.8_0402_1%
1 1 1 4

1
75_0402_1%

75_0402_1%
1 1 1 10
MV: modify pull low resistor R214 C471 C859 C469 D_DDCCLK 15
R211 R217 C858 5
2 2 2 C476 C472
2 2 2
16 GND

2
RED_L 35 17 GND
2 2
GREEN_L 35
+3VS SUYIN_070546FR015S265ZR
BLUE_L 35
+CRT_VCC @

+CRT_VCC SI:change CRT Conn.

1

R237 R238 +3VS 1 2

4.7K_0402_5% 4.7K_0402_5% R100 R218 C473

5
1
0.1U_0402_16V4Z
5

6.8K_0402_5% 6.8K_0402_5%

P
OE#
2

2 4 D_HSYNC 1 2 HSYNC
11,14 CRT_HSYNC A Y
4 3 D_DDCDATA L84 10_0402_5%
11 UMA_CRT_DAT D_DDCDATA 35

G
U14
Q10B

3
2N7002DW-7-F_SOT363-6 SN74AHCT1G125GW_SOT353-5 1 2 VSYNC
L83 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
+3VS +CRT_VCC
1 1

1 2 C474 C470
2

C477 @ @

5
1
0.1U_0402_16V4Z 2 2
1 6 D_DDCCLK

P
OE#
11 UMA_CRT_CLK D_DDCCLK 35
2 4 D_VSYNC
11,14 CRT_VSYNC A Y
Q10A 1 1

G
U13
2N7002DW-7-F_SOT363-6 C857 C856 SN74AHCT1G125GW_SOT353-5

3
@ @
RS780 DAC_SCL & SDA is 5V tolerance 470P_0402_50V8J 2 2 470P_0402_50V8J
D_HSYNC 35
3 3

D_VSYNC 35

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 16 of 46
A B C D E
 A B C D E

+LCDVDD

+5VALW

1
R225

2
470_0805_5%
R224
1M_0402_5% +3VS

3 2
1 1
80mil

3
S
Q144B R222 G
2N7002DW-7-F_SOT363-6 5 1 2 2 Q43
100K_0402_5% SI2301BDS-T1-E3_SOT23-3

6
D
2

1
80mil
C863 +LCDVDD
2 1000P_0402_50V7K
11 UMA_ENVDD Q144A 1

2
2N7002DW-7-F_SOT363-6 1

1
R276
2.2K_0402_5% C487 C491
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2

1
2 2

+LCDVDD INVPWR_B+

+3VS B+ L44 INVPWR_B+

2 1
FBMA-L11-201209-221LMA30T_0805
MV: mount for EMI

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
1 1 1

LVDS CONN
C481

C479

C480
LVDS_ACLK- 1 2
2 2 2 JP7 @ C868 680P_0402_50V7K
1 2 LVDS_ACLK+ 1 2
D22 1 2 LVDS_A2- 11
3 4 @ C869 680P_0402_50V7K
3 4 LVDS_A2+ 11
+5VALW 4 2 USB20_P5 5 6
VIN IO1 5 6 LVDS_A1- 11
7 8 DMIC_DAT 1 2
7 8 LVDS_A1+ 11
USB20_N5 3 1 9 10 @C923
@ C923 220P_0402_50V7K
IO2 GND 9 10 LVDS_A0- 11
11 12 DMIC_CLK 1 2
11 12 LVDS_A0+ 11
@ PRTR5V0U2X_SOT143-4 20 USB20_P5 USB20_P5 13 14 LVDS_ACLK- @C924
@ C924 220P_0402_50V7K
13 14 LVDS_ACLK- 11
20 USB20_N5 USB20_N5 15 16 LVDS_ACLK+
15 16 LVDS_ACLK+ 11
17 17 18 18 SI2: Add 220P for EMI
19 19 20 20
21 21 22 22
LVDS_BCLK+ 23 24 DMIC_DAT
11 LVDS_BCLK+ 23 24 DMIC_DAT 29
2 1 LVDS_BCLK+ LVDS_BCLK- 25 26 DMIC_CLK
3 11 LVDS_BCLK- 25 26 DMIC_CLK 29 3
680P_0402_50V7K C870 @ 27 28 1 2 +5VS SI: Change R491 to 0805 size
LVDS_BCLK- 27 28 INVT_PWM 100_0805_5% R491
2 1 11 LVDS_B0+ 29 29 30 30 INV_PWM 33
680P_0402_50V7K C871 @ 31 32 BKOFF# BKOFF# 33
11 LVDS_B0- 31 32
33 34 DAC_BRIG
11 LVDS_B1+ 33 34 DAC_BRIG 33
11 LVDS_B1- 35 35 36 36 +USB_CAM
37 38 LCD_DDC_CLK
11 LVDS_B2+ 37 38 LCD_DDC_CLK 11
39 40 LCD_DDC_DAT
11 LVDS_B2- 39 40 LCD_DDC_DAT 11
41 GND GND 42

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K
1 1 1

680P_0402_50V7K

680P_0402_50V7K
1 2 LVDS_GND ACES_88242-4001

C482

C483

C628
@

C866

C867
PJP8 PAD-OPEN 3x3m
SI: Add +5VS jumper 2 2 2

2
1 2 +3VS
@ @
PJP9 PAD-OPEN 3x3m BKOFF# 1 2
+5VALW +5VS @ 4.7K_0402_5% R483
PV: mount for EMI
LCD_DDC_CLK 1 2
1

4.7K_0402_5% R274
PJP4 +USB_CAM
PAD-OPEN 2x2m PJP7 LCD_DDC_DAT 1 2
PAD-OPEN 2x2m @ 215K_0402_1% 4.7K_0402_5% R275
U54
1
2

1 VIN VOUT 5
2 R891
2

2 GND
C720 R16 2
2

10U_0805_10V4Z 0_0402_5% 3 4
1 EN BP C719
1

RT9193-39GB_SOT23-5 1 10U_0805_10V4Z
1

4 R892 1 4
21 CAM_SHDN# 2 1
R17 @ 0_0402_5% C511 100K_0402_1%
0.1U_0402_16V4Z @
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 17 of 46
A B C D E
 A B C D E

+3VS +HDMI_5V_OUT

+HDMI_5V_OUT

2
HDMI_HPD +3VS
C851 2 R176 R209
1 0.1U_0402_16V4Z 2 1 4.7K_0402_5% 4.7K_0402_5% R210 R236 1
+3VS

2
R615 R628 2 C850 6.8K_0402_5% 6.8K_0402_5%
5
1

5
2.2K_0402_5% 100K_0402_5% 0.1U_0402_16V4Z

1
1 P
OE# HDMI_SDATA
2 A Y 4 HPD 11 11 HDMIDAT_UMA 4 3
1

1
G

U39
SN74AHCT1G125GW_SOT353-5 Q139B
3

2N7002DW-7-F_SOT363-6

+3VS

2
1 6 HDMI_SCLK
11 HDMICLK_UMA

Q139A
2N7002DW-7-F_SOT363-6

2 2

MP:Update D10 to meet HDMI.

SI:Add R6161~R624 for EMI requset
D10
HDMI_CLK- 1 2 HDMI_R_CK- +5VS 2 1 +HDMI_5V_OUT
R616 0_0402_5%
RB491D_SOT23
L85
1 1 2 2 1
SI:Add Q136 & Q137 for AMD request C468

4 3 0.1U_0402_16V4Z
4 3 2
@ WCM-2012-900T_0805
HDMI_CLK+ 1 2 HDMI_R_CK+
R617 0_0402_5% Q136A
2N7002DW-7-F_SOT363-6
HDMI_R_CK+ 1 2 6 1
R307 715_0402_1%
HDMI_TX0- 1 2 HDMI_R_D0- HDMI_R_CK- 1 2
R618 0_0402_5% R315 715_0402_1%

2
C507 1 2 0.1U_0402_16V7K HDMI_CLK+
10 TMDS_B_CLK
C508 1 2 0.1U_0402_16V7K HDMI_CLK- L86 +5VS
10 TMDS_B_CLK#
1 1 2 2

C655 1 2 0.1U_0402_16V7K HDMI_TX0+ Q136B

10 TMDS_B_DATA0
C675 1 2 0.1U_0402_16V7K HDMI_TX0- 4 3 2N7002DW-7-F_SOT363-6
3 10 TMDS_B_DATA0#

C804 1
@
4 3
WCM-2012-900T_0805
HDMI_R_D0- 1
R304
2
715_0402_1%
3 4
HDMI Connector 3

10 TMDS_B_DATA1 2 0.1U_0402_16V7K HDMI_TX1+ HDMI_TX0+ 1 2 HDMI_R_D0+ HDMI_R_D0+ 1 2

C827 1 2 0.1U_0402_16V7K HDMI_TX1- R619 0_0402_5% R172 715_0402_1%
10 TMDS_B_DATA1#

5
+HDMI_5V_OUT JP8
+5VS 18 +5V
C852 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_SDATA 16 13
10 TMDS_B_DATA2 SDA CEC
C853 1 2 0.1U_0402_16V7K HDMI_TX2- HDMI_TX1- 1 2 HDMI_R_D1- HDMI_SCLK 15 14
10 TMDS_B_DATA2# Q137A SCL Reserved
R620 0_0402_5% HDMI_HPD 19
2N7002DW-7-F_SOT363-6 HP_DET
GND 2
L87 HDMI_R_D1- 1 2 6 1 HDMI_R_CK- 12 5
R297 715_0402_1% HDMI_R_CK+ CK- GND
1 1 2 2 10 CK+ GND 8
HDMI_R_D1+ 1 2 HDMI_R_D0- 9 11
R173 715_0402_1% HDMI_R_D0+ D0- GND
7 20

2
HDMI_R_D1- D0+ GND
4 4 3 3 6 D1- GND 21
+5VS HDMI_R_D1+ 4 22
@ WCM-2012-900T_0805 HDMI_R_D2- D1+ GND
3 D2- GND 23
HDMI_TX1+ 1 2 HDMI_R_D1+ HDMI_R_D2+ 1 17
R621 0_0402_5% Q137B D2+ DDC/CEC_GND
2N7002DW-7-F_SOT363-6
HDMI_R_D2+ 1 2 3 4 @ SUYIN_100042MR019S153ZL
R141 715_0402_1%
HDMI_TX2- 1 2 HDMI_R_D2- HDMI_R_D2- 1 2 SI:Update HDMI footprint
R623 0_0402_5% R139 715_0402_1%

5
L88 +5VS
1 1 2 2 PV:Change R from 750ohm to 715 ohm

4 4 3 3

@ WCM-2012-900T_0805
4 HDMI_TX2+ HDMI_R_D2+ 4
1 2
R624 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 18 of 46
A B C D E
 A B C D E

Check AMD need pull low or not

1 2 NB_RST#_R
R300 @ 8.2K_0402_5%
U15A

NB_RST#_R N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3

PCI CLKS
C492 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
1 10 SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 23 1
C493 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
10 SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 23
C494 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
10 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 23
C495 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
10 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 23
C496 1 2 0.1U_0402_16V7K SB_RX2P_C U25
10 SB_RX2P PCIE_TX2P
C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
10 SB_RX2N PCIE_TX2N
C498 1 2 0.1U_0402_16V7K SB_RX3P_C T23
10 SB_RX3P PCIE_TX3P
C499 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
10 SB_RX3N PCIE_TX3N PCIRST#

PCI EXPRESS INTERFACE

10 SB_TX0P U22 PCIE_RX0P
10 SB_TX0N U21 PCIE_RX0N AD0 U2
10 SB_TX1P U19 PCIE_RX1P AD1 P7
10 SB_TX1N V19 PCIE_RX1N AD2 V4
10 SB_TX2P R20 PCIE_RX2P AD3 T1
10 SB_TX2N R21 PCIE_RX2N AD4 V3
10 SB_TX3P R18 PCIE_RX3P AD5 U1
10 SB_TX3N R17 PCIE_RX3N AD6 V1
AD7 V2
R305 2 1 562_0402_1% T25 T2
R306 PCIE_CALRP AD8
+PCIE_VDDR 2 1 2.05K_0402_1% T24 PCIE_CALRN AD9 W1
L53 T9
+SB_PCIEVDD AD10
+1.2V_HT 1 2 P24 PCIE_PVDD AD11 R6
BLM18PG121SN1D_0603 1 1 R7
AD12
P25 PCIE_PVSS AD13 R5
C504 C505 U8
+3VALW 10U_0805_10V4Z 1U_0402_6.3V4Z AD14
C506 AD15 U5
2 2
AD16 Y7
2 1 AD17 W8
AD18 V9
5

@ 0.1U_0402_16V4Z U16 Close to SB Y8

AD19
2 AA8
P

B PLT_RST# AD20
Y 4 PLT_RST# 11,14,25,26,27,32,33 AD21 Y4
NB_RST#_R 1 Y3
A AD22
G

2 @ NC7SZ08P5X_NL_SC70-5 PCI_AD23 2
AD23 Y2 PCI_AD23 23
AA2 PCI_AD24
PCI_AD24 23
3

AD24 PCI_AD25
AD25 AB4 PCI_AD25 23
N25 AA1 PCI_AD26
15 CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 23
N24 AB3 PCI_AD27
15 CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 23
2 1 AB2 PCI_AD28
AD28 PCI_AD28 23
R312 33_0402_5% K23 AC1
NB_DISP_CLKP AD29
K22 NB_DISP_CLKN AD30 AC2
AD31 AD1
M24 W2

PCI INTERFACE
NB_HT_CLKP CBE0#
M25 NB_HT_CLKN CBE1# U7
CBE2# AA7
P17 CPU_HT_CLKP CBE3# Y1
M18 CPU_HT_CLKN FRAME# AA6
DEVSEL# W5
M23 SLT_GFX_CLKP IRDY# AA5
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6
J19 GPP_CLK0P STOP# W6
J18 GPP_CLK0N PERR# W4
SERR# V7 PCI_SERR# 33
L20 GPP_CLK1P REQ0# AC3
L19 GPP_CLK1N REQ1# AD4
@ R314 20M_0402_5%
@R314 AB7
REQ2#
1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 AB6 PAD T15
GPP_CLK2N REQ4#/GPIO71
C643 GNT0# AD2

CLOCK GENERATOR
N22 GPP_CLK3P GNT1# AE4
1 2 SB_32KHI P22 AD5
GPP_CLK3N GNT2#
GNT3#/GPIO72 AC6
18P_0402_50V8J Y3 L18 AE5 PAD T16
25M_48M_66M_OSC GNT4#/GPIO73
1

4 3 AD6 PAD T17

3 R389 OUT NC CLKRUN# 3
LOCK# V5
20M_0603_5% 1 2 J21
IN NC 25M_X1 CLK_PCI_EC C501 1
INTE#/GPIO33 AD3 1 2 2@ 100P_0402_25V8K
32.768KHZ_12.5P_1TJS125BJ4A421P AC4 R303 @ 100_0402_5%
C652
2

INTF#/GPIO34 CLK_PCI_SIO C503 1

INTG#/GPIO35 AE2 1 2 2@ 100P_0402_25V8K
1 2 SB_32KHO J20 AE3 PCI_PIRQH# R967 2 1 0_0402_5% R369 @ 100_0402_5%
25M_X2 INTH#/GPIO36 ACCEL_INT 28
18P_0402_50V8J
08/29 new add
G22 R308 1 2 22_0402_5% CLK_PCI_EC
LPCCLK0 CLK_PCI_EC 23,33
Close to SB E22 R309 1 2 22_0402_5% CLK_PCI_SIO
LPCCLK1 CLK_PCI_SIO 23,32
SB_32KHI A3 H24 R310 1 2@ 22_0402_5%
X1 LAD0 LPC_AD0 32,33 CLK_PCI_SIO2 32
LAD1 H23
J25
LPC_AD1 32,33 EC & TPM &Debug
LAD2 LPC_AD2 32,33
J24
RTC XTAL

LAD3 LPC_AD3 32,33

LPC

SB_32KHO B3 H25
X2 LFRAME# LPC_FRAME# 32,33
LDRQ0# H22
LDRQ1#/GNT5#/GPIO68 AB8 LPC_DRQ1# 32
BMREQ#/REQ5#/GPIO65 AD7
+3VS 2 1 H_PROCHOT# V15
SERIRQ SIRQ 32,33
R319 10K_0402_5%
CPU_LDT_REQ# F23
6,11 CPU_LDT_REQ# ALLOW_LDTSTP
H_PROCHOT#
6 H_PROCHOT#
H_PWRGD
F24
F22
PROCHOT# RTCCLK C3
C2
RTC_CLK 23 STRAP PIN
6,43 H_PWRGD LDT_PG INTRUDER_ALERT# +3VL
CPU

6,11 LDT_STOP# G25 LDT_STP# VBAT B2 +SB_VBAT

G24 +SB_VBAT +RTCVCC
6 LDT_RST# LDT_RST# +RTCBATT
RTC

R316 R317 D42

120_0402_5% 120_0402_5% 2
1 2 1 2 1 R876 JBATT1
218S7EALA11FG_BGA528_SB700 1 1 3 1 2 W=20mils 1
W=20mils 1
W=20mils 2 2

2
C509 C510 DAN202U_SC70 1K_0402_5% 3
4 SBR1@ J1 GND 4
4

2
2 2 @ JUMP_43X39 GND
1U_0402_6.3V4Z ACES_85205-02001

1
CONN@
0.1U_0402_16V4Z

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700-PCIE/PCI/ACPI/LPC/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 19 of 46
A B C D E
 A B C D E

+3VALW

2
R561
10K_0402_5%

1
PCIE_WAKE#
25,26 LAN_PCIE_WAKE# U15D
1 2 C617 1 2@ 100P_0402_25V8K
25,26 MINI_PCIE_WAKE# R311 @ 100_0402_5%
SB700 Part 4 of 5
1 1
E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 15
demo circuit LID use RI# H7 SLP_S2/GPM9#
F5 G8 USB_RCOMP 1 2
33 SLP_S3# SLP_S3# USB_RCOMP
G1 11.8K_0402_1% R323
33 SLP_S5# SLP_S5#

USB MISC
ACPI / WAKE UP EVENTS
33 PWRBTN_OUT# H2 PWR_BTN#
6,33,43 SB_PWRGD H1 PWR_GOOD
+3VS 1 2 SUS_STAT# SUS_STAT# K3
11 SUS_STAT# SUS_STAT#
R388 4.7K_0402_5% SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
SB700 has internal PD SB_TEST0 H3 TEST0

USB 1.1
Y15 F7 USB10_P12 Touch Screen
33 GATEA20 GA20IN/GEVENT0# USB_FSD12P USB10_P12 31
+3VALW 1 2 SB_TEST2 W15 E8 USB10_N12
33 KB_RST# KBRST#/GEVENT1# USB_FSD12N USB10_N12 31
R320 @ 2.2K_0402_5% K4
33 EC_SCI# LPC_PME#/GEVENT3#
1 2 SB_TEST1 K24 H11 USB20_P11
33 EC_SMI# LPC_SMI#/EXTEVNT1# USB_HSD11P USB20_P11 26
R321 @ 2.2K_0402_5% F1 J10 USB20_N11 USB-11 New Card
S3_STATE/GEVENT5# USB_HSD11N USB20_N11 26
1 2 SB_TEST0 J2
R322 @ 2.2K_0402_5% PCIE_WAKE# SYS_RESET#/GPM7# USB20_P10
H6 WAKE#/GEVENT8# USB_HSD10P E11 USB20_P10 26
F2 F11 USB20_N10 USB-10 MiniCard(TV tuner)
BLINK/GPM6# USB_HSD10N USB20_N10 26
H_THERMTRIP# J6
6,33 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
11 NB_PWRGD W14 NB_PWRGD USB_HSD9P A11
USB_HSD9N B11 USB-9 Card Reader(delete)
2 1 EC_RSMRST# PV:delete R381 & R386 D3 RSMRST#
R327 100K_0402_5% C10 USB20_P8
USB_HSD8P USB20_P8 26
D10 USB20_N8 USB-8 WLAN
USB_HSD8N USB20_N8 26
SI2: change from 2.2K to 100K ohm AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 31
AD18 H12 USB20_N7 USB-7 Fingerprint
CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 31
EC_RSMRST# AA19
33 EC_RSMRST# SMARTVOLT1/SATA_IS2#/GPIO4
W17 E12 USB20_P6
CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_P6 31
V17 E14 USB20_N6 USB-6 Bluetooth
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 31
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
2 USB20_P5 2
29 SB_SPKR W21 C12

USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 17
8,9,15,28 SMB_CK_CLK0 SMB_CK_CLK0 AA18 D12 USB20_N5 USB-5 USB Camera
SCL0/GPOC0# USB_HSD5N USB20_N5 17
8,9,15,28 SMB_CK_DAT0 SMB_CK_DAT0 W18
+3VS SMB_CK_CLK1 SDA0/GPOC1# USB20_P4
26 SMB_CK_CLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 31
SMB_CK_DAT1 K2 A12 USB20_N4 USB-4 Left side
26 SMB_CK_DAT1 SDA1/GPOC3# USB_HSD4N USB20_N4 31
AA20 DDC1_SCL/GPIO9

GPIO
R328 1 2 2.2K_0402_5% SMB_CK_CLK0 Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 35
C1 G14 USB20_N3 USB-3 Dock
LLB#/GPIO66 USB_HSD3N USB20_N3 35
R329 1 2 2.2K_0402_5% SMB_CK_DAT0 +3VS 1 2 Y19
R400 @ 4.7K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB20_P2 31
+3VALW USB20_N2
USB_HSD2N H15 USB20_N2 31 USB-2 Left Side
MV: reserve pull high for GPIO5
A13 USB20_P1
USB_HSD1P USB20_P1 31
B13 USB20_N1 USB-1 Right side
USB_HSD1N USB20_N1 31
R331 1 2 2.2K_0402_5% SMB_CK_CLK1
B14 USB20_P0
USB_HSD0P USB20_P0 31
R332 1 2 2.2K_0402_5% SMB_CK_DAT1 B9 A14 USB20_N0 USB-0 Right side
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 31
B8 USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
33 EC_LID_OUT# A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
26 EXP_CPPE# E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
27 CR_CPPE# F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
R333 33_0402_5% 1 2 PAD T45 E4 F19
29 HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
R334 33_0402_5% 1 2 HDA_BITCLK E20
34 HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
R335 33_0402_5% 1 2 M1 E21
34 HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
R336 33_0402_5% 1 2 HDA_SDOUT M2 E19
29 HDA_SDOUT_CODEC AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
29 HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 23
HDA_SDIN1
34 HDA_SDIN1 J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 23 STRAP PIN

HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R337 33_0402_5% 1 2 HDA_SYNC L6 G21
34 HDA_SYNC_MDC AZ_SYNC IMC_GPIO19
R338 33_0402_5% 1 2 M4 D25
3 29 HDA_SYNC_CODEC AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
R339 33_0402_5% HDARST#

INTEGRATED uC
29 HDA_RST#_CODEC 1 2 IMC_GPIO22 C25
R340 33_0402_5% 1 2 C24
34 HDA_RST#_MDC IMC_GPIO23
PAD T41 IMC_GPIO24 B25
IMC_GPIO25 C23
STRAP PIN 23,33 HDARST#
B24
IMC_GPIO26
IMC_GPIO27 B23
IMC_GPIO28 A23
IMC_GPIO29 C22
IMC_GPIO30 A22
IMC_GPIO31 B22
IMC_GPIO32 B21
IMC_GPIO33 A21
H19 IMC_GPIO0 IMC_GPIO34 D20
H20 IMC_GPIO1 IMC_GPIO35 C20
INTEGRATED uC

H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20

F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
IMC_GPIO38 B19
D22 IMC_GPIO4 IMC_GPIO39 A19
E24 IMC_GPIO5 IMC_GPIO40 D18
E25 IMC_GPIO6 IMC_GPIO41 C18
D23 IMC_GPIO7

218S7EALA11FG_BGA528_SB700

SBR1@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 USB/AC97
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 20 of 46
A B C D E
 A B C D E

U15B
1 1

C512 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9 SB700 AA24

24 SATA_TXP0 SATA_TX0P IDE_IORDY
C513 1 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25
24 SATA_TXN0 SATA_TX0N IDE_IRQ
IDE_A0 Y22
24 SATA_RXN0_C AB10 SATA_RX0N IDE_A1 AB23
24 SATA_RXP0_C AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK# AB24 Local Frame Buffer Strapping List
C514 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25 Copy from Becks.
24 SATA_TXP1 SATA_TX1P IDE_DRQ
C515 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
24 SATA_TXN1 SATA_TX1N IDE_IOR#
IDE_IOW# AC24
24 SATA_RXN1_C AD11
AE11
SATA_RX1N IDE_CS1# Y25
Y24
LFB_ID2 LFB_ID1 LFB_ID0
24 SATA_RXP1_C SATA_RX1P IDE_CS3#
C520 1 2 0.01U_0402_25V7K SATA_STX_DRX_P5 AB12 AD24
31 SATA_TXP5 SATA_TX2P IDE_D0/GPIO15
C521 2 0.01U_0402_25V7K SATA_STX_DRX_N5 AC12
31 SATA_TXN5 1 SATA_TX2N IDE_D1/GPIO16 AD23 Hynix32M*16 1 1 0

ATA 66/100/133
IDE_D2/GPIO17 AE22
31 SATA_RXN5_C AE12 SATA_RX2N IDE_D3/GPIO18 AC22
31 SATA_RXP5_C AD12 SATA_RX2P IDE_D4/GPIO19 AD21

C518 1 2 0.01U_0402_25V7K SATA_STX_DRX_P4 AD13 IDE_D5/GPIO20 AE20

AB20
Samsung32M*16 1 0 1
24 SATA_TXP4 SATA_TX3P IDE_D6/GPIO21
C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N4 AE13 AD19
24 SATA_TXN4 SATA_TX3N IDE_D7/GPIO22
AE19

SERIAL ATA
IDE_D8/GPIO23
24 SATA_RXN4_C AB14 SATA_RX3N IDE_D9/GPIO24 AC20
24 SATA_RXP4_C AC14 SATA_RX3P IDE_D10/GPIO25 AD20
IDE_D11/GPIO26 AE21
T24 PAD AE14 AB22
T25 PAD SATA_TX4P IDE_D12/GPIO27
AD14 SATA_TX4N IDE_D13/GPIO28 AD22

T26 PAD AD15

IDE_D14/GPIO29 AE23
AC23
LFB_ID0 to LFB_ID2 got internal PU 10K to S5.
T27 PAD SATA_RX4N IDE_D15/GPIO30
AE15 SATA_RX4P LFB_ID2 R344 1 2@ 1K_0402_5%
2 T18 PAD 2
AB16 SATA_TX5P
T19 PAD AC16 LFB_ID1 R367 1 2@ 1K_0402_5%
SATA_TX5N
SPI_DI/GPIO12 G6
T20 PAD AE16 D2 LFB_ID0 R345 1 2@ 1K_0402_5%
T23 PAD SATA_RX5N SPI_DO/GPIO11
AD16 SATA_RX5P SPI_CLK/GPIO47 D1
F4

SPI ROM
SATA_CAL SPI_HOLD#/GPIO31
2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3
R342 1K_0402_1%
SATA_X1 Y12 U15
SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
SATA_X2 AA12 SATA_X2
+3VS R343 1 2 10K_0402_5% FANOUT0/GPIO3 M8
34 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5 CR_WAKE# 27
+1.2V_HT M7
L54 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5 T31 PAD
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
FANIN1/GPIO51 P8 GSENSOR_LED# 34

SATA PWR
2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL 32
C522 C523 C6
1U_0402_6.3V4Z TEMP_COMM
1U_0402_6.3V4Z TEMPIN0/GPIO61 B6 XMIT_OFF# 26
1 1
TEMPIN1/GPIO62 A6 BT_COMBO_EN# 26
TEMPIN2/GPIO63 A5 <BOM Structure>
B5

HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# 33 CH751H-40PT_SOD323-2
+3VS A4 2 1
VIN0/GPIO53 AC_IN 33,38
L55 B4
VIN1/GPIO54 BT_OFF 31 D41
2 1 +XTLVDD_SATA C4
VIN2/GPIO55 CAM_SHDN# 17
BLM18PG121SN1D_0603 2 1 D4 1 2 +3VALW
VIN3/GPIO56 LFB_ID0 R562 150K_0402_5%
VIN4/GPIO57 D5
C524 C625 D6 LFB_ID1 PV:Add D41 and R562
1U_0402_6.3V4Z @ 0.1U_0402_16V4Z VIN5/GPIO58 LFB_ID2
VIN6/GPIO59 A7
3 1 2 <BOM Structure> 3
VIN7/GPIO60 B7

PV:Reserve for EMI +3VALW

L56
F6 +SB_AVDD 2 1
AVDD BLM18PG121SN1D_0603
1 1
10P_0402_50V8J 2 1 C516 SATA_X1 G7
AVSS C526
1

2.2U_0603_6.3V4Z
Y4 R341 2 2
218S7EALA11FG_BGA528_SB700
25MHZ_20P C525
10M_0402_5% 0.1U_0402_16V4Z
2

SBR1@
2

10P_0402_50V8J 2 1 C517 SATA_X2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 SATA/IDE/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 21 of 46
A B C D E
 A B C D E

U15C U15E
1 2 +1.2VALW
R592 @ 0_0805_5%
SB700 L15 +1.2V_HT_R
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1
M12
1
R593
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 VSS_1
2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
C528 22U_0805_6.3V6M U9 N13 10U_0805_6.3V6M C529 B1

CORE S0
1 C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3 1
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO I/O
C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19
C536 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
C535 1 2 1U_0402_6.3V4Z Y6 T16 0.1U_0402_16V4Z 2 1 C527 U12 K9
C539 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C540 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C541 1 2 0.1U_0402_16V4Z AB5 V14 K16
C542 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 AVSS_SATA_9 VSS_13 L10
No IDE device unmount CAP Y14 AVSS_SATA_10 VSS_14 L11
L60 Y17 L12
+1.2V_CKVDD AVSS_SATA_11 VSS_15
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 2 1 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 0_0603_5% AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
2 1 AA22 L24 AB11 M6

IDE/FLSH I/O

CLKGEN I/O
C543 @ 22U_0805_6.3V6M VDD33_18_3 CKVDD_1.2V_3 C546 @ 1U_0402_6.3V4Z AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 1 2 AB13 AVSS_SATA_15 VSS_19 M10
C544 1 2 @ 1U_0402_6.3V4Z C545 1 2 @ 1U_0402_6.3V4Z AB15 M11
C547 AVSS_SATA_16 VSS_20
1 2 @ 1U_0402_6.3V4Z C548 2 1 @ 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C549 1 2 @ 1U_0402_6.3V4Z C551 2 1 @ 0.1U_0402_16V4Z AC8 M15
C550 @ 10U_0805_10V4Z AVSS_SATA_18 VSS_22
1 2 AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12
VSS_25 N14
+PCIE_VDDR P6
L61 POWER MV:internal CLKGEN no use,cap unmount VSS_26
VSS_27 P9
+1.2V_HT 2 1 VSS_28 P10
0_0805_5% A15 P11
AVSS_USB_1 VSS_29
P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
2 1 P19 +3VALW C14 P15
C552 4.7U_0805_10V6K PCIE_VDDR_2 AVSS_USB_3 VSS_31
P20 PCIE_VDDR_3 D8 AVSS_USB_4 VSS_32 R1
C553 1 2@ 1U_0402_6.3V4Z P21 A17 +S5_3V 1 2 D9 R2

A-LINK I/O
C555 PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
1 2 1U_0402_6.3V4Z R22 PCIE_VDDR_5 S5_3.3V_2 A24 R564 0_0805_5% D11 AVSS_USB_6 VSS_34 R4
C554 1 2 1U_0402_6.3V4Z R24 B17 1 2 D13 R9
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35

GROUND
2 C558 2
1 2 1U_0402_6.3V4Z R25 PCIE_VDDR_7 S5_3.3V_4 J4 22U_0805_6.3V6M C556 D14 AVSS_USB_8 VSS_36 R10

3.3V_S5 I/O
C557 1 2 0.1U_0402_16V4Z J5 1U_0402_6.3V4Z 2 1 C559 D15 R12
C560 S5_3.3V_5 AVSS_USB_9 VSS_37
1 2 0.1U_0402_16V4Z S5_3.3V_6 L1 1U_0402_6.3V4Z 2 1 C561 E15 AVSS_USB_10 VSS_38 R14
L2 1U_0402_6.3V4Z 2 1 C562 F12 T11
+1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z 2 C563 AVSS_USB_11 VSS_39
1 F14 AVSS_USB_12 VSS_40 T12
L63 0.1U_0402_16V4Z 2 1 C564 G9 T14
0.1U_0402_16V4Z 2 C565 AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 1 H9 AVSS_USB_14 VSS_42 U4
0_0805_5% AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 J9 AVSS_USB_16 VSS_44 V6
2 1 AA17 G2 +S5_1.2V L64 0_0603_5% J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O
C566 22U_0805_6.3V6M AC18 G4 J12 AB1
C567 1U_0402_6.3V4Z AVDD_SATA_5 S5_1.2V_2 +1.2VALW 1U_0402_6.3V4Z C569 AVSS_USB_18 VSS_46
1 2 AD17 AVDD_SATA_6 2 1 J14 AVSS_USB_19 VSS_47 AB19
C568 1 2 1U_0402_6.3V4Z AE17 1U_0402_6.3V4Z 2 1 C570 J15 AB25
C571 0.1U_0402_16V4Z AVDD_SATA_7 +1.2_USB L65 0_0603_5% AVSS_USB_20 VSS_48
1 2 K10 AVSS_USB_21 VSS_49 AE1
C572 1 2 0.1U_0402_16V4Z A10 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
10U_0805_10V4Z C573 K15
1U_0402_6.3V4Z 2 C574 AVSS_USB_24
1 PCIE_CK_VSS_9 P23
1U_0402_6.3V4Z 2 1 C575 R16
PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
+AVDD_USB T17
L66 PCIE_CK_VSS_12
PCIE_CK_VSS_13 U18
+3VALW 2 1 A16 AE7 +V5_VREF 1K_0402_5% 2 1 R346 +5VS H18 U20
0_0805_5% AVDDTX_0 V5_VREF D14 PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
C16 J16 +AVDDCK_3.3V 1 2 +3VS J22 V20
C576 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C578 C579 PCIE_CK_VSS_3 PCIE_CK_VSS_16
1 2 D16 AVDDTX_3 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
C577 1 2 10U_0805_10V4Z D17 K17 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z CH751H-40PT_SOD323-2 M16 W19
PLL

C580 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C581 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

C583 0.1U_0402_16V4Z AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
1 2 F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
C582 1 2 0.1U_0402_16V4Z F18 L67
C584 0.1U_0402_16V4Z AVDDRX_2
1 2 G15 AVDDRX_3 2 1 +3VALW F9 AVSSC AVSSCK L17
3 0_0603_5% 3
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C585 218S7EALA11FG_BGA528_SB700

0.1U_0402_16V4Z 2 1 C586
218S7EALA11FG_BGA528_SB700 SBR1@

SBR1@

L68
+AVDDCK_1.2V 2 1 +1.2V_HT
0_0603_5%

2.2U_0603_6.3V4Z 2 1 C587

0.1U_0402_16V4Z 2 1 C588

L69
+AVDDCK_3.3V 2 1 +3VS
0_0603_5%

2.2U_0603_6.3V4Z 2 1 C589

0.1U_0402_16V4Z 2 1 C590

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 22 of 46
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
H,H = Reserved
ENABLED STRAPS
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R355

R356
R347

R348

R349

R350

R351

R352

R353

R354
2

2
@

@
@ @ @ @ @ @ @
19 PCI_CLK2
19 PCI_CLK3 SI2: mount 2.2K
19 PCI_CLK4
19 PCI_CLK5
19,33 CLK_PCI_EC
19,32 CLK_PCI_SIO
19 RTC_CLK
20,33 HDARST#
2 20 GPIO17 2
20 GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R363

R365

R366
R357

R358

R359

R360

R361

R362

R364
2

2
@ @ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

19 PCI_AD28
19 PCI_AD27
19 PCI_AD26
19 PCI_AD25
19 PCI_AD24
19 PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R373

R374

R375

R376

R377

R378
2

2
@ @ @ @ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB700 STRAPS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 23 of 46
A B C D E
 A B C D E

HDD Connector
JP9
+5VS
GND 1
2 SATA_TXP0
A+ SATA_TXP0 21

10U_0805_10V4Z

0.1U_0402_16V4Z
3 SATA_TXN0
A- SATA_TXN0 21
1 1 1 1 4 0.01U_0402_16V7K
C593 GND

C595
1 SATA_RXN0 1
B- 5 2 1 C592 SATA_RXN0_C SATA_RXN0_C 21
C594 C591 6 SATA_RXP0 2 1 C596 SATA_RXP0_C
B+ SATA_RXP0_C 21
7 0.01U_0402_16V7K
2 2 2 2 GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side.
V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10
GND 11
GND 12
GND 13
V5 14
15 +5VS
V5
V5 16
GND 17
Reserved 18
GND 19
V12 20
V12 21
V12 22

SUYIN_127072FR022G210ZR_RV
@

DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA

SUYIN_127043FR022G204ZL_22P_NR

2
2nd HDD Connector-option 2

JP10
+5VS
GND 1
2 SATA_TXP1
A+ SATA_TXP1 21
10U_0805_10V4Z

0.1U_0402_16V4Z

3 SATA_TXN1
A- SATA_TXN1 21
1 1 1 1 4 0.01U_0402_16V7K
GND
C601

C604

5 SATA_RXN1 2 1 C605 SATA_RXN1_C

B- SATA_RXN1_C 21
C602 C603 6 SATA_RXP1 2 1 C606 SATA_RXP1_C
B+ SATA_RXP1_C 21
7 0.01U_0402_16V7K
2 2 2 2 GND
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side.
V33 8 +3VS
V33 9
Pleace near HD CONN (JP23) V33 10
GND 11
GND 12
GND 13
V5 14
15 +5VS
V5
V5 16
GND 17
Reserved 18
GND 19
V12 20
V12 21
V12 22

SUYIN_127072FR022G210ZR_RV
@
3 3
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

CD-ROM Connector
+5VS JP11

Placea caps. near ODD CONN. GND 1

SATA_TXP4
A+ 2 SATA_TXP4 21
3 SATA_TXN4
A- SATA_TXN4 21
4 0.01U_0402_16V7K
GND SATA_RXN4
B- 5 2 1 C612 SATA_RXN4_C SATA_RXN4_C 21
6 SATA_RXP4 2 1 C611 SATA_RXP4_C
B+ SATA_RXP4_C 21
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

7 0.01U_0402_16V7K
GND
1 1 1 1
Near CONN side.
C613

C614

C615

C616 8
10U_0805_10V4Z DP
V5 9
2 2 2 2
V5 10 +5VS
MD 11
15 GND GND 12
14 GND GND 13

4 SUYIN_127382FR013G509ZR 4
@

SI: Update ODD footprint to fix pin reverse issue

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 24 of 46
A B C D E
 A B C D E

1 2 +3V_LAN
R382 3.6K_0402_5%

U17 SI2: remove U17 & C618 ,use LAN internal EEPROM
LAN_DO 4 5 2
LAN_DI DO GND C618
3 DI NC 6
LAN_SK_LAN_LINK# 2 7
LAN_CS SK NC
1 CS VCC 8 +3V_LAN
1
@ 0.1U_0402_16V4Z
@ AT93C46-10SI-2.7_SO8

2 1
R712 10K_0402_5%

1 1

Place Close to Chip U18

C485 2 0.1U_0402_16V7K
1 PCIE_PTX_IRX_P3 20 33 LAN_DO
10 PCIE_PTX_C_IRX_P3 HSOP LED3/EEDO
34 LAN_DI
C488 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 LED2/EEDI/AUX LAN_SK_LAN_LINK# +LAN_VDD12
10 PCIE_PTX_C_IRX_N3 1 21 HSON LED1/EESK 35 Close to Pin48 Close to Pin10,13,30,36
32 LAN_CS
EECS
10 PCIE_ITX_C_PRX_P3 15 HSIP
38 LAN_ACTIVITY#
LED0
10 PCIE_ITX_C_PRX_N3 16 HSIN 2 2 2 2
RTL8102EL 2 LAN_MDI0+ VCTRL12 0.1U_0402_16V4Z C637 C638 C639 C640
MDIP0 LAN_MDI0-
15 CLK_PCIE_LAN 17 REFCLK_P MDIN0 3
18 5 LAN_MDI1+ 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
15 CLK_PCIE_LAN# REFCLK_M MDIP1 1 1 1 1
6 LAN_MDI1- C641
MDIN1 C642
15 CLKREQ_LAN 25 CLKREQB NC 8
NC 9
2 1
11,14,19,26,27,32,33 PLT_RST# 27 PERSTB NC 11
12 @ 10U_0805_10V4Z
NC
R408 1 2 2.49K_0402_1% 46 4
RSET NC
26 48 VCTRL12
20,26 LAN_PCIE_WAKE# LANWAKEB VCTRL12A
ISOLATEB 28 ISOLATEB
VDDTX 19 +EVDD12
+3VS LAN_X1 41 30
CKXTAL1 DVDD12 +LAN_VDD12
LAN_X2 42 36
CKXTAL2 DVDD12
DVDD12 13
1

DVDD12 10
R384
2 1K_0402_1% 2
NC 39

23 44
2

ISOLATEB NC NC
24 NC VCTRL12D 45 +LAN_VDD12 Close to Pin19
7 29 +EVDD12
GND VDD33 +3V_LAN
14 GND VDD33 37
R401 31
15K_0402_5% GND
47 GND AVDD33 1
NC 40
22 GNDTX NC 43 2 2
C636
C644
RTL8102EL-GR_LQFP48_7X7 1U_0402_6.3V4Z 0.1U_0402_16V4Z
1 1
Close to Pin1,37,29
Close to Pin45 +3V_LAN

+LAN_VDD12
2 2 2
C620 C621 C622

2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1
C650 C645
0.1U_0402_16V4Z @ 10U_0805_10V4Z
1 2

3 3

PJP6 LAN Conn.

1 2
+3VALW JP12
PAD-OPEN 4x4m 13
+3V_LAN Yellow LED+
40 mils LAN_ACTIVITY# R391 2 1 300_0402_5% 14 Yellow LED-
S

3 1 +3V_LAN 1 SHLD1 16
8 PR4-
2

2 PV:Add ESD diode for EMI request C656 9

R713 @68P_0402_50V8K DETECT PIN1
G

7
2

@ 100K_0402_5% C707 Q61 2 PR4+

SI2301BDS-T1-E3_SOT23-3 RJ45_MIDI1- 6
1 LAN_ACTIVITY# PR2-
1

33 LANPWR 1 2 5 PR3-
Y1 R715 10K_0402_5% 0.1U_0402_16V4Z LAN_SK_LAN_LINK#
LAN_X1 2 1LAN_X2 4 PR3+
SI2: remove 100K ohm ,use EC pull high

2
25MHZ_20P RJ45_MIDI1+ 3
D39 PR2+
1 1
C255 C254 PSOT24C_SOT23-3 RJ45_MIDI0- 2 PR1-
@ DETCET PIN2 10
27P_0402_50V8J 27P_0402_50V8J 2 RJ45_MIDI0+ 1
2 2 PR1+
1 SHLD1 15
C657 11
@68P_0402_50V8K +3V_LAN Green LED+
LAN_SK_LAN_LINK# 1 R395 2 1 300_0402_5% 12 Green LED-
U19 @ FOX_JM36113-P1122-7F
LANGND
LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI0+ 35 1 1
4 LAN_MDI0- TD+ TX+ RJ45_MIDI0- C661 C662 4
2 TD- TX- 15 RJ45_MIDI0- 35
2 1 3 14 R394
C659 0.01U_0402_16V7K CT CT C600
4 NC NC 13 2 1 0.01U_0603_100V4Z 1 2 75_0402_1% 0.1U_0402_16V4Z 4.7U_0805_10V4Z
C610 2 2
5 NC NC 12 2 1 0.01U_0603_100V4Z 1 2 75_0402_1% RJ45_GND 1 2
2 1 6 11 R396 C658 1000P_1808_3KV7K
C660 0.01U_0402_16V7K LAN_MDI1+ CT CT RJ45_MIDI1+
7 RD+ RX+ 10 RJ45_MIDI1+ 35
LAN_MDI1- 8 9 RJ45_MIDI1- RJ45_MIDI1- 35
RD- RX-

NS681680
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8111C/8102E 10/100/1000 LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 25 of 46
A B C D E
 A B C D E

Mini Card---TV tuner

SI2: chagne power plan from +3VALW to +3VS_TV
+1.5VS_TV
+3VS_TV +3VS_TV
0.01U_0402_16V7K 4.7U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
1 1 C667 C668 C669 C670
C665 C666
2 2 2 2
2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z
1 1
@

New Card SI: Exchange TV & WLAN

minicard location
@
JP14
1 1 2 2 +3VS_TV
+1.5VS 3 4
C681 U21 3 4
5 5 6 6 +1.5VS_TV
2 1 0.1U_0402_16V4Z 12 1.5Vin 1.5Vout 11 +1.5VS_PEC 15 CLKREQ_MCARD1# 7 7 8 8
14 1.5Vin 1.5Vout 13 9 9 10 10
+3VS 11 12
15 CLK_PCIE_MCARD1# 11 12
C679 13 14
15 CLK_PCIE_MCARD1 13 14
2 1 0.1U_0402_16V4Z 2 3.3Vin 3.3Vout 3 +3VS_PEC 15 15 16 16
4 3.3Vin 3.3Vout 5 17 17 18 18 SI2: chagne power plan from +3VALW to +3VS_TV
2 1 0.1U_0402_16V4Z 19 19 20 20
+3VALW C680 17 15 +3V_PEC 21 22 PLT_RST#
AUX_IN AUX_OUT 21 22
10 PCIE_PTX_C_IRX_N5 23 23 24 24 +3VS_TV
PLT_RST# 6 19 10 PCIE_PTX_C_IRX_P5 25 26
11,14,19,25,27,32,33 PLT_RST# SYSRST# OC# 25 26
27 27 28 28 +1.5VS_TV
20 8 PERST# 29 30 SMB_CK_CLK1
33,36,40 SYSON SHDN# PERST# 29 30
31 32 SMB_CK_DAT1
10 PCIE_ITX_C_PRX_N5 31 32
29,33,36,38,41 SUSP# 1 STBY# NC 16 10 PCIE_ITX_C_PRX_P5 33 33 34 34
35 35 36 36 USB20_N10 20
+3VALW 2 1@ 100K_0402_5% 10 CPPE# GND 7 37 37 38 38 USB20_P10 20
R412 +3VS_TV 39 40
39 40
20 EXP_CPPE# 9 CPUSB# 41 41 42 42
THERMAL_PAD 21 43 43 44 44
18 45 46
Power Switch internal pull high RCLKEN
47
45 46
48 +1.5VS_TV
47 48
R5538D001-TR-F_QFN20_4X4~D 49 49 50 50
51 51 52 52 +3VS_TV
2 2
USE TI TPS2231MRGPR 53 GND1GND2 54

MOLEX 67910-0002 52P

+1.5VS R406 1 2 0_1206_5% +1.5VS_TV

+3VS R407 1 2 0_1206_5% +3VS_TV

Mini-Express Card---WLAN
+3VS_WLAN +1.5VS_WLAN +3VALW

0.01U_0402_16V7K 4.7U_0805_10V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z

Near to Express Card slot. C785

1
C786
1
C787
1 1
C781 C782
1
C783
1 1
C784 0.1U_0402_16V4Z
+3VS_PEC
2 2 2 2 2 2 2
JP16 4.7U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 GND 1 1
3 3
20 USB20_N11 2 USB_D- 21 BT_COMBO_EN# 1 2 CH_CLK
3 C677 C678 R547 0_0402_5%
20 USB20_P11 USB_D+

2
EXP_CPPE# 4 CPUSB# 2 2 R553
5 RSV
6 0.1U_0402_16V4Z 4.7K_0402_5% +1.5VS_WLAN +3VS_WLAN
RSV @ +3VS
20 SMB_CK_CLK1 7 SMB_CLK
8 R556 ＠ 0_0402_5% JP26
20 SMB_CK_DAT1

1
SMB_DATA +1.5VS_PEC MINI_PCIE_WAKE# 1 L78
+1.5VS_PEC 9 +1.5V 2 1 1 2 2 1 2 0_1206_5%
+1.5VS_PEC 10 +1.5V 31 CH_DATA 3 3 4 4
MINI_PCIE_WAKE# 11 4.7U_0805_10V4Z CH_CLK 5 5 6
20,25 MINI_PCIE_WAKE# WAKE# 31 CH_CLK 6 +1.5VS
+3V_PEC 12 +3.3VAUX 1 1 15 CLKREQ_MCARD2# 7 7 8 8
PERST# 13 9 9 10
PERST# C683 C682 10 L79
+3VS_PEC 14 +3.3V 15 CLK_PCIE_MCARD2# 11 11 12 12 1 2 0_1206_5%
15 +3.3V 15 CLK_PCIE_MCARD2 13 13 14 14
2 2
15 CLKREQ_NCARD# 16 CLKREQ# 15 15 16 16
EXP_CPPE# 17 17 17 18
CPPE# 0.1U_0402_16V4Z 18
15 CLK_PCIE_NCARD# 18 REFCLK- 19 19 20 20 XMIT_OFF# 21
19 21 21 22 PLT_RST#
15 CLK_PCIE_NCARD REFCLK+ 22
20 10 PCIE_PTX_C_IRX_N2 23 23 24 +3VAUX R634 1 2 @ 0_0603_5% +3VALW
GND 24 R635 1 0_0603_5%
10 PCIE_PTX_C_IRX_N0 21 PERn0 10 PCIE_PTX_C_IRX_P2 25 25 26 26 2 +3VS
10 PCIE_PTX_C_IRX_P0 22 PERp0 27 27 28 28
23 +3V_PEC 29 29 30 SMB_CK_CLK1
GND 30 SMB_CK_DAT1
10 PCIE_ITX_C_PRX_N0 24 PETn0 10 PCIE_ITX_C_PRX_N2 31 31 32 32
10 PCIE_ITX_C_PRX_P0 25 4.7U_0805_10V4Z 33 33 34
PETp0 10 PCIE_ITX_C_PRX_P2 34
26 GND 35 35 36 36 USB20_N8 20
1 1 37 37 38 38 USB20_P8 20
27 GND1 SHIELD 29 +3VS_WLAN 39 39 40 40
28 30 C684 C685 41 41 42
GND2 SHIELD 42
43 43 44 44 WL_LED# 34
SANTA_131851-A_LT 2 2
45 45 46 46
0.1U_0402_16V4Z 47 47 48
48
@ 49 49 50 50
4 4
51 51 52 52 SI: Exchange TV & WLAN
53 GND1GND2 54 minicard location
MOLEX 67910-0002 52P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Mini-PCI/Express Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 26 of 46
A B C D E
 A B C D E

SI:Per ME request change Card Reader Connector

JP21 to new one JP21
+VCC_4IN1 3 XD-VCC SD-VCC 21 +VCC_4IN1
MS-VCC 28
+VCC_4IN1 XD_SD_MS_D0 32
XD_SD_MS_D1 XD-D0 SDCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
10K_0402_5% R45 XD_SD_MS_D2 9 14 XD_SD_MS_D0
XD-D2 SD-DAT0
1 2 XDWP#_SDWP# XD_SD_MS_D3 8 XD-D3 SD-DAT1 12 XD_SD_MS_D1
10K_0402_5% XD_SD_D4 7 30 XD_SD_MS_D2 SDCLK 1 2 1 2
XD_RB# XD_SD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
1 2 6 XD-D5 SD-DAT3 29
XD_SD_D6 5 27 XD_SD_D4 R413 C902
R106 XD_SD_D7 XD-D6 SD-DAT4 XD_SD_D5 @ 100_0402_5% @ 100P_0402_25V8K
4 XD-D7 SD-DAT5 23
18 XD_SD_D6
1 +3VS SDCMD_MSBS_XDWE# 34 SD-DAT6 XD_SD_D7 1
XD-WE SD-DAT7 16
XDWP#_SDWP# 33 25 SDCMD_MSBS_XDWE#
XD_CLE XD_ALE XD-WP SD-CMD XDCD0#_SDCD#
2 1 SI:Per Jmicro request change 35 XD-ALE SD-CD-SW 1
10K_0402_5% R405 R405 & R122 from 200K to 10K XD_CD# 40
XD_ALE XD_RB# XD-CD XDWP#_SDWP#
2 1 39 XD-R/B SD-WP-SW 2
10K_0402_5% R122 XD_RE# 38
XDCE# XD-RE MSCLK
37 XD-CE 1 2 1 2
2 1 XD_RE# XD_CLE 36 26 MSCLK
200K_0402_5% R86 XD-CLE MS-SCLK XD_SD_MS_D0 R410 C900
MS-DATA0 17
2 1 2 1 XDCE# 11 15 XD_SD_MS_D1 @ 100_0402_5% @ 100P_0402_25V8K
7IN1 GND MS-DATA1 XD_SD_MS_D2
31 7IN1 GND MS-DATA2 19
C901 R411 24 XD_SD_MS_D3
100P_0402_25V8K @ 100_0402_5% @ MS-DATA3 XDCD1#_MSCD#
MS-INS 22
13 SDCMD_MSBS_XDWE#
MS-BS
41 7IN1 GND
42 7IN1 GND +1.8VS_OUT +1.8VS
TAITW_R015-B10-LM R387
+3VS 0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
@ 1 1 1 1
@ 0_0603_5%
1

C892 C688 C687 C893

R126 SI:Use build in Regulator
2 2 2 2
10K_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z Chip unmount R387
2 2

+3VS
G

Q54 2 1
1 3 CPPE# 0.1U_0402_16V4Z C695
20 CR_CPPE# Power Circuit
D

2 2N7002_SOT23-3 U23 2
+3VS
1 1
0_0402_5% 3 5
15 CLK_PCIE_MCARD0# APCLKN APVDD
21 CR_WAKE# 1 2 XDCD0#_SDCD# 4 10 C691 C692 D40
15 CLK_PCIE_MCARD0 APCLKP APV18
R397 30 XDCD1#_MSCD# 2
TAV33 2 2 XD_CD#
10 PCIE_ITX_C_PRX_N1 9 APRXN 1 1
8 19 0.1U_0402_16V4Z 0.1U_0402_16V4Z XDCD0#_SDCD# 3
10 PCIE_ITX_C_PRX_P1 APRXP DV33 C696
DV33 20
10 PCIE_PTX_C_IRX_N1 C693 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N1 11 44 DAN202U_SC70 270P_0402_50V7K
C697 1 0.1U_0402_16V7K PCIE_PTX_IRX_P1 APTXN DV33 2
10 PCIE_PTX_C_IRX_P1 2 12 APTXP DV18 18 +1.8VS_OUT
DV18 37 1 1
SI:Per Jmicro request change 2 1 7 APREXT
R114 from 10K to 8.2K 8.2K_0402_5% R114 48 XD_SD_MS_D0 C686 C690
MDIO0 XD_SD_MS_D1 0.1U_0402_16V4Z
MDIO1 47
XD_SD_MS_D2 2 2
+3VS 1 2 38 PCIES_EN MDIO2 46
10K_0402_5% R409 39 45 XD_SD_MS_D3
PCIES JMB385 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# 0.1U_0402_16V4Z
42 SDCLK_MSCLK_XDCE#
MDIO5 XDWP#_SDWP#
MDIO6 41
+5VS XD_CLE
SI:Use build in Regulator MDIO7 40
29 XD_SD_D4 SDCLK_MSCLK_XDCE# 2 1 SDCLK
MDIO8
Chip mount R383,C689,C694 11,14,19,25,26,32,33 PLT_RST# 1 XRSTN MDIO9 28 XD_SD_D5 22_0402_5% 2 1 R457 MSCLK
1

2 27 XD_SD_D6 22_0402_5% 2 1 R456 XDCE#

R370 XTEST MDIO10 XD_SD_D7 22_0402_5% R455
MDIO11 26
+VCC_OUT +VCC_4IN1 470_0402_5% 25 XD_RE#
CPPE# MDIO12 XD_RB#
13 SEEDAT MDIO13 23
R383 14 22 XD_ALE
2 2

SEECLK MDIO14
1 2
NC 34
0_0603_5% 1 1 D5 XDCD1#_MSCD# 15 35
XDCD0#_SDCD# CR1_CD1N NC
HT-F196BP5_WHITE 16 CR1_CD0N NC 36
C689 C694
3 10U_0805_10V4Z 0.1U_0402_16V4Z 3
APGND 6
2 2
+VCC_OUT 17
1

CR1_PCTLN
GND 24
GND 31
1

+3VS D Q53 CR_LED# 21 CR1_LEDN GND 32

2 CR_LED# 33
4.7K_0402_5% R121 G GND
2

1 2XDCD0#_SDCD# S 2N7002_SOT23-3
3

R113
4.7K_0402_5% R111 4.7K_0402_5% JMB385-LGEZ0A_LQFP48_7X7
1 2 XDCD1#_MSCD#
SI: Use 0740 date code chip
1

SI:Use new chip ,change to

High active control
SI:Use build in Regulator
Chip unmount U22 and relation parts

+VCC_4IN1
+VCC_OUT
40mil
+3VS U22

3 IN OUT 1
4 4
4 EN OUT 5
1
1

C895 2 1
GND
@ 0.1U_0402_16V4Z @ G5250C2T1U_SOT23-5 C896
2
2 150K_0402_5%
2

@ 1U_0603_10V4Z R123
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

reserved power circuit THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
JMB380/385 card reader/1394
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 27 of 46
A B C D E
 5 4 3 2 1

D D

ACCELEROMETER

SMB_CK_CLK0 8,9,15,20

14
U66

SCL / SPC
+3VS

+3VS 1 Vdd_IO SDA / SDI / SDO 13 SMB_CK_DAT0 8,9,15,20

2 GND SDO 12
Pin12(internal pull high ) pull up I2C address :0011101b

10U_0805_6.3V6M
0.1U_0402_16V4Z
3 Reserved Reserved 11

C1030

C1031
1 1 4 10
pull low I2C address:0011100b
GND GND
5 GND INT 2 9
2 2
6 Vdd INT 1 8 ACCEL_INT 19

C C

CS
LIS302DLTR_LGA14_3x5

7
+3VS 2 1
R964 10K_0402_5%

I2C address:0111000Xb
+3VS
U68

VDDIO 9 1 2
C830 @ 0.1U_0402_16V4Z
+3VS 5 CSB VDD 2 +3VS

8,9,15,20 SMB_CK_CLK0 6 SCK INT 4 ACCEL_INT 19

10U_0805_6.3V6M
0.1U_0402_16V4Z
C828

C829
8,9,15,20 SMB_CK_DAT0 8 SDI SDO 7
1 1
B 10 3 B
reserved GND
1 reserved GND 11
2 2

GND 12
@ @

@ BMA150_LGA12

SI: Reserve Bosch solution

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R5C833_1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Consumer Discrete 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 28 of 46
5 4 3 2 1
 A B C D E

CODEC POWER
+3VDD_CODEC +VDDA_CODEC 0212_Change to +5VALW.
R885
+3VS 1 2
+5VALW +VDDA_CODEC

0.1U_0402_16V4Z

0.1U_0402_16V4Z
BLM18BD601SN1D_0603 W=40Mil U32

1U_0603_10V4Z

1U_0603_10V4Z
0.1U_0402_16V4Z
1 1 1
1 1 C728 1 2 1
(4.75V)
IN

2.2U_0805_16V4Z
0.1U_0402_16V4Z
2
OUT 5
1
300mA
2 2 2 GND

C734

C733

C904
2 2

C730

C731

C729
26,33,36,38,41 SUSP# 3 SHDN BYP 4
1 G9191-475T1U_SOT23-5 1 2 1
C732

0.1U_0402_16V4Z
2

U27

+3VDD_CODEC 9 DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 47 EAPD_CODEC 33

1 DVDD_CORE VOL_UP/DMIC_0/GPIO 1 2 DMIC_DAT 17

VOL_DN/DMIC_1/GPIO 2 4
+VDDA_CODEC 25 AVDD1*
GPIO 3 30
38 AVDD2**
VREFOUT-E / GPIO 4 31

+3VDD_CODEC 3 DVDD_IO GPIO 5 43

32 MONO_OUT GPIO 6 44

45 SPDIF_OUT
SPDIF OUT1 / GPIO 7 SPDIF_OUT 35
HDA_BITCLK_CODEC 6
20 HDA_BITCLK_CODEC BITCLK
SPDIF OUT0 48 SI2: change to SPDIF to pin 45
20 HDA_SDOUT_CODEC 5 SDO
R522 1 2 33_0402_5% 8
20 HDA_SDIN0 SDI_CODEC
VREFOUT-B 28 +VREFOUT_B 30
20 HDA_SYNC_CODEC 10 SYNC
2 VREFOUT-C 29 should be 10K for int MIC 2
PV: add bead for EMI 20 HDA_RST#_CODEC 11 RESET# 5.1K_0402_1% 2 1 R548 +VDDA_CODEC
2 1 1 2 20K_0402_1% 2 1 R569 EXTMIC_DET# 30
17 DMIC_CLK
L58FBMA-L10-160808-301LMT_0603 R230 22_0402_5% 13 SENSEA# 39.2K_0402_1% 2 1 R571 JACK_DET# 30,35
R537 SENSE_A @ 10K_0402_1% 2 R570
33 EC_BEEP 1 2 2 1 46 DMIC_CLK 1 INTMIC_DET# 30
47K_0402_5% C913 1U_0603_10V4Z 0.1U_0402_16V4Z 2 1 C951
R524 1 2 1 2 MONO_INR 33 41 HP_OUTR
20 SB_SPKR CAP2 PORTA_R HP_OUTR 30
47K_0402_5% C955 0.1U_0402_16V4Z HP Jack & Dock
12 39 HP_OUTL
PCBEEP PORTA_L HP_OUTL 30
R523 1 2 10K_0402_5%
1U_0603_10V4Z
C956 1 2 0.1U_0402_16V4Z 22 MIC_EXT_R C908 1 2
PORTB_R MIC_EXTR 30
R584 1
40 NC / OTP MIC_EXT_L
Jack MIC
+VDDA_CODEC 2 5.1K_0402_1% PORTB_L 21 C907 1 2 MIC_EXTL 30
35 SENSE_B# R916 1 2 39.2K_0402_1% SENSEB# 34 SENSE_B / NC 1U_0603_10V4Z
1
C979 37 24 MIC_IN_R
NC PORTC_R MIC_IN_R 30
0.1U_0402_16V4Z MIC_IN_L
Internal MIC
18 NC PORTC_L 23 MIC_IN_L 30
2
19 NC
36 LINE_OUT_R
PORTD_R LINE_OUT_R 30
HDA_BITCLK_CODEC 20 Internal SPKR.
NC LINE_OUT_L
PORTD_L 35 LINE_OUT_L 30
1

10U_0805_10V4Z C972 1U_0603_10V6K

R525 C744 1 2 +VC_REFA 27 15 DOCK_MICR 1 2 1 2
VREFFILT PORTE_R DOCK_MIC_R 35
@ 47_0402_5% R943 10K_0402_5% DOCK MIC
26 14 DOCK_MICL 1 2 1 2
AVSS1* PORTE_L DOCK_MIC_L 35
R944 10K_0402_5%
2

1
1 42 C973 1U_0603_10V6K
AVSS2** R910 R911
PORTF_R 17
3 C745 3
7 DVSS**
@ 33P_0402_50V8K 16 1.21K_0402_1% 1.21K_0402_1%
2 PORTF_L

2
92HD71B7X5NLGXA1X8_QFN48_7X7 SI2: Use new version Codec 1/10*Vin
need close to Codec

C746
1 2
@ 1000P_0402_25V8J
SENSE A SENSE B C747
1 2
@ 1000P_0402_25V8J
Port Resistor Port Resistor C748
1 2
@ 1000P_0402_25V8J
A 39.2K E 39.2K HP_DET# MIC_DET PORT-A
C749
1 2
LINEOUT <Earphone OUT> MIC EQ
@ 1000P_0402_25V8J 0(LOW) 0(LOW) OFF ON ON Disable
B 20K F 20K
4
0(LOW) NC OFF ON OFF Disable 4
R195 1 2 0_1206_5%
NC 0(LOW) ON OFF ON Enable
C 10K G 10K R198 NC NC ON OFF OFF Enable
1 2 GNDA 30,35
@ 0_0805_5%
D 5.11K H 5.11K
GND GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title
0312_Mount C379~383, R313. Audio Codec-IDT9271B7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 29 of 46
A B C D E
 A B C D E

JP17
MIC_EXTR 1
+5VAMP +5VS MIC_EXTL 1
SI2:change from 12.7K to 7.5K 2 2
1 U28 R594 1
3 3
EC_MUTE# 14 19 1 2 HP_OUT_R 4
33 EC_MUTE# RS/D RVDD 0_1206_5% HP_OUT_L 4
5 5
9 LS/D LVDD 7 6 6
EXTMIC_DET# 7
29 EXTMIC_DET# 7
HP_DET# 8 8

10U_0805_10V4Z

10U_0805_10V4Z
1 2 1 R701 2 16 1 SPKR+ 9
0.1U_0402_16V7K C770 7.5K_0402_1% RIN+ ROUT+ C766 C767 9
10 10
1 2 1 R702 2 17 3 SPKR- CIR_IN 11
29 LINE_OUT_R RIN- ROUT- 33,35 CIR_IN 11
0.1U_0402_16V7K C775 7.5K_0402_1% +5VL 12 12
13 13
1 2 1 R703 2 12 4 SPKL+ 14
0.1U_0402_16V7K C776 7.5K_0402_1% LIN+ LOUT+ 14
1 2 1 R704 2 13 6 SPKL- ACES_87213-1400G
29 LINE_OUT_L 0.1U_0402_16V7K C817 7.5K_0402_1% LIN- LOUT-
@
Keep 10 mil width
High Pass Freq: 125Hz 15 RBYPASS
NC 20
11 +3VALW
1 LBYPASS
1 NC 18
JACK_DET# 29,35

2
C818 2 10
2 C765 GND NC R46

3
2 10K_0402_5%
5 GND NC 8
B+
1U_0603_10V4Z 21

1
1U_0603_10V4Z THERMAL_PAD
5

1
SI2:change from 10u to 1u for Q148B
PA PA sound issue TPA6020A2RGWR_QFN20_5x5 R871

4
2N7002DW-7-F_SOT363-6
330K_0402_5%

2
2 2

+3VALW 0.01U_0402_25V7K

1
Q21 D
1

2
2
R47 2N7002_SOT23-3 G
R909 0_0402_5% 10K_0402_5% S C854 PV:change cap form 100uF to 150uF

3
2
29 +VREFOUT_B 2 1 1 2

6
SI2: Add cap & 44.2 ohm for dock

1
1

C742 1U_0603_10V4Z
R907 R908

2
4.7K_0402_5% 4.7K_0402_5% HP_DET# 2 Q20A
C945
R602 44.2_0603_1%
2N7002DW-7-F_SOT363-6 DOCK_R

+
29 HP_OUTR 3 4 1 6 1 2 1 2 DOCK_LOUT_R 35
2

1
Q147B Q22A
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 150U_D_6.3VM
SI: change 2n7002 to dual package
MIC_EXTR
29 MIC_EXTR
MIC_EXTL
29 MIC_EXTL

2
C946
R607 44.2_0603_1%
DOCK_L

+
29 HP_OUTL 3 4 1 6 1 2 1 2 DOCK_LOUT_L 35
Q23B Q23A
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 150U_D_6.3VM

SI: change 2n7002 to dual package

HP OUT For Docking
PV:change cap form 100uF to 150uF
3 HP_OUT_R 3

+
29 HP_OUTR 1 2
+3VS C940 150U_D_6.3VM
Analog MIC 2 HP_OUT_L

+
29 HP_OUTL 1
2

@ R906 0_0402_5% C941 150U_D_6.3VM

+VDDA_CODEC 2 1 1 2 R555
@ 10K_0402_5%
1

C743 1U_0603_10V4Z @
R904 R905 PV:change cap form 100uF to 150uF
1

@ 4.7K_0402_5% 4.7K_0402_5%
@
2

JP20
@ 1U_0603_10V6K 1
C970 MICIN_L 1
29 MIC_IN_L 1 2 2 2
1 2 MICIN_R 3
29 MIC_IN_R
C971 @ 1U_0603_10V6K 4
3
4 SP02000D000 S W-CONN ACES 85204-04001 4P P1.25 SPEAKER
+3VS 2 1 JP15
33 ANA_MIC_DET R956@ 10K_0402_5% 5 SPKL+ 1
GND1 SPKL- 1
6 GND2 2 2
1

D Q27 SPKR+ 3 3
2 ACES_88231-04001 SPKR- 4
@ 2N7002_SOT23-3 G @ 4

29 INTMIC_DET# S 5
3

GND1

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
6 GND2
1

D Q28 1 1 1 1
1

2 ACES_88231-04001

C760

C761

C762

C763
@ 2N7002_SOT23-3 G @
S R957
3

@ 100K_0402_5% 2 2 2 2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 30 of 46
A B C D E
 A B C D E

Left side USB CONNECTOR 0 Left side ESATA/USB combination Connector

+5VALW +USB_VCCA
L46 +USB_VCCA JP27 +USB_VCCA
U40
1 8 W=100mils 1 2 1 WCM-2012-900T_0805 JP28
GND OUT 20 USB20_N4 1 2 USB20_N4_R VCC USB
2 IN OUT 7 2 D- 20 USB20_N2 1 1 2 2 1 B_VCC

1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z
3 6 1 USB20_P4_R 3 USB20_N2_R 2
IN OUT D+ USB20_P2_R B_D-
1 4 EN# OC# 5 1 1 20 USB20_P4 4 4 3 3 4 GND 3 B_D+

C789
+

C790

C791
C788 9 4 3 4
THERMAL_PAD WCM-2012-900T_0805 20 USB20_P2 4 3 B_GND
5 GND
1 4.7U_0805_10V4Z TPS2061IDGN_MSOP8~N 6 L51 5 1
2 2 2 2 GND SATA_TXP5 GND
7 GND 21 SATA_TXP5 6 A+
8 SATA_TXN5 7 ESATA
D8 GND 21 SATA_TXN5 A-
8 GND SHIELD 12
+5VALW 4 2 USB20_P4_R SUYIN_020173MR004S50TZL_4P-T C792 2 1 0.01U_0402_16V7K SATA_RXN5 9 13
VIN IO1 21 SATA_RXN5_C B- SHIELD
USB_EN# C793 2 1 0.01U_0402_16V7K SATA_RXP5 10 14
21 SATA_RXP5_C B+ SHIELD
USB20_N4_R 3 IO2 GND 1 SI2: change new Connector 11 GND SHIELD 15
@
@ PRTR5V0U2X_SOT143-4 TYCO_1759576-1

@
SI: change new footprint

D11 D9

+5VALW 4 2 SATA_TXP5 +5VALW 4 2 USB20_P2_R

VIN IO1 VIN IO1
SATA_TXN5 3 1 USB20_N2_R3 1
IO2 GND IO2 GND
@ PRTR5V0U2X_SOT143-4 @ PRTR5V0U2X_SOT143-4

USB Board Conn Touch screen D12

4 2 SATA_RXN5
SI: new add for ESD
+5VALW VIN IO1
JP47
+5VALW 1 JP18 +5VS SATA_RXP5 3 1
1 IO2 GND
2 2 1 1
3 2 @ PRTR5V0U2X_SOT143-4
3 2 USB10_N12 20
33 USB_EN# 4 4 3 3 USB10_P12 20
2 2
20 USB20_N0 5 5 4 4
20 USB20_P0 6 6 5 5
7 7 GND1 6
20 USB20_N1 8 8 GND2 7
20 USB20_P1 9 9
10 ACES_88266-05001
10

@
11 GND1
12 GND2
ACES_87213-1000G

@
ACES_87213-0800G
BT Connector
10 GND 8 8 +3VAUX_BT
7 7
6 USB20_P6
6 USB20_P6 20
5 USB20_N6
3 5 USB20_N6 20 3
4 4 BT_LED 34
3 @ R517 1 2 1K_0402_5%
3 @ R518 1 1K_0402_5% CH_DATA 26
1 2 2 2 2 CH_CLK 26
@ R622 0_0603_5% 9 1
+3VALW Q31 +3VS GND 1
JP32
0612 no install
D16
S

+3VS_FB
D

3 1 1 2
@ SI2301BDS_SOT23 1 R581 0_0603_5% +5VALW 4 2 USB20_P6
C832 VIN IO1
0.1U_0402_16V4Z USB20_N6
G

3 1
2

IO2 GND
33 USB_EN# 2
MV: add PJP10 JP39 SI2: change form @ PRTR5V0U2X_SOT143-4
1
USB20_N7 2
1 +3VALW to +3VS +3VS +3VAUX_BT
20 USB20_N7 2
USB20_P7 3 Q24 SI2301BDS_SOT23
20 USB20_P7 3
4 4 0.1U_0402_16V4Z

D
5 5 3 1
D21 1 2 6 6
7 GND

1
USB20_P7

G
+5VALW 4 2 8 1 2 1 1 1

2
VIN IO1 PAD-OPEN 2x2m GND R519 C799 C800 C801
USB20_N7 3 1 PJP10 ACES_85201-06051 C798 C802
IO2 GND @ 1U_0603_10V4Z 0.1U_0402_16V4Z 100K_0402_5%
PRTR5V0U2X_SOT143-4 2 1 2 2 2

2
0.01U_0402_16V7K 4.7U_0805_10V4Z

PV: Change PN to SC300000K00 for ESD request R520

21 BT_OFF 1 2

10K_0402_5%

4 4
SI: change to 10K ohm to make
sure MOS can turn on

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 31 of 46
A B C D E
 A B C D E

SI2: Change from +3VL to +3VALW and unmount this EEPROM

+3VL

+3VALW +3VALW SPI Flash (8Mb*1) 1 20mils

C484 U29

1
1 8 VCC VSS 4
C803 0.1U_0402_16V4Z
R521 2 SI2: Change from +3VALW to +3VL
3 W
@ 0.1U_0402_16V4Z @ 100K_0402_5%
2 U31 7

2
HOLD
8 VCC A0 1
1 SPI_CS# INT_SPI_CS# +3VL 1
7 WP A1 2 33 SPI_CS# 1 2 1 S
6,33,34,37 SMB_EC_CK1 6 3 R221 0_0402_5%
SCL A2 SPI_CLK_R
6,33,34,37 SMB_EC_DA1 5 SDA GND 4 33 SPI_CLK 1 2 6 C C624
R227 33_0402_5%
@ AT24C16AN-10SI-2.7_SO8 33 EC_SO_SPI_SI 2 1 EC_SO_SPI_SI_R 5 2 EC_SI_SPI_SO_R 2 1 2 1
D Q EC_SI_SPI_SO 33
R229 0_0402_5% R223 0_0402_5%
SST25LF080A_SO8-200mil @ 0.1U_0402_16V4Z
SPI_CLK_R SI2: chagne 0 ohm to 33ohm for EMI

1
R526 2 SI2: Add 22p for EMI
@ 100K_0402_5%

5
C794 U24 R313 @ 100K_0402_5%
R385
22P_0402_50V8J 2 INT_FLASH_EN# 1 2

G Vcc
2
1 INT_SPI_CS# B
1 2 4 Y
1 SPI_CS#
@ 22_0402_5% A
@ NC7SZ32P5X_NL_SC70-5

3
JP50
SPI_CS# 1 2 +3VL
EC_SI_SPI_SO_R 1 2 INT_FLASH_EN#
3 3 4 4
5 6 SPI_CLK_R
21 SB_INT_FLASH_SEL 5 6
7 8 EC_SO_SPI_SI_R
7 8
@ E&T_2941-G08N-00E~D

C:Chg. PN to LTC00000200

2 2

LPC Debug Port

+3VS
JP41
1 1
2 2
3 3
4 4
5 5
6 6 CLK_14M_SIO 15
7 LPC_AD0
7 LPC_AD1
8 8
9 LPC_AD2
9 LPC_AD3
10 10
11 LPC_FRAME#
11 LPC_DRQ1#
12 12
13 PLT_RST#
13 R137 1
14 14 2 @ 0_0402_5%
15 15 CLK_PCI_SIO2 19
16 SIRQ
16
17 17
18 18
19 19
20 20

@ ACES_85201-2005

3 3

LPC Debug Port

H31
+3VALW

6 5 LPC_DRQ1# 19

7 4 PLT_RST#
19,33 SIRQ PLT_RST# 11,14,19,25,26,27,33

LPC_AD3 8 3 LPC_AD2
19,33 LPC_AD3 LPC_AD2 19,33

LPC_AD1 9 2 LPC_AD0
19,33 LPC_AD1 LPC_AD0 19,33

LPC_FRAME# 10 1 CLK_PCI_SIO
19,33 LPC_FRAME# CLK_PCI_SIO 19,23

2
@ DEBUG_PAD R232
22_0402_5%
@

1
2
C486
4 22P_0402_50V8J 4
1
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 32 of 46
A B C D E
 A B C D E

SI2: Change keyboard conn

+3VL_EC

0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K PV: change to BEAD for EMI request KBD CONN
@
1 1 1 1 1
JP33
C805 C806 C807 C808 C809 +3VL +3VL_EC +EC_AVCC
1 KSO17
For EMI
2 2 2 2 2 R527 1 KSO16 KSO17 @ C213 100P_0402_25V8K
2 2 1 2
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 3 KSO15 KSO9 @ C609 1 2 100P_0402_25V8K
FBMA-L11-201209-601LMT_0805 3 KSO10 KSO16 @ C754 100P_0402_25V8K
4 4 1 2
5 KSO11 KSI6 @ C756 1 2 100P_0402_25V8K
5 KSO14 KSO14 @ C757 100P_0402_25V8K
6 6 1 2

111
125
+3VL SI2: Change from +5VL to +3VL KSO13 KSO11 @ C758 100P_0402_25V8K

22
33
96

67
7 7 1 2

9
1 U33 KSO12 KSO10 @ C759 100P_0402_25V8K 1
8 8 1 2
SMB_EC_DA1 R528 1 2 4.7K_0402_5% 9 KSO3 KSO15 @ C764 1 2 100P_0402_25V8K

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R529 BATT_OVP 2 9 KSO6 KSO6
1 2 4.7K_0402_5% 1 10 10 @ C768 1 2 100P_0402_25V8K
100P_0402_50V8J C327 11 KSO8 KSO3 @ C769 1 2 100P_0402_25V8K
+3VS 11 KSO7 KSO12 @ C822 100P_0402_25V8K
12 12 1 2
GATEA20 1 21 INV_PWM 13 KSO4 KSO13 @ C823 1 2 100P_0402_25V8K
20 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 17 13
SMB_EC_DA2 R531 1 2 4.7K_0402_5% KB_RST# 2 23 FAN_PWM 14 KSO2 KSO2 @ C824 1 2 100P_0402_25V8K
20 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM 4 14
SMB_EC_CK2 R532 1 2 4.7K_0402_5% SIRQ 3 26 15 KSI0 KSO4 @ C825 1 2 100P_0402_25V8K
19,32 SIRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP 29 15
LPC_LFRAME# 4 27 ACOFF 16 KSO1 KSO7 @ C826 1 2 100P_0402_25V8K
19,32 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 38 16
C810 R530 19,32 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K 17 KSO5 KSO8 @ C875 1 2 100P_0402_25V8K
LPC_AD2 LAD3 C812 ECAGND 17 KSI3 KSI3 @ C876 100P_0402_25V8K
1 2 1 2 19,32 LPC_AD2 7 LAD2 PWM Output 1 2 18 18 1 2
@ 33_0402_5% 19,32 LPC_AD1 LPC_AD1 8 63 BATT_TEMP 19 KSI2 KSO5 @ C877 1 2 100P_0402_25V8K
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 37 19
@ 15P_0402_50V8J LPC_AD0 BATT_OVP KSO0 KSO1 @ C878 100P_0402_25V8K
19,32 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 37 20 20
KSI5 KSI0 @ C884
1 2
100P_0402_25V8K
ADP_I/AD2/GPIO3A 65 ADP_I 38 21 21 1 2
CLK_PCI_EC 12 AD Input 66 22 KSI4 KSI4 @ C885 1 2 100P_0402_25V8K
19,23 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_ID 37 22
PLT_RST# 13 75 TP_BTN# 23 KSO9 KSI5 @ C886 1 2 100P_0402_25V8K
11,14,19,25,26,27,32 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 TP_BTN# 34 23
+3VL R533 1 2 ECRST# 37 76 24 KSI6 KSO0 @ C887 1 2 100P_0402_25V8K
ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET 30 24
47K_0402_5% EC_SCI# 20 27 25 KSI7 KSI2 @ C888 1 2 100P_0402_25V8K
20 EC_SCI# SCI#/GPIO0E G1 25 KSI1 KSI1 @ C889 100P_0402_25V8K
20,23 HDARST# 38 CLKRUN#/GPIO1D 28 G2 26 26 1 2
68 KSI7 @ C890 1 2 100P_0402_25V8K
DAC_BRIG/DA0/GPIO3C DAC_BRIG 17
2 1 EN_DFAN1/DA1/GPIO3D 70 VCTRL 38
DA Output 71 IREF ACES_85201-26051
IREF/DA2/GPIO3E IREF 38
C811 0.1U_0402_16V4Z KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F AC_SET 38
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI4 59
KSI3/GPIO33
KSI4/GPIO34
PSCLK1/GPIO4A
PSDAT1/GPIO4B 84
EC_MUTE# 30
USB_EN# 31
KB Back Light Conn
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C I2C_INT 34 +5VS_LED
KSI6 61 PS2 Interface 86
+3VALW KSI6/GPIO36 PSDAT2/GPIO4D MUTE_LED 35
SUSP# SYSON KSI7 62 87 TP_CLK JP48
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 34
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 34 1 1
SI2: Change from 10K to 100K KSO1 40 2
KSO1/GPIO21 2
1

2 KSO2 2
41 KSO2/GPIO22 3 3
R536 R539 KSO3 AC_LED#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 AC_LED# 37 PV:Add for AC_LED function 4 4
1

100K_0402_5% 100K_0402_5% KSO4 43 98 DOCK_VOL_UP# 35 5

R538 KSO5 KSO4/GPIO24 SDICLK/GPXOA01 G1
100K_0402_5% KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 DOCK_VOL_DWN# 35 G2 6
45 KSO6/GPIO26 Matrix 109 VGATE 43
2

KSO7 SDIDI/GPXID0 ACES_85201-0405N

46 KSO7/GPIO27 SPI Device Interface
KSO8 47 @
2

KSO9 KSO8/GPIO28
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO 32
KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 32
LID_SW# KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 32
KSO12 51 128
KSO12/GPIO2C SPICS# SPI_CS# 32
KSO13 52
KSO14 KSO13/GPIO2D CIR_IN +3VS
0205_Add Pull down 53 KSO14/GPIO2E 2 1 +5VL
R402 for SUSP#. KSO15 54 73 CIR_IN R554 10K_0402_5%
KSO15/GPIO2F CIR_RX/GPIO40 CIR_IN 30,35
KSO16 81 74 TP_BTN# 1 2
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG R540 10K_0402_5% +5V_TP
82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG 38
BATT_CHGI_LED#/GPIO52 90 STD_ADP 38
91 TP_CLK 1 2
CAPS_LED#/GPIO53 CAPS_LED# 34
SMB_EC_CK1 77 GPIO 92 BAT_LED# R534 10K_0402_5%
6,32,34,37 SMB_EC_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BAT_LED# 34
SMB_EC_DA1 78 93 ON/OFFBTN_LED#
6,32,34,37 SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# 34
SMB_EC_CK2 79 SM Bus 95 SYSON TP_DATA 1 2
6 SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 26,36,40
SMB_EC_DA2 80 121 VR_ON R535 10K_0402_5%
6 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 43
127 ACIN_D
AC_IN/GPIO59
2 1
R541 10K_0402_5% MV: Change from +3VALW to +3VL
SLP_S3# 6 100 EC_RSMRST#
20 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20
SLP_S5# 14 101
20 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 20
EC_SMI# 15 102 1 2 +3VL
20 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 36,39
+3VL LID_SW# 16 103 WL_BLUE_LED# R560 150K_0402_5%
34 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 WL_BLUE_LED# 34
ESB_CLK 17 104 SB_PWRGD D33
ESB_CLK R563 34 ESB_CLK ESB_DAT SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# SB_PWRGD 6,20,43 ACIN_D
1 2 4.7K_0402_5% 34 ESB_DAT 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 17 2 1 AC_IN 21,38
ESB_DAT R576 1 2 4.7K_0402_5% 19 GPIO 106
3 EC_PME#/GPIO0D WL_OFF#/GPXO09 TP_LED# CH751H-40PT_SOD323-2 3
6,20 H_THERMTRIP# 25 EC_THERM#/GPIO11 GPXO10 107 TP_LED# 34
35 CONA# 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108
36 VLDT_EN 29 FANFB2/GPIO15 2 1
E51_TXD 30 C326 100P_0402_50V8J
34,35 DOCK_SLP_BTN# EC_TX/GPIO16
LANPWR 31 110
25 LANPWR EC_RX/GPIO17 PM_SLP_S4#/GPXID1 VFIX_EN 43
34,35 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL 11
R543 34 114 EAPD_CODEC 29
34 DIM_LED PWR_LED#/GPIO19 GPXID3
+3VL 2 1 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 21
116 SUSP#
GPXID5 SUSP# 26,29,36,38,41
4.7K_0402_5% C813 117 PWRBTN_OUT#
GPXID6 PWRBTN_OUT# 20
15P_0402_50V8J 118 2 1
GPXID7 PCI_SERR# 19
1 2 CRY2 122 R231 0_0402_5%
XCLK1
123 XCLK0 V18R 124 2 1
C814 4.7U_0805_10V4Z
Y7
1

AGND

SI: Mount C814 for KB926C

GND
GND
GND
GND
GND

3 4 @
NC OSC R545
2 1 20M_0402_5% KB926QFC0_LQFP128_14X14
EC DEBUG port
11
24
35
94
113

69

NC OSC
2

@ 32.768KHZ_12.5PF_9H03200413
JP34
1 1 2 CRY1 +3VL_EC
1 +5VL
2 LANPWR
2 E51_TXD C815
3
ECAGND

3
1

4 15P_0402_50V8J
4 L80
ACES_85205-0400 +EC_AVCC FBM-11-160808-601-T_0603

L81
2

1 2 1 2
C816 0.1U_0402_16V4Z FBM-11-160808-601-T_0603
4 4

PV: change to BEAD for EMI request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 33 of 46
A B C D E
 A B C D E

MDC 1.5 Conn. CAPS LOCK LED WHITE +5VS_LED

Change type 4/25 D30 R552

33 CAPS_LED# 1 2 1 2

JP25 HT-F196BP5_WHITE 750_0402_5%

1 GND1 RES0 2 +3VS MV: Modify R552 change to 750ohm

HDA_SDOUT_MDC 3 4
20 HDA_SDOUT_MDC

20 HDA_SYNC_MDC HDA_SYNC_MDC
5
7
IAC_SDATA_OUT
GND2
RES1
3.3V 6
8
+3VS POWER LED(Left 1) WHITE +5VALW_LED

IAC_SYNC GND3
20 HDA_SDIN1 1 R495 2 HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10 D27 R549
20 HDA_RST#_MDC 33_0402_5% 11 12 HDA_BITCLK_MDC 20 ON/OFFBTN_LED# 1 2 1 2
1 IAC_RESET# IAC_BITCLK 1
2 1 1 2 HT-F196BP5_WHITE 470_0402_5%
+3VS R496 C777

GND
GND
GND
GND
GND
GND
@ 10_0402_5% @ 10P_0402_25V8K

ACES_88018-124G
Battery Charge LED(Left 2)

13
14
15
16
17
18
+5VALW_LED
1000P_0402_50V7K
C778

C779

0.1U_0402_16V4Z WHITE
1 1 1
Connector for MDC Rev1.5 D28 R550
C780 1 2 1 2
33 BAT_LED#
@4.7U_0805_10V4Z @
2 2 2 HT-F196BP5_WHITE 470_0402_5%

HDD LED(Left 3)
QSMF-C16E_AMBER-WHITE +5VS_LED
+3VS +5VS White

1 2 1 2

1
R551 820_0402_5%
10K_0402_5% R631

3
R577 10K_0402_5% 3 4 1 2 +3VS
Q138B 21 GSENSOR_LED# R559 470_0402_5%
2N7002DW-7-F_SOT363-6

2
5 Amber
WL_BLUE_LED# 33 LED1
MV: Modify R551& R559 to 820 & 470 ohm

4
6
1

D Q138A
2 Q55 2N7002DW-7-F_SOT363-6
2 31 BT_LED 2
G 2N7002_SOT23-3 2
21 SATA_LED#
S
DIM LED
3
1

1
R505 +5VALW_LED +5VS_LED
100K_0402_5% Q32 Q58
SI2301BDS-T1-E3_SOT23-3 SI2301BDS-T1-E3_SOT23-3
2

S
D

D
+5VALW 3 1 +5VS 3 1

1 1

1
C836 C845

G
2

2
D15 R587 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 PV: Add LDO for ENE cap board 10K_0402_5%
26 WL_LED# 2 2
CH751H-40PT_SOD323-2

2
APL5151-33BC-TRL_SOT23-5
PV: change from MOS to Diode
+5VL 1 2 3 EN BP 4 1 2
R578 @ 10K_0402_5%
2 C185 @ 0.33U_0603_10V7K
GND

1
D
1
1 5 1 2 +3VL_LDO 2 Q51
VIN VOUT 33 DIM_LED
C795 R248 @ 0_0603_5% G 2N7002_SOT23-3
@ 1U_0402_6.3V4Z U55 @ S

3
2

+3VL 1 2
R240 0_0603_5%
SI: Change to +3VL to support Qplay SI2: add 4.7u for
+3VL_LDO
3
bottom boot in BATT mode Cypress cap board 3

+5VS_LED 1 2

T/P Board (Inculde T/P_ON/OFF) PV: change from Q85 to R235

SWITCH BOARD. C502 4.7U_0805_10V4Z
JP36
PV: Change PN to SCA00000G00 for ESD request 1 2
R235 0_0603_5% PV: Add for EMI 1
TP_DATA TP_BTN# +5VALW +5V_TP +5VS_LED 1
33 ON/OFFBTN_LED# 2 2
TP_CLK TP_LED# 0_0402_5% ON/OFFBTN_LED# 3
@ SI2301BDS-T1-E3_SOT23-3 R603 1 R610 1 3
33 ESB_CLK 2 2 KC FBMA-11-100505-301T_0402 CAP_CLK 4 4
3

R604 1 2 R611 1 2 KC FBMA-11-100505-301T_0402 CAP_DAT 5

33 ESB_DAT 5
S

+5V_TP D31 D32

D

3 1 33 I2C_INT 6 6
PSOT24C_SOT23-3 PSOT24C_SOT23-3 0_0402_5% +5VALW_LED 1 2 R_PWR_LED 7
R705 1.8K_0402_5% 7
@ 33 LID_SW# 8 8
Q85 ON/OFF
G

33,35 ON/OFF 9
2

9
1 @ 6,32,33,37 SMB_EC_CK1
R605 1 2 0_0402_5% 10
1

C819 R606 1 0_0402_5% 10

6,32,33,37 SMB_EC_DA1 2 11 11 GND 13
12 12 GND 14
0.1U_0402_16V4Z
2 35,36,42 SYSON#
JP37 ON/OFFBTN_LED# MV:R705 change to 1.8Kohm
1 ON/OFF ACES_85201-1205N
1
2
EMI request @
2 +5VS_LED

2
3 3
4 TP_CLK TP_CLK 33 D38 PV: change to 12pin
4 TP_DATA PSOT24C_SOT23-3 33P_0402_50V8K @ C947 CAP_CLK
@C947
5 5 TP_DATA 33 2 1
6 TP_BTN# TP_BTN# 33 @ 0.1U_0402_16V4Z 2 1 @ C192 +3VL_LDO
@C192
6 TP_LED# 0.1U_0402_16V4Z @C191
@ C191 +5VS_LED
7 7 TP_LED# 33 2 1
8 1 0.1U_0402_16V4Z 2 1 C186 ON/OFFBTN_LED#
@C186
@
8 0.1U_0402_16V4Z @C187
@ C187 I2C_INT
GND 9 1 1 2 1
@ 10 @ 0.1U_0402_16V4Z 2 1 @C188
@ C188 R_PWR_LED
GND C820 C821 0.1U_0402_16V4Z C189 LID_SW#
@C189
@
2 1
4 ACES_85201-08051 100P_0402_50V8J 100P_0402_50V8J 0.047U_0402_16V7K @C190
@ C190 ON/OFF 4
2 1
2 2
@
MV: Add cap for ENE board EMI

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 34 of 46
A B C D E
 A B C D E

Atlas/ Saturn Dock

+DOCKVIN JP38

43 43
44 44
+3VS
16 GREEN_L 40 40 39 39
D43 38 37
16 RED_L 38 37
+5VS 1 2 2 D_DDCDATA 36 35
16 D_DDCDATA 36 35
R586 1K_0402_5% 1 DOCK_PWR_ON 34 33 DOCK_VOL_UP# 2 1
16 BLUE_L 34 33
+3VALW 1 2 3 D_HSYNC 32 31 R589 10K_0402_5%
16 D_HSYNC 32 31
R585 1K_0402_5% D_DDCCLK 30 29 CIR_IN DOCK_VOL_DWN# 2 1
1 16 D_DDCCLK 30 29 CIR_IN 30,33 1
DAN202U_SC70 USB20_N3 28 27 DOCK_PWR_ON R590 10K_0402_5%
20 USB20_N3 28 27

6
D_VSYNC 26 25 MUTELED 1 2 MUTE_LED 33
16 D_VSYNC 26 25

2
Q145A 24 23 DOCK_SLP_BTN# R591 1K_0402_5%
24 23 DOCK_SLP_BTN# 33,34
2N7002DW-7-F_SOT363-6 R588 USB20_P3 22 21
20 USB20_P3 22 21 JACK_DET# 29,30
2 10K_0402_5% 20 19 R_VOL_UP# R567 1 2 200_0402_5% DOCK_VOL_UP# DOCK_VOL_UP# 33
34,36,42 SYSON# 20 19
18 17 R_VOL_DWN# R568 1 2 200_0402_5% DOCK_VOL_DWN# DOCK_VOL_DWN# 33
18 17 SPDIFO_L
16 15

1
16 15 AUDIO_OGND
14 14 13 13
RJ45_MIDI1+ 12 11 DOCK_LOUT_R DOCK_LOUT_R 30
25 RJ45_MIDI1+ 12 11
RJ45_MIDI1- 10 9 DOCK_LOUT_L DOCK_LOUT_L 30
25 RJ45_MIDI1- 10 9
RJ45_MIDI0+ 8 7 DOCK_MIC_R_C
25 RJ45_MIDI0+ 8 7
RJ45_MIDI0- DOCK_MIC_L_C
DOCK_PWR_ON Spec 25 RJ45_MIDI0-
+V_BATTERY
6
4
6 5 5
3 AUDIO_IGND
4 3
0V = Notebook S4/S5, Dock off PJP5 2 2 1 1 DOCK_PRESENT

2.5V = Notebook S3, Dock on B+ 1 2

41 45
4V = Notebook S0, Dock on PAD-OPEN 2x2m 42
41
42
SHIELD
SHIELD 46

FOX_QL1122L-H212AR-7F
@

need change to reverse type connector

+3VL
+1.5VS
2

2
R565
2 R574 2
10K_0402_5%
@ 33_0402_5%
SI2:chang R572 to 22 ohm & R566 to
1

2K to fix dock usb issue CONA# 33

1 1
3

C
Q145B Q7 2 1 2 1 2 SPDIF_OUT 29

220P_0402_50V7K
R572 2N7002DW-7-F_SOT363-6 @ MMBT3904_NL_SOT23-3 B 0.1U_0402_16V7K R647 150_0402_5%

1
DOCK_PRESENT 1 2 22_0402_5% 5 E C894

3
R575 1 R573

C944
DOCK_LOUT_R SPDIFO_L 1 2 110_0402_5%
4
1

DOCK_LOUT_L
R566 1 1

2
0_0402_5% 2

220P_0402_50V7K

220P_0402_50V7K
2K_0402_1%

C942

C943
2

2 2

R_VOL_UP# R_VOL_DWN#

1 1
C843 C844

3 MIC_Dock Need 600 Ohm 500 mA 2

1000P_0402_50V7K
2
1000P_0402_50V7K
3

L94
FBM-11-160808-601-T_0603
29 DOCK_MIC_R 1 2 DOCK_MIC_R_C

29 DOCK_MIC_L 1 2 DOCK_MIC_L_C
L93
FBM-11-160808-601-T_0603 1 1
C922
C921
220P_0402_50V7K 2 2 220P_0402_50V7K

+3VS

10K_0402_5%
2

SENSE_B# 29
R915
2

R914 D
1

10K_0402_5% 2 Q100
G 2N7002_SOT23-3
1

C S
1

2
R912 MMBT3904_NL_SOT23-3 B
1

10K_0402_5% C E Q18
3

DOCK_MIC_L_C 1 2 2 Q16
4 B MMBT3904_NL_SOT23-3 4
2

2 E
3

R913
47K_0402_5% C978
1
1

1U_0603_10V6K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 35 of 46
A B C D E
 A B C D E

Screw Hole
H1 H2 H3 H4
H_4P5X3P0N H_7P0X5P0N H_3P4N 3P0N

@ @ @ @
+5VALW TO +5VS

1
+3VALW TO +3VS
+5VALW +5VS H5 H6 H7 H8 H9 H10 H11 H12 H13 H14
4.7U_0805_10V4Z +3VALW +3VS H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1 1 @ @ @ @ @ @ @ @ @ @
1 Q35 C833 C835 1
1 1

1
8 1 Q14 C839 C838 4.7U_0805_10V4Z
D S
7 D S 2 8 D S 1
2 2
6 D S 3 7 D S 2
2 2 H15 H16 H18 H19
5 D G 4 6 D S 3
1U_0402_6.3V4Z 5 4 H_3P0 H_3P0 H_3P0 H_3P0
SI4800BDY_SO8 D 1U_0402_6.3V4Z G
4.7U_0805_10V4Z

1 SI4800BDY_SO8 RUNON 2 R152 1 B+ @ @ @ @

0.01U_0402_25V7K
4.7U_0805_10V4Z
1 1 750K_0402_1%

1
C864 RUNON

1
C840 D
2 C834 Q17 SUSP
2
2 2 2N7002_SOT23-3
G H21 H22 H23 H24
S 4P0 4P0 4P0 4P0

3
@ @ @ @

1
H27 H25 H33
H_4P0 H_3P0 H_4P0
+1.8V TO +1.8VS @ @ @ CF1 CF2 CF3 CF4
+1.2VALW TO +1.2V_HT 1 1 1 1

1
+1.8V +1.8VS
+1.2VALW +1.2V_HT

Q4 1 2 Q11 1 1
IRF8113PBF_SO8 C848 IRF8113PBF_SO8 C846 C862 4.7U_0805_10V4Z
2 C841 2
8 1 8 1
7 2 10U_0805_10V4Z 7 2 +5VL +5VL
2 1 2 2
6 3 6 3
5 5

1
1U_0402_6.3V4Z 1U_0402_6.3V4Z
4.7U_0805_10V4Z

1 R595 R596
4

4
4.7U_0805_10V4Z 1
C842 2 R233 1 B+ 100K_0402_5% 100K_0402_5%

0.01U_0402_25V7K
C847 1 330K_0402_5%

2
1
2 1.8VS_ENABLE R138 2 SYSON# SUSP
1 B+ 34,35,42 SYSON# SUSP 42

1
2 D
0.01U_0402_25V7K

1 750K_0402_1% R808
1

10M_0402_5% C837 2 Q12 VLDT_EN#

1

R809 D 2 G 2N7002_SOT23-3

6
10M_0402_5% C849 Q13
2 SUSP S
2

3
2 2N7002_SOT23-3
G Q142B Q142A
S 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
2

26,33,40 SYSON 5 2 SUSP# 26,29,33,38,41

SI2: Add this resistor to meet MOS voltage

1
SI2: Add this resistor to meet MOS voltage

Discharge circuit
+5VS +1.8VS +1.2V_HT +1.8V +1.2VALW
3 3
2

2
R239 R279 R280 R284 R368
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% @ 470_0805_5%
1

1
1

D D D D D
SUSP 2 Q46 SUSP 2 Q48 VLDT_EN# 2 Q37 SYSON# 2 Q41 EC_ON# 2 Q42
G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3 G 2N7002_SOT23-3
S S S S S @
3

+5VL +5VL

1
R598
R597 100K_0402_5%
+3VS +0.9V 100K_0402_5%
+1.5VS +1.1VS

2
2

R288 R292 VLDT_EN# EC_ON#

13 VLDT_EN#
470_0805_5% 470_0805_5% R293 R294
470_0805_5% 470_0805_5%

3
1

Q143B
1

2N7002DW-7-F_SOT363-6
1

D D VLDT_EN 2
33 VLDT_EN 5 EC_ON 33,39
1

4 SUSP Q47 SYSON# Q49 D D Q143A 4

2 2
G 2N7002_SOT23-3 G 2N7002_SOT23-3 SUSP 2 Q50 SUSP 2 Q52 2N7002DW-7-F_SOT363-6

4
S S G 2N7002_SOT23-3 G 2N7002_SOT23-3
3

S S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4091P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 36 of 46
A B C D E
 A B C D

+3VL
+3VALW

1
PQ3
TP0610K-T1-E3_SOT23-3

3
PR9
100K_0402_5%

2
BATT
1 2 AC_LED# 33 1

499K_0402_1% 340K_0402_1%
PR1 1
+5VALW
ADP_ID 33

0.01U_0402_50V7K

0.01U_0402_16V7K
2 1

2
1
PD4

1
PC13

PC1
PR8

PR4 1
2K_0402_5% PR2 PC12 820P_0402_50V7K
10K_0402_5%
+DOCKVIN

2
RLZ3.6B_LL34
1

2
ADP_SIGNAL 1 2

8
5 5
4
PR3
10K_0402_5%
VIN 3
PR5
10K_0402_5%

P
4 PL1 PL2 +
3 3 0 1 2 1 BATT_OVP 33
2 SMB3025500YA_2P SMB3025500YA_2P 2
2 -

G
105K_0402_1%
1 ADPIN 1 2 2 1
1

PR6 1
0.01U_0402_25V7K

4
1
PJP1 PU1A

PC6
0.01U_0402_50V7K
@ ACES_88334-057N LM358ADT_SO8

820P_0402_50V7K

2
2

0.01U_0402_50V7K
PD1

2
1

1
PC5
PC2

PC4
PC3
820P_0402_50V7K
2

2
1

2 PJSOT24C_SOT23-3 2

VMB
PL3 BATT
PJP2 SMB3025500YA_2P
1 1 1 2
2 2
3 EC_SMD PD2
PH1 under CPU botten side :
3 EC_SMC @ SM05_SOT23
4 4
5 3
CPU thermal protection at 90 +-3 degree C
5
1

1
6 6
7 2
1 Recovery at 47 +-3 degree C
7 PC9
8 PC8
2

8 1000P_0402_50V7K 0.01U_0402_25V7K PR7

GND 9
10 +5VS 47K_0402_1%
GND
3

3 @ CPU 1 2
3
1

SUYIN_200275MR008GXOLZR
1

1
PD3
1

@ SM24.TC_SOT23-3 PH1
PR14
PR13 100_0402_5% 10K_TH11-3H103FT_0603_1%
100_0402_5%
2

PU1B ENTRIP1 39
2

2
SMB_EC_DA1 SMB_EC_DA1 6,32,33,34 PR10 LM358ADT_SO8

8
15K_0402_1%

1
D
1 2 5

P
SMB_EC_CK1 + PQ1
SMB_EC_CK1 6,32,33,34 0 7 2
1 2 6 G @SSM3K7002FU_SC70-3
-

G
BAT_ID 38 +5VALW PR11 S

3
1 150K_0402_1%

4
1

1
+3VL PC10 PR12
PR16 2.55K_0402_1%
6.49K_0402_1% 0.22U_0603_10V7K PR15
2

1 2 150K_0402_1% PC11
2

2
1000P_0402_50V7K EN0 39

2
1

1
PR17 D
1K_0402_5% 2 PQ2
G SSM3K7002FU_SC70-3
2

3
BATT_TEMP 33
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 37 of 52
A B C D
 A B C D

P4 B+

BATT
VIN P2
PQ102
AM4835EP-T1-PF_SO8

PQ101 PQ103 1 8
1
PR102 PL101 2 7 1
AM4835EP-T1-PF_SO8 AM4835EP-T1-PF_SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
8 1 1 8 1 2 1 2 CHG_B+ 5
7 2 2 7 PR103
6 3 3 6 47K_0402_5%

4
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5 5 1 2 1 2 VIN
PR101

1
47P_0402_50V8J

47K_0402_5% PR104 ACDET PC102

1
PC103

PC104

PC105
0.1U_0603_25V7K
1 2 0_0402_5% 1U_0603_6.3V6M
33 AC_SET 1 2 ACSET

2
1

PR105
PC101

1
DTA144EUA_SC70-3 10K_0402_5%

0.22U_0603_16V7K

PC108
1

1
PQ104
2

2
1
PC109

200K_0402_5%
PC107 PR140

2
100K_0402_5%

PC106

PR106
2 @ 0.01U_0402_16V7K @ 0.1U_0603_25V7K ACOFF#

2
CHG_B+

2
1

CHGEN#

2
PR108

1
PR107 10_1206_5%

1
47K_0402_1% 1 2
1

1 2 2

ACP
LPREF

ACSET

ACDET

LPMD

ACN

CHGEN
TP 29

5
6
7
8
PR110 PC110 2 ACOFF 33
PQ105 0_0402_5% 1U_0805_25V6K
1

D DTC115EUA_SC70-3 26,29,33,36,41 SUSP# 1 2 8 28 1 2

3

IADSLP PVCC

1
2 PQ107 PC111
G 0.1U_0402_10V7K PQ108

3
S PR109 9 27 BST_CHG 1 2 4 AO4466_SO8 PQ106
3

SSM3K7002FU_SC70-3 150K_0402_5% AGND BTST DTC115EUA_SC70-3

PC112 BQ24740VREF PU101
2
PACIN_1 39 1 2 10 BQ24740RHDR_QFN28_5X5 26 DH_CHG BATT
VREF HIDRV PL102 PR112

3
2
1
1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
PR111 11 25 LX_CHG 1 2 1 2
VDAC PH
1

3K_0402_1% D

1
PACIN 1 2 2 PQ109 PD102

5
6
7
8
G SSM3K7002FU_SC70-3 PR113 VADJ 12 24 REGN 2 1
143K_0402_1% VADJ REGN
S
3

ACOFF# PR114 RLS4148_LL34-2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1 2 2

@ 0_0402_5% 13 23 DL_CHG
2
EXTPWR LODRV

1
PD101 33 VCTRL 1 2 PQ110

PC113

PC114

PC115

PC116
RLS4148_LL34-2 4 AO4468_SO8
1

14 22

2
ISYNSET PGND
1

DPMDET
1
PC117 PR115

IADAPT
1 2

SRSET

CELLS

1
1U_0603_10V6K 100K_0402_1% PC119

SRN

SRP
2

3
2
1
BAT
PR116
2

39K_0402_5% 1U_0603_10V6K PC118

2
0.1U_0402_10V7K

15

16

17

18

19

20

21
PR117
100K_0402_5%

IADAPT
PR118
Charge Detector 10K_0402_5%
1 2 BQ24740VREF

1
1 2
33 ADP_I 47K_0402_5%

100P_0402_50V8J
0.22U_0603_10V7K
1

1
PR119

1
D
PC120

PC121

2
PQ111 2 BAT_ID 37
2

2
SSM3K7002FU_SC70-3 G

BATT
S

3
VIN

0.1U_0603_25V7K

0.1U_0603_25V7K
PR120
2 1 IREF 33
2

PC122
PC124
133K_0402_1%

1
PD104 PC123
1

RLS4148_LL34-2 0.1U_0402_10V7K PR122

2
PR121 1M_0402_5%
200K_0402_1% 1 2
1

PR123 @
2

1M_0402_5%
3
1 2 3
VIN_1

PR124
+3VL VIN 1K_0402_5%
VIN
1 2
+3VL AC_IN 21,33
1

1
PR125 PR126
1
10K_0402_5%

47_1206_5% 133K_0402_1% PR127

VIN PR130 10K_0402_1%
1

8
+3VL
10K_0402_1%

PR128

2.15K_0402_1% PU102B
2

2
1 2 5

P
+
1

PR129

7 PACIN
2

O
1

PACIN
100K_0402_5%

PR131 6 -

G
133K_0402_1% PC125 CHGEN#
2

1
PR132

0.1U_0603_25V7K PC126 LM393DG_SO8

PR133
2

1
0.047U_0402_16V7K 10K_0603_0.1%
2

PR134
2

2
1

D PD103
3 10K_0402_5%
P

2
+ PQ112 RLZ4.3B_LL34
O 1 2
1

2 G SSM3K7002FU_SC70-3

2
-
G

PU102A S
PR135
3

LM393DG_SO8 FSTCHG#
4

10K_0603_0.1% PR136
60.4K_0402_1%
2

D VIN_1
1 2
1.24VREF 33 FSTCHG 2 PQ113
G SSM3K7002FU_SC70-3
S
3

STD_ADP 33
PU103

4 REF CATHODE 3 1.24VREF

1 2 ACDET

1
PC127 2
PR137 NC
22P_0402_50V8J
1

100K_0402_1%

4
20K_0402_1% 5 1
4

2
ANODE NC
PR138

LMV431ACM5X_SOT23-5
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 38 of 52
A B C D
 A B C D E

2VREF_51125

0.22U_0603_10V7K

1
1 1

PC302

2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 19.6K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PR305 PR306

1
180K_0402_1% 150K_0402_1%
1

1
PC301

PC303

PC304

PC305

PC313
10U_0805_6.3V6M
1 2 1 2

2
2

5
6
7
8
PC306
PU301

8
7
6
5

ENTRIP2

VREF

ENTRIP1
VFB2

TONSEL

VFB1
25 PQ302
2
P PAD AO4466_SO8 2

2
PQ301
AO4466_SO8 7 24 4
VO2 VO1
4

UG1_5V
PR308 PC308

UG1_3V
8 VREG3 PGOOD 23
PR307 0_0402_5% 0.1U_0402_10V7K
PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

3
2
1
0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
1
2
3

PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303

4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 10U_LF919AS-100M-P3_4.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
8
7
6
5

5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1
+3VL

SKIPSEL

150U_D_6.3VM
OCP=4.594(min)

VREG5
1

VCLK
GND
1

EN0
MOSTemperature Factor=1.3 (100C)

VIN

100K_0402_5%
+
PC309
150U_D_6.3VM

PQ303

1
+

PC310
AO4468_SO8 4 4

13

14

15

16

17

18
2

PR316
TPS51125RGER_QFN24_4X4
2
37 EN0
VL
1
2
3

3
2
1
@
@620K_0402_5%
PQ304

1
FDS6690AS_NL_SO8
1 2 1 2 3/5V_OK 41

PR311

PC311
10U_0805_10V6K
PR312 PR318 0_0402_5%

1
@ 0_0402_5%

2
3 PR317 3
37 ENTRIP1 6 ENTRIP2
0_0402_5% OCP=7.644(min)

2
MOSTemperature Factor=1.3 (100C)

1
B++

0.1U_0603_25V7K
2
PC312
2VREF_51125
1

D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL +5VL
PJP304
2 1
1 2 VL PJP302 PAD-OPEN 2x2m
PR313 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
+5VALWP
PQ308 100K_0402_5%
+3VLP +3VL
1

SSM3K7002FU_SC70-3 D D PQ307
38 PACIN_1 PAD-OPEN 4x4m
1 2 2 2 PJP301
G G EC_ON 33,36 PJP303
2 1
PR315 S S SSM3K7002FU_SC70-3 1 2 +3VALW (3A,120mils ,Via NO.= 6)
3

+3VALWP
1

PC314
0.022U_0603_25V7K

604K_0402_1% PAD-OPEN 2x2m

1

PAD-OPEN 4x4m
2

100K_0402_5%
4 PR314 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 39 of 52
A B C D E
 A B C D

1 1

PL401
PR401
0_0402_5% HCB1608KF-121T30_0603
1 2 1.8V_B+ 1 2 B+
6,33,36 SYSON
1

3300P_0402_50V7-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
PC401

1
@ 1000P_0402_50V7K
2

1
PC408

PC406

PC403

PC404
PC405
680P_0402_50V7K
PC407

2
+5VALW

2
5
6
7
8
BST_1.8V
1+5VALW

1 2 1 2
PQ401
PR404 AO4466_SO8
0_0402_5% 0.1U_0402_10V7K

PR403 DH_1.8V

15

14
2 4 2

1
316_0402_1% PU401
PR405

EN_PSV

TP

VBST
255K_0402_1%
2

1 2 2 13 DH_1.8V_1 1 2 PL402

3
2
1
TON DRVH PR407 2.2UH_PCMC063T-2R2MN_8A_20%
PR406
+1.8VP 2 1 3 12 LX_1.8V 0_0402_5% 1 2 +1.8VP
VOUT LL
0_0402_5%
4 V5FILT TRIP 11 1 2

5
6
7
8

220U_6.3VM_R15
PR408 OCP=9.8913(min)
5 10 +5VALW 14K_0402_1% PR410
VFB V5DRV 4.7_1206_5% 1
MOSTemperature Factor=1.3 (100C)
1

1
PC411 6 9 DL_1.8V PC415
PGOOD DRVL

PGND
+

PC409
1U_0603_10V6K 4.7U_0805_10V6K
GND

2 2
4
2

2
+1.8VP PC410
2
PR411
7

1 2 680P_0603_50V7K

1
14.3K_0603_0.1% TPS51117RGYR_QFN14_3.5x3.5 PQ402

3
2
1
FDS6690AS_NL_SO8
1 2
PC413
@ 10P_0402_50V8J
1

PR409
10K_0603_0.1%
3 3
2

4 4
PJP401

+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 40 of 52
A B C D
 5 4 3 2 1

D D
PR501 PR502 PR503 PR504
11.5K_0402_1% 24.9K_0402_1% 18.7K_0402_1% 11.5K_0402_1%

+1.1VSP 1 2 1 2 2 1 2 1 +1.2VALWP
B+++

B+++

2
PR505 B+++ B+
0_0402_5% PL502

2200P_0402_50V7K
HCB2012KF-121T50_0805
4.7U_0805_25V6-K

4.7U_0805_25V6-K 2 1

1
1

1
PC501

PC516

PC502
2

1.1VS_POK

2200P_0402_50V7K
4.7U_0805_25V6-K
8
7
6
5

5
6
7
8
PC503 PU501
0.022U_0603_25V7K PQ502

VO2

VFB2

TONSEL

GND

VFB1

VO1

1
25 AO4466_SO8

2
P PAD

PC504

PC505
PQ501

2
AO4466_SO8 4 7 24 4
C
PGOOD2 PGOOD1 C
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.1VSP 2 1 2 1 BST_1.1V 9 22 BST_1.2V 2 1 1 2
1
2
3

3
2
1
VBST2 VBST1
+1.2VALWP
PL501 UG1_1.1V 2 1 UG_1.1V 10 21 UG_1.2V 2 1 UG1_1.2V PL503
2.2UH_PCMC063T-2R2MN_8A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 3.3UH_SIQB74B-3R3PF_5.9A_20%
+1.1VSP 2 1 LX_1.1V 11 20 LX_1.2V 0_0402_5% 1 2 +1.2VALWP
LL2 LL1
LG_1.1V 12 19 LG_1.2V
DR VL2 DR VL1
8
7
6
5

5
6
7
8
PC510

PGND2

PGND1
1

V5FILT
TRIP2

TRIP1
PQ504 PR515 1

V5IN
1

2
PC508 + AO4468_SO8

4.7U_0805_6.3V6K
2
220U_D2_4VM PC509 1K_0402_5% +
4.7U_0805_6.3V6K 4 TPS51124RGER_QFN24_4x4 PC511
2

13

14

15

16

17

18
2 220U_6.3VM_R15
4

1
2

1
PQ503

1
FDS6690AS_NL_SO8
1
2
3

PR511 PR512

3
2
1
OCP=9.6(min) 19.1K_0402_1% PR510 0_0402_5%
1 2 19.1K_0402_1% 1 2
MOSTemperature Factor=1.3 (100C) 3/5V_OK 39 OCP=4.487(min)

2
PR513 MOSTemperature Factor=1.3 (100C)
21K_0402_1%
2 1
26,29,33,36,38 SUSP#

1
PC512
B @ 0.1U_0402_10V7K B
1 2 +5VALW

2
PR514
3.3_0402_5%
1

1
PC513 PC514 PC515
0.1U_0402_10V7K 1U_0603_10V6K 4.7U_0805_10V6K
2

PJP501
+1.1VSP 1 2 +1.1VS (6A,240mils ,Via NO.=12)
PAD-OPEN 4x4m

PJP502
+1.2VALWP 1 2 +1.2VALW (4A,160mils ,Via NO.=8)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.1VSP/1.2VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 41 of 52
5 4 3 2 1
 5 4 3 2 1

D D

+1.8V
+1.8V

PU601
1 6 PU603
VIN VCNTL +5VALW

10U_0805_10V6K
1 VIN VCNTL 6 +5VALW

10U_0805_10V6K
2 GND NC 5

PC602
2 GND NC 5

PC609
PC601 3 7
VREF NC

1
10U_0805_10V6K PC613 3 7

2
VREF NC

1
PR601 PC603
4 8 10U_0805_10V6K

2
1K_0402_1% VOUT NC 1U_0603_10V6K PR606 PC612
4 8

2
1K_0402_1% VOUT NC 1U_0603_10V6K
9

2
@ TP @ 9

2
G2992F1U_SO8 TP
G2992F1U_SO8
1 2 VREF1.5V
34,35,36 SYSON#
PR602 +0.9VP

0.1U_0402_10V7K

0.1U_0402_10V7K
0_0402_5%
+1.5VSP

1
PQ601
SSM3K7002FU_SC70-3 PR603 PQ602

1
D

PC604
1K_0402_1% SSM3K7002FU_SC70-3 PR607

1
PC605 D
36 SUSP 1 2 2 5.1K_0402_1%

2
G 10U_0805_10V6K 1 2 2 PC614
PR604 36 SUSP

PC611
@ 0_0402_5% S PR608 G 10U_0805_10V6K

2
1
0_0402_5% S

3
1
C PC606 C

2
@ 0.1U_0402_10V7K PC610

2
@ 0.1U_0402_10V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3 +2.5VSP

B PJP601 +3VS B
2 IN OUT 3
(2A,80mils ,Via NO.= 4)

4.7U_0805_6.3V6K
+0.9VP 1 2 +0.9V 1U_0603_6.3V6M
1

1
GND
PAD-OPEN 3x3m
PC607

PC608
PR605
PJP602 1 @ 150_1206_5%
2

2
+2.5VSP 1 2 +2.5VS (500mA,40mils ,Via NO.= 1)

2
PAD-OPEN 3x3m

PJP603

+1.5VSP 1 2 +1.5VS (1A,40mils ,Via NO.= 2)

PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VSP/2.5VSP/1.5VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 42 of 52
5 4 3 2 1
 5 4 3 2 1

PL201

4.7UH_SIQB74B-4R7PF_4A_20%

+CPU_CORE_NB 2 1

PQ201 PQ202
1
6 VDD_NB_FB_H AO4468_SO8 AO4466_SO8

10U_0805_10V6K
1
+ PC202 1 8 1 8 CPU_B+
220U_B2_2.5VM

PC201
2 7 2 7
3 6 3 6

1
2 5 5 PC204
4.7U_0805_25V6-K

ISL6265_PWROK
6 VDD_NB_FB_L

2
D D

2
PC203
PR203 2200P_0402_50V7K

SSM3K7002FU_SC70-3
PR204 0_0402_5%
22K_0402_1%
1 2

UGATE NB 1
PHASE NB
LGATE NB
1

D
33 VFIX_EN
PQ115

2 1 2
G
S PC205
3

Connect to EC Pin 110. 1000P_0402_50V7K

PR205

0_0402_5%
0_0402_5%
2_0402_5%
+5VS 1 2

1
B+
CPU_B+

1
PC207 PL202

1200P_0402_50V7K
0.1U_0402_10V7K PC206

33P_0402_50V8K
2

1
0.1U_0603_16V7K SMB3025500YA_2P

15.4K_0402_1%
<BOM Structure>

2
1
PC209

PC208
2 1
+5VS

PR207

BOOT_NB1
1

1
PR208

2200P_0402_50V7K

1000P_0402_50V7K
2_0402_5% 1 1

1
820P_0402_50V7K
1 2

3300P_0402_50V7-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

68U_25V_M_R0.44

68U_25V_M_R0.44
CPU_B+

1
+ +

PR206

PR209

PC241

PC242

PC235

PC234

PC212

PC213

PC214

PC240

PC211

PC215
PC210
2.2U_0603_6.3V6K

44.2K_0402_1%

2
1

2
2 2

PR210
PC216 PR211

5
6
7
8
0.1U_0603_25V7K 1_0603_5%
2

D
D
D
D
VSEN_NB

RTN_NB
+5VS
2

2
1 2 PQ203
+3VS PR212

UGATE NB
PHASE NB
LGATE NB

G
S
S
S
0_0402_5% SI4684DY-T1-E3_SO8
1 2

BOOT_NB

4
3
2
1
PR213
C @ 0_0402_5% 2.2_0603_5% 0.22U_0603_10V7K UGATE0_1 C
1 2 PR214 PC217 0.36UH_PCMC104T-R36MN1R17_30A_20%
1
10K_0402_1%

48

47

46

45

44

43

42

41

40

39

38

37
1 2 1 2 2 1 +CPU_CORE_0

5
6
7
8
PR215 PU201

5
6
7
8

1
PR216

@ 10K_0402_5% PL203

4.7_1206_5%

16.5K_0402_1%
VIN

VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB

PR220

PR221
1 2

BOOT0
0_0603_5%
2

PR219

680P_0603_50V7K
1 OFS/VFIXEN BOOT_NB 36
4 PR217

1 2

2
2 35 4 4.02K_0402_1%
33 VGATE PGOOD BOOT0

PC218
PR242 1 100K_0402_5%
2 PQ204 1 2
6,19 H_PWRGD 1 2 ISL6265_PWROK 3 34 UGATE0 FDS6676AS_SO8 PQ205
6,20,33 SB_PWRGD PR234 <BOM Structure>
100K_0402_5% PWROK UGATE0 FDS6676AS_SO8 PC219 1 2

3
2
1

2
1 2 SVD 4 33 PHASE0 0.1U_0603_25V7K

3
2
1
6 CPU_SVD PR218 0_0402_5% SVD PHASE0 ISP 0
1 2 SVC 5 32
6 CPU_SVC PR222 0_0402_5% SVC PGND0
CPU_B+
6 31 LGATE0
33 VR_ON PR223 PR224 ENABLE LGATE0

820P_0402_50V7K
2200P_0402_50V7K

3300P_0402_50V7-K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
6
7
8
1 2 1 2 7 RBIAS PVCC 30

1
PC220

PC221

PC222

PC237

PC236

PC243

PC244
PQ206

D
D
D
D
34.8K_0402_1% 82.5K_0402_1% 8 29 LGATE1 SI4684DY-T1-E3_SO8
OCSET LGATE1

2
PR225 PC223 9 28
VDIFF0 PGND1

G
S
S
S
1 2 1 2 ISL6265IRZ-T_QFN48_6X6
10 27 PHASE1

4
3
2
1
255_0402_1% 4700P_0402_25V7K FB0 PHASE1 PR226
PR227 11 26 UGATE1 1 2 UGATE1_1
COMP0 UGATE1 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
12 25 BOOT1 1 2 1 2 2 1 +CPU_CORE_1
1K_0402_1% VW0 BOOT1 PR228 PL204
COMP1
VDIFF1
VSEN0

VSEN1

5
6
7
8

5
6
7
8

1
RTN0

RTN1

2.2_0603_5% PC224
ISN0

ISN1
ISP0

ISP1
VW1

1
FB1

0.22U_0603_10V7K PR229

16.5K_0402_1%
TP

PR231
PR230 PC225 4.7_1206_5%
1 2 1 2
13

+CPU_CORE_014

15

16

17

18

19

20

21

22

23

24

49

2
54.9K_0402_1% 1200P_0402_50V7K PR232 4 4

2
1 2 1 2 PR233

1
PC227 4.02K_0402_1%
B 180P_0402_50V8J 6.81K_0402_1% +CPU_CORE_1 PQ207 PQ208 PC226 B
1 2
ISP 0

680P_0603_50V7K
3
2
1

3
2
1

2
ISP 1 FDS6676AS_SO8 FDS6676AS_SO8 PC229
1 2 PC230 0.1U_0603_25V7K 1 2
PC228 1000P_0402_50V7K
1000P_0402_50V7K 2 1

PC231
1 2 VSEN0 180P_0402_50V8J ISP 1
6 CPU_VDD0_FB_H PR235 0_0402_5%
1

2 1 2 1
PC238 PR236 PR238
@1000P_0402_50V7K 6.81K_0402_1% 54.9K_0402_1%
2

1 2 RTN0 2 1 2 1
6 CPU_VDD0_FB_L PR237 0_0402_5%
PC232
1 2 RTN1 1200P_0402_50V7K
6 CPU_VDD1_FB_L PR239 0_0402_5% PR240
1

1K_0402_1%
PC239 2 1
@1000P_0402_50V7K
2

1 2 VSEN1 PR243
6 CPU_VDD1_FB_H PR241 0_0402_5% 255_0402_1%
2 1 2 1

4700P_0402_25V7K
PC233

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4091P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 43 of 52

5 4 3 2 1
 A B C D E

Version Change List ( P. I. R. List ) for Power Circuit

Item Page# Date Request Issue Description Rev.
Title Solution Description
Owner
PU401 change the IC from "S IC RT8204PQW WQFN 16P" to
1
1 40 1.8VP 10/23 Compal for power requset "S IC TPS51117RGYR QFN 14P". 1

2 38 Charger 10/30 Compal for power requset PQ104 swap the PQ104 1,3 Pin

3 39 3V/5V 10/30 Compal for power requset Change PR301 to 13.7K modify output voltage

4 39 3V/5V 10/30 Compal for power requset Change PR305 to 180K modify OCP

5 39 3V/5V 10/30 Compal for power requset Change PR306 to 150K modify OCP

6 39 3V/5V 10/30 Compal for power requset Change PR311 to 620K

7 39 3V/5V 10/30 Compal for power requset Change PR315 to 604K modify sequence

8 41 +1.1VSP 10/30 Compal for power requset Change PR510 to 19.1K modify OCP

2
9 41 +1.2VALWP 10/30 Compal for power requset Change PR511 to 19.1K modify OCP 2

10 38 Charger 10/30 Compal for power requset Del PR119

11 43 CPU_CORE 10/30 Compal for power requset Change PC202 to B2 type for ME limit

12 43 CPU_CORE 10/30 Compal for power requset Change PR223 to 17.8K and PR224 to 100K modify OCP

13 43 CPU_CORE 10/30 Compal for power requset Change PR221,PR231 to 16.5K and PR217,PR233 to 4.02K
for CPU_CORE compensation

14 37 DC connector 10/30 Compal for power requset Add PR3,PD4,PC12 for ADP_ID function

15 39 3V/5V 10/30 Compal for power requset Add PR317,PR318

16 38 Charger 10/30 Compal for power requset Change net from +3VLP to +3VL

3 3
17 41 +1.1VSP 10/30 Compal for power requset Change PR513 to 21K for HW power scquence.

18 41 +1.1VSP 11/08 Compal for power requset Change PC508 to D2 size for ME limit.

19 38 Charger 11/09 Compal for power requset Pop PR119 Unpop PR9

20 42 0.9VSP 11/09 Compal for power requset Change PC601,PC605,PC611,PC603,PC613,PC614,PC612,

PC201 for common part

21 38 Charger 11/09 Compal for power requset Change PR112 to 0.015 Ohm

22 51 CPU_CORE 12/05 Compal for EMI requset Add PR220,PR229 for EMI

23 49 CPU_CORE 12/05 Compal for EMI requset Add PC218,PC226 for EMI

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 44 of 52
A B C D E
 A B C D E

Version Change List ( P. I. R. List ) for Power Circuit

Item Page# Date Request Issue Description Rev.
Title Solution Description
45 Owner
Change PR120 to 133K to change charger current
1
1 46 Charger 12/05 Compal for power requset 1

2 47 3V/5V 12/05 Compal for power requset Change PR302 to 30.9K for common part

3 47 3V/5V 12/05 Compal for power requset Change PR304 to 20K for common part

4 48 +1.8VP 12/05 Compal for power requset Change PR408 to 18.2K modify OCP

5 DC Connector 12/25 Compal for power requset Del PR9

/CPU_OTP

6 46 Charger 12/25 Compal for power requset Reconnect from BQ24740VREF to +3VL

7 47 3V/5V 12/25 Compal for power requset Add PU302

8 43 CPU_CORE 12/27 Compal for power requset ADD PC204 & PC211 68uF

2 2
9 48 +1.8VP 1/2 Compal for EMI requset Add PR410 4.7ohm and PC410 680P

10 48 +1.8VP 1/2 Compal for EMI requset Add PC405 680P and 408 3.3nF

11 43 CPU_CORE 1/2 Compal for EMI requset ADD PC241 820p & PC242 3300p

12 52 VGA_CORE 1/2 Compal for EMI requset Add PR710 and PC709

13 43 CPU_CORE 1/2 Compal for EMI requset ADD PC243 to 3.3n PC244 to 820p

14 43 CPU_CORE 1/3 Compal for power requset ADD PR234 & PQ115

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4111P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 45 of 52
A B C D E
 5 4 3 2 1

HW4 Product Improvement Record (P.I.R.)

D D

C C

U3

RS780MN
RS780MN R3
RS780R3@
B B
U15

SB700
SB700 R3
SBR3@

ZZZ

PCB
PCB 03X LA-4091P REV1 M/B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/5/18 Deciphered Date 2008/5/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 19, 2008 Sheet 46 of 46
5 4 3 2 1